1; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after finalize-isel -o %t.mir %s
2; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s
3
4; Test that SIMachineFunctionInfo can be round trip serialized through
5; MIR.
6
7@lds = addrspace(3) global [512 x float] undef, align 4
8
9; CHECK-LABEL: {{^}}name: kernel
10; CHECK: machineFunctionInfo:
11; CHECK-NEXT: explicitKernArgSize: 128
12; CHECK-NEXT: maxKernArgAlign: 64
13; CHECK-NEXT: ldsSize: 0
14; CHECK-NEXT: isEntryFunction: true
15; CHECK-NEXT: noSignedZerosFPMath: false
16; CHECK-NEXT: memoryBound: false
17; CHECK-NEXT: waveLimiter: false
18; CHECK-NEXT: scratchRSrcReg:  '$sgpr96_sgpr97_sgpr98_sgpr99'
19; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr101'
20; CHECK-NEXT: frameOffsetReg:  '$sgpr101'
21; CHECK-NEXT: stackPtrOffsetReg: '$sgpr101'
22; CHECK-NEXT: argumentInfo:
23; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
24; CHECK-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
25; CHECK-NEXT: workGroupIDX: { reg: '$sgpr6' }
26; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' }
27; CHECK-NEXT: workItemIDX: { reg: '$vgpr0' }
28; CHECK-NEXT: mode:
29; CHECK-NEXT: ieee: true
30; CHECK-NEXT: dx10-clamp: true
31; CHECK-NEXT: highBitsOf32BitAddress: 0
32; CHECK-NEXT: body:
33define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) {
34  %gep = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %arg0
35  store float 0.0, float addrspace(3)* %gep, align 4
36  ret void
37}
38
39; CHECK-LABEL: {{^}}name: ps_shader
40; CHECK: machineFunctionInfo:
41; CHECK-NEXT: explicitKernArgSize: 0
42; CHECK-NEXT: maxKernArgAlign: 1
43; CHECK-NEXT: ldsSize: 0
44; CHECK-NEXT: isEntryFunction: true
45; CHECK-NEXT: noSignedZerosFPMath: false
46; CHECK-NEXT: memoryBound: false
47; CHECK-NEXT: waveLimiter: false
48; CHECK-NEXT: scratchRSrcReg:  '$sgpr96_sgpr97_sgpr98_sgpr99'
49; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr101'
50; CHECK-NEXT: frameOffsetReg:  '$sgpr101'
51; CHECK-NEXT: stackPtrOffsetReg: '$sgpr101'
52; CHECK-NEXT: argumentInfo:
53; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr3' }
54; CHECK-NEXT: implicitBufferPtr: { reg: '$sgpr0_sgpr1' }
55; CHECK-NEXT: mode:
56; CHECK-NEXT: ieee: false
57; CHECK-NEXT: dx10-clamp: true
58; CHECK-NEXT: highBitsOf32BitAddress: 0
59; CHECK-NEXT: body:
60define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) {
61  ret void
62}
63
64; CHECK-LABEL: {{^}}name: function
65; CHECK: machineFunctionInfo:
66; CHECK-NEXT: explicitKernArgSize: 0
67; CHECK-NEXT: maxKernArgAlign: 1
68; CHECK-NEXT: ldsSize: 0
69; CHECK-NEXT: isEntryFunction: false
70; CHECK-NEXT: noSignedZerosFPMath: false
71; CHECK-NEXT: memoryBound: false
72; CHECK-NEXT: waveLimiter: false
73; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
74; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr33'
75; CHECK-NEXT: frameOffsetReg: '$sgpr34'
76; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
77; CHECK-NEXT: argumentInfo:
78; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
79; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' }
80; CHECK-NEXT: mode:
81; CHECK-NEXT: ieee: true
82; CHECK-NEXT: dx10-clamp: true
83; CHECK-NEXT: highBitsOf32BitAddress: 0
84; CHECK-NEXT: body:
85define void @function() {
86  ret void
87}
88
89; CHECK-LABEL: {{^}}name: function_nsz
90; CHECK: machineFunctionInfo:
91; CHECK-NEXT: explicitKernArgSize: 0
92; CHECK-NEXT: maxKernArgAlign: 1
93; CHECK-NEXT: ldsSize: 0
94; CHECK-NEXT: isEntryFunction: false
95; CHECK-NEXT: noSignedZerosFPMath: true
96; CHECK-NEXT: memoryBound: false
97; CHECK-NEXT: waveLimiter: false
98; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
99; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr33'
100; CHECK-NEXT: frameOffsetReg: '$sgpr34'
101; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
102; CHECK-NEXT: argumentInfo:
103; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
104; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr33' }
105; CHECK-NEXT: mode:
106; CHECK-NEXT: ieee: true
107; CHECK-NEXT: dx10-clamp: true
108; CHECK-NEXT: highBitsOf32BitAddress: 0
109; CHECK-NEXT: body:
110define void @function_nsz() #0 {
111  ret void
112}
113
114; CHECK-LABEL: {{^}}name: function_dx10_clamp_off
115; CHECK: mode:
116; CHECK-NEXT: ieee: true
117; CHECK-NEXT: dx10-clamp: false
118define void @function_dx10_clamp_off() #1 {
119  ret void
120}
121
122; CHECK-LABEL: {{^}}name: function_ieee_off
123; CHECK: mode:
124; CHECK-NEXT: ieee: false
125; CHECK-NEXT: dx10-clamp: true
126define void @function_ieee_off() #2 {
127  ret void
128}
129
130; CHECK-LABEL: {{^}}name: function_ieee_off_dx10_clamp_off
131; CHECK: mode:
132; CHECK-NEXT: ieee: false
133; CHECK-NEXT: dx10-clamp: false
134define void @function_ieee_off_dx10_clamp_off() #3 {
135  ret void
136}
137
138; CHECK-LABEL: {{^}}name: high_address_bits
139; CHECK: machineFunctionInfo:
140; CHECK: highBitsOf32BitAddress: 4294934528
141define amdgpu_ps void @high_address_bits() #4 {
142  ret void
143}
144
145attributes #0 = { "no-signed-zeros-fp-math" = "true" }
146attributes #1 = { "amdgpu-dx10-clamp" = "false" }
147attributes #2 = { "amdgpu-ieee" = "false" }
148attributes #3 = { "amdgpu-dx10-clamp" = "false" "amdgpu-ieee" = "false" }
149attributes #4 = { "amdgpu-32bit-address-high-bits"="0xffff8000" }
150