19cac4e6dSMatt Arsenault; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after finalize-isel -o %t.mir %s 2bc6d07caSMatt Arsenault; RUN: llc -run-pass=none -verify-machineinstrs %t.mir -o - | FileCheck %s 3bc6d07caSMatt Arsenault 4bc6d07caSMatt Arsenault; Test that SIMachineFunctionInfo can be round trip serialized through 5bc6d07caSMatt Arsenault; MIR. 6bc6d07caSMatt Arsenault 7bc6d07caSMatt Arsenault@lds = addrspace(3) global [512 x float] undef, align 4 8bc6d07caSMatt Arsenault 9bc6d07caSMatt Arsenault; CHECK-LABEL: {{^}}name: kernel 10bc6d07caSMatt Arsenault; CHECK: machineFunctionInfo: 11bc6d07caSMatt Arsenault; CHECK-NEXT: explicitKernArgSize: 128 12bc6d07caSMatt Arsenault; CHECK-NEXT: maxKernArgAlign: 64 13bc6d07caSMatt Arsenault; CHECK-NEXT: ldsSize: 2048 14bc6d07caSMatt Arsenault; CHECK-NEXT: isEntryFunction: true 15bc6d07caSMatt Arsenault; CHECK-NEXT: noSignedZerosFPMath: false 16bc6d07caSMatt Arsenault; CHECK-NEXT: memoryBound: false 17bc6d07caSMatt Arsenault; CHECK-NEXT: waveLimiter: false 18bc6d07caSMatt Arsenault; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99' 19bc6d07caSMatt Arsenault; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr101' 20bc6d07caSMatt Arsenault; CHECK-NEXT: frameOffsetReg: '$sgpr101' 21b812b7a4SMatt Arsenault; CHECK-NEXT: stackPtrOffsetReg: '$sgpr101' 22bc6d07caSMatt Arsenault; CHECK-NEXT: body: 23bc6d07caSMatt Arsenaultdefine amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) { 24bc6d07caSMatt Arsenault %gep = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %arg0 25bc6d07caSMatt Arsenault store float 0.0, float addrspace(3)* %gep, align 4 26bc6d07caSMatt Arsenault ret void 27bc6d07caSMatt Arsenault} 28bc6d07caSMatt Arsenault 29bc6d07caSMatt Arsenault; CHECK-LABEL: {{^}}name: ps_shader 30bc6d07caSMatt Arsenault; CHECK: machineFunctionInfo: 31bc6d07caSMatt Arsenault; CHECK-NEXT: explicitKernArgSize: 0 32bc6d07caSMatt Arsenault; CHECK-NEXT: maxKernArgAlign: 0 33bc6d07caSMatt Arsenault; CHECK-NEXT: ldsSize: 0 34bc6d07caSMatt Arsenault; CHECK-NEXT: isEntryFunction: true 35bc6d07caSMatt Arsenault; CHECK-NEXT: noSignedZerosFPMath: false 36bc6d07caSMatt Arsenault; CHECK-NEXT: memoryBound: false 37bc6d07caSMatt Arsenault; CHECK-NEXT: waveLimiter: false 38bc6d07caSMatt Arsenault; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99' 39bc6d07caSMatt Arsenault; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr101' 40bc6d07caSMatt Arsenault; CHECK-NEXT: frameOffsetReg: '$sgpr101' 41b812b7a4SMatt Arsenault; CHECK-NEXT: stackPtrOffsetReg: '$sgpr101' 42bc6d07caSMatt Arsenault; CHECK-NEXT: body: 43bc6d07caSMatt Arsenaultdefine amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) { 44bc6d07caSMatt Arsenault ret void 45bc6d07caSMatt Arsenault} 46bc6d07caSMatt Arsenault 47bc6d07caSMatt Arsenault; CHECK-LABEL: {{^}}name: function 48bc6d07caSMatt Arsenault; CHECK: machineFunctionInfo: 49bc6d07caSMatt Arsenault; CHECK-NEXT: explicitKernArgSize: 0 50bc6d07caSMatt Arsenault; CHECK-NEXT: maxKernArgAlign: 0 51bc6d07caSMatt Arsenault; CHECK-NEXT: ldsSize: 0 52bc6d07caSMatt Arsenault; CHECK-NEXT: isEntryFunction: false 53bc6d07caSMatt Arsenault; CHECK-NEXT: noSignedZerosFPMath: false 54bc6d07caSMatt Arsenault; CHECK-NEXT: memoryBound: false 55bc6d07caSMatt Arsenault; CHECK-NEXT: waveLimiter: false 56bc6d07caSMatt Arsenault; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' 57*d88db6d7SMatt Arsenault; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr33' 58bc6d07caSMatt Arsenault; CHECK-NEXT: frameOffsetReg: '$sgpr5' 59bc6d07caSMatt Arsenault; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' 60bc6d07caSMatt Arsenault; CHECK-NEXT: body: 61bc6d07caSMatt Arsenaultdefine void @function() { 62bc6d07caSMatt Arsenault ret void 63bc6d07caSMatt Arsenault} 64bc6d07caSMatt Arsenault 65bc6d07caSMatt Arsenault; CHECK-LABEL: {{^}}name: function_nsz 66bc6d07caSMatt Arsenault; CHECK: machineFunctionInfo: 67bc6d07caSMatt Arsenault; CHECK-NEXT: explicitKernArgSize: 0 68bc6d07caSMatt Arsenault; CHECK-NEXT: maxKernArgAlign: 0 69bc6d07caSMatt Arsenault; CHECK-NEXT: ldsSize: 0 70bc6d07caSMatt Arsenault; CHECK-NEXT: isEntryFunction: false 71bc6d07caSMatt Arsenault; CHECK-NEXT: noSignedZerosFPMath: true 72bc6d07caSMatt Arsenault; CHECK-NEXT: memoryBound: false 73bc6d07caSMatt Arsenault; CHECK-NEXT: waveLimiter: false 74bc6d07caSMatt Arsenault; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' 75*d88db6d7SMatt Arsenault; CHECK-NEXT: scratchWaveOffsetReg: '$sgpr33' 76bc6d07caSMatt Arsenault; CHECK-NEXT: frameOffsetReg: '$sgpr5' 77bc6d07caSMatt Arsenault; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' 78bc6d07caSMatt Arsenault; CHECK-NEXT: body: 79bc6d07caSMatt Arsenaultdefine void @function_nsz() #0 { 80bc6d07caSMatt Arsenault ret void 81bc6d07caSMatt Arsenault} 82bc6d07caSMatt Arsenault 83bc6d07caSMatt Arsenaultattributes #0 = { "no-signed-zeros-fp-math" = "true" } 84