1; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -amdgpu-spill-sgpr-to-vgpr=0 -stop-after prologepilog -verify-machineinstrs %s -o - | FileCheck -check-prefix=AFTER-PEI %s
2
3; Test that the ScavengeFI is serialized in the SIMachineFunctionInfo.
4
5; AFTER-PEI-LABEL: {{^}}name: scavenge_fi
6; AFTER-PEI: machineFunctionInfo:
7; AFTER-PEI-NEXT: explicitKernArgSize: 12
8; AFTER-PEI-NEXT: maxKernArgAlign: 8
9; AFTER-PEI-NEXT: ldsSize:         0
10; AFTER-PEI-NEXT: dynLDSAlign:     1
11; AFTER-PEI-NEXT: isEntryFunction: true
12; AFTER-PEI-NEXT: noSignedZerosFPMath: false
13; AFTER-PEI-NEXT: memoryBound:     false
14; AFTER-PEI-NEXT: waveLimiter:     false
15; AFTER-PEI-NEXT: hasSpilledSGPRs: true
16; AFTER-PEI-NEXT: hasSpilledVGPRs: false
17; AFTER-PEI-NEXT: scratchRSrcReg:  '$sgpr68_sgpr69_sgpr70_sgpr71'
18; AFTER-PEI-NEXT: frameOffsetReg:  '$fp_reg'
19; AFTER-PEI-NEXT: stackPtrOffsetReg: '$sgpr32'
20; AFTER-PEI-NEXT: argumentInfo:
21; AFTER-PEI-NEXT:   privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
22; AFTER-PEI-NEXT:   kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
23; AFTER-PEI-NEXT:   workGroupIDX:    { reg: '$sgpr6' }
24; AFTER-PEI-NEXT:   privateSegmentWaveByteOffset: { reg: '$sgpr7' }
25; AFTER-PEI-NEXT:   workItemIDX:     { reg: '$vgpr0' }
26; AFTER-PEI-NEXT: mode:
27; AFTER-PEI-NEXT:   ieee:            true
28; AFTER-PEI-NEXT:   dx10-clamp:      true
29; AFTER-PEI-NEXT:   fp32-input-denormals: true
30; AFTER-PEI-NEXT:   fp32-output-denormals: true
31; AFTER-PEI-NEXT:   fp64-fp16-input-denormals: true
32; AFTER-PEI-NEXT:   fp64-fp16-output-denormals: true
33; AFTER-PEI-NEXT: highBitsOf32BitAddress: 0
34; AFTER-PEI-NEXT: occupancy: 5
35; AFTER-PEI-NEXT: scavengeFI: '%fixed-stack.0'
36; AFTER-PEI-NEXT: body:
37define amdgpu_kernel void @scavenge_fi(i32 addrspace(1)* %out, i32 %in) #0 {
38  %wide.sgpr0 = call <32 x i32>  asm sideeffect "; def $0", "=s" () #0
39  %wide.sgpr1 = call <32 x i32>  asm sideeffect "; def $0", "=s" () #0
40  %wide.sgpr2 = call <32 x i32>  asm sideeffect "; def $0", "=s" () #0
41  %wide.sgpr3 = call <32 x i32>  asm sideeffect "; def $0", "=s" () #0
42
43  call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr0) #0
44  call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr1) #0
45  call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr2) #0
46  call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr3) #0
47  ret void
48}
49
50attributes #0 = { nounwind }
51