1; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -amdgpu-spill-sgpr-to-vgpr=0 -stop-after prologepilog -verify-machineinstrs %s -o - | FileCheck -check-prefix=AFTER-PEI %s
2
3; Test that the ScavengeFI is serialized in the SIMachineFunctionInfo.
4
5; AFTER-PEI-LABEL: {{^}}name: scavenge_fi
6; AFTER-PEI: machineFunctionInfo:
7; AFTER-PEI-NEXT: explicitKernArgSize: 12
8; AFTER-PEI-NEXT: maxKernArgAlign: 8
9; AFTER-PEI-NEXT: ldsSize:         0
10; AFTER-PEI-NEXT: gdsSize:         0
11; AFTER-PEI-NEXT: dynLDSAlign:     1
12; AFTER-PEI-NEXT: isEntryFunction: true
13; AFTER-PEI-NEXT: noSignedZerosFPMath: false
14; AFTER-PEI-NEXT: memoryBound:     false
15; AFTER-PEI-NEXT: waveLimiter:     false
16; AFTER-PEI-NEXT: hasSpilledSGPRs: true
17; AFTER-PEI-NEXT: hasSpilledVGPRs: false
18; AFTER-PEI-NEXT: scratchRSrcReg:  '$sgpr68_sgpr69_sgpr70_sgpr71'
19; AFTER-PEI-NEXT: frameOffsetReg:  '$fp_reg'
20; AFTER-PEI-NEXT: stackPtrOffsetReg: '$sgpr32'
21; AFTER-PEI-NEXT: bytesInStackArgArea: 0
22; AFTER-PEI-NEXT: returnsVoid: true
23; AFTER-PEI-NEXT: argumentInfo:
24; AFTER-PEI-NEXT:   privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
25; AFTER-PEI-NEXT:   kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
26; AFTER-PEI-NEXT:   workGroupIDX:    { reg: '$sgpr6' }
27; AFTER-PEI-NEXT:   privateSegmentWaveByteOffset: { reg: '$sgpr7' }
28; AFTER-PEI-NEXT:   workItemIDX:     { reg: '$vgpr0' }
29; AFTER-PEI-NEXT: mode:
30; AFTER-PEI-NEXT:   ieee:            true
31; AFTER-PEI-NEXT:   dx10-clamp:      true
32; AFTER-PEI-NEXT:   fp32-input-denormals: true
33; AFTER-PEI-NEXT:   fp32-output-denormals: true
34; AFTER-PEI-NEXT:   fp64-fp16-input-denormals: true
35; AFTER-PEI-NEXT:   fp64-fp16-output-denormals: true
36; AFTER-PEI-NEXT: highBitsOf32BitAddress: 0
37; AFTER-PEI-NEXT: occupancy: 5
38; AFTER-PEI-NEXT: scavengeFI: '%fixed-stack.0'
39; AFTER-PEI-NEXT: vgprForAGPRCopy: ''
40; AFTER-PEI-NEXT: body:
41define amdgpu_kernel void @scavenge_fi(i32 addrspace(1)* %out, i32 %in) #0 {
42  %wide.sgpr0 = call <32 x i32>  asm sideeffect "; def $0", "=s" () #0
43  %wide.sgpr1 = call <32 x i32>  asm sideeffect "; def $0", "=s" () #0
44  %wide.sgpr2 = call <32 x i32>  asm sideeffect "; def $0", "=s" () #0
45  %wide.sgpr3 = call <32 x i32>  asm sideeffect "; def $0", "=s" () #0
46
47  call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr0) #0
48  call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr1) #0
49  call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr2) #0
50  call void asm sideeffect "; use $0", "s"(<32 x i32> %wide.sgpr3) #0
51  ret void
52}
53
54attributes #0 = { nounwind }
55