1; RUN: llc -march=hexagon < %s | FileCheck %s
2
3; Make sure we generate 3 aligned stores.
4; CHECK: vmem({{.*}}) =
5; CHECK: vmem({{.*}}) =
6; CHECK: vmem({{.*}}) =
7; CHECK-NOT: vmem
8
9define void @f0(i16* %a0, i32 %a11, <64 x i16> %a22, <64 x i16> %a3) #0 {
10b0:
11  %v0 = add i32 %a11, 64
12  %v1 = getelementptr i16, i16* %a0, i32 %v0
13  %v2 = bitcast i16* %v1 to <64 x i16>*
14  store <64 x i16> %a22, <64 x i16>* %v2, align 2
15  %v33 = add i32 %a11, 128
16  %v44 = getelementptr i16, i16* %a0, i32 %v33
17  %v5 = bitcast i16* %v44 to <64 x i16>*
18  store <64 x i16> %a3, <64 x i16>* %v5, align 2
19  ret void
20}
21
22attributes #0 = { nounwind "target-cpu"="hexagonv66" "target-features"="+hvx,+hvx-length128b" }
23