1; RUN: llc -march=hexagon < %s | FileCheck %s
2
3; CHECK-LABEL: f0:
4; CHECK: vmemu
5; CHECK: vmux
6define <128 x i8> @f0(<128 x i8>* %a0, i32 %a1, i32 %a2) #0 {
7  %q0 = call <128 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32 %a2)
8  %v0 = call <32 x i32> @llvm.hexagon.V6.lvsplatb.128B(i32 %a1)
9  %v1 = bitcast <32 x i32> %v0 to <128 x i8>
10  %v2 = call <128 x i8> @llvm.masked.load.v128i8.p0v128i8(<128 x i8>* %a0, i32 4, <128 x i1> %q0, <128 x i8> %v1)
11  ret <128 x i8> %v2
12}
13
14; CHECK-LABEL: f1:
15; CHECK: vlalign
16; CHECK: if (q{{.}}) vmem{{.*}} = v
17define void @f1(<128 x i8>* %a0, i32 %a1, i32 %a2) #0 {
18  %q0 = call <128 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32 %a2)
19  %v0 = call <32 x i32> @llvm.hexagon.V6.lvsplatb.128B(i32 %a1)
20  %v1 = bitcast <32 x i32> %v0 to <128 x i8>
21  call void @llvm.masked.store.v128i8.p0v128i8(<128 x i8> %v1, <128 x i8>* %a0, i32 4, <128 x i1> %q0)
22  ret void
23}
24
25declare <128 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32) #1
26declare <32 x i32> @llvm.hexagon.V6.lvsplatb.128B(i32) #1
27declare <128 x i8> @llvm.masked.load.v128i8.p0v128i8(<128 x i8>*, i32 immarg, <128 x i1>, <128 x i8>) #2
28declare void @llvm.masked.store.v128i8.p0v128i8(<128 x i8>, <128 x i8>*, i32 immarg, <128 x i1>) #2
29
30attributes #0 = { "target-cpu"="hexagonv65" "target-features"="+hvx,+hvx-length128b" }
31attributes #1 = { nounwind readnone }
32attributes #2 = { argmemonly nounwind readonly willreturn }
33attributes #3 = { argmemonly nounwind willreturn }
34
35
36