1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=hexagon < %s | FileCheck %s
3
4define <32 x i32> @fred(i32 %a0) #0 {
5; CHECK-LABEL: fred:
6; CHECK:         .cfi_startproc
7; CHECK-NEXT:  // %bb.0:
8; CHECK-NEXT:    {
9; CHECK-NEXT:     r3:2 = combine(#20,#9)
10; CHECK-NEXT:     v0 = vxor(v0,v0)
11; CHECK-NEXT:     r1 = #24
12; CHECK-NEXT:     r4 = #12
13; CHECK-NEXT:    }
14; CHECK-NEXT:    {
15; CHECK-NEXT:     v1 = vror(v0,r1)
16; CHECK-NEXT:    }
17; CHECK-NEXT:    {
18; CHECK-NEXT:     v1.w = vinsert(r2)
19; CHECK-NEXT:     r4 = #7
20; CHECK-NEXT:     r2 = #116
21; CHECK-NEXT:     v0 = vror(v0,r4)
22; CHECK-NEXT:    }
23; CHECK-NEXT:    {
24; CHECK-NEXT:     v0.w = vinsert(r4)
25; CHECK-NEXT:    }
26; CHECK-NEXT:    {
27; CHECK-NEXT:     v1 = vror(v1,r3)
28; CHECK-NEXT:    }
29; CHECK-NEXT:    {
30; CHECK-NEXT:     v1.w = vinsert(r0)
31; CHECK-NEXT:     v0 = vror(v0,r2)
32; CHECK-NEXT:    }
33; CHECK-NEXT:    {
34; CHECK-NEXT:     v1 = vror(v1,r3)
35; CHECK-NEXT:    }
36; CHECK-NEXT:    {
37; CHECK-NEXT:     v0 = vor(v0,v1)
38; CHECK-NEXT:     jumpr r31
39; CHECK-NEXT:    }
40  %v0 = insertelement <32 x i32> undef, i32 undef, i32 0
41  %v1 = insertelement <32 x i32> %v0, i32 undef, i32 1
42  %v2 = insertelement <32 x i32> %v1, i32 undef, i32 2
43  %v3 = insertelement <32 x i32> %v2, i32 7, i32 3
44  %v4 = insertelement <32 x i32> %v3, i32 undef, i32 4
45  %v5 = insertelement <32 x i32> %v4, i32 undef, i32 5
46  %v6 = insertelement <32 x i32> %v5, i32 undef, i32 6
47  %v7 = insertelement <32 x i32> %v6, i32 undef, i32 7
48  %v8 = insertelement <32 x i32> %v7, i32 undef, i32 8
49  %v9 = insertelement <32 x i32> %v8, i32 undef, i32 9
50  %v10 = insertelement <32 x i32> %v9, i32 undef, i32 10
51  %v11 = insertelement <32 x i32> %v10, i32 undef, i32 11
52  %v12 = insertelement <32 x i32> %v11, i32 undef, i32 12
53  %v13 = insertelement <32 x i32> %v12, i32 undef, i32 13
54  %v14 = insertelement <32 x i32> %v13, i32 undef, i32 14
55  %v15 = insertelement <32 x i32> %v14, i32 undef, i32 15
56  %v16 = insertelement <32 x i32> %v15, i32 undef, i32 16
57  %v17 = insertelement <32 x i32> %v16, i32 undef, i32 17
58  %v18 = insertelement <32 x i32> %v17, i32 undef, i32 18
59  %v19 = insertelement <32 x i32> %v18, i32 undef, i32 19
60  %v20 = insertelement <32 x i32> %v19, i32 undef, i32 20
61  %v21 = insertelement <32 x i32> %v20, i32 undef, i32 21
62  %v22 = insertelement <32 x i32> %v21, i32 9, i32 22
63  %v23 = insertelement <32 x i32> %v22, i32 undef, i32 23
64  %v24 = insertelement <32 x i32> %v23, i32 undef, i32 24
65  %v25 = insertelement <32 x i32> %v24, i32 undef, i32 25
66  %v26 = insertelement <32 x i32> %v25, i32 undef, i32 26
67  %v27 = insertelement <32 x i32> %v26, i32 %a0, i32 27
68  %v28 = insertelement <32 x i32> %v27, i32 undef, i32 28
69  %v29 = insertelement <32 x i32> %v28, i32 undef, i32 29
70  %v30 = insertelement <32 x i32> %v29, i32 undef, i32 30
71  %v31 = insertelement <32 x i32> %v30, i32 undef, i32 31
72  ret <32 x i32> %v31
73}
74
75attributes #0 = { "target-cpu"="hexagonv66" "target-features"="+hvx,+hvx-length128b" }
76
77