1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=hexagon < %s | FileCheck %s
3
4define <64 x half> @f0(<64 x float> %a0) #0 {
5; CHECK-LABEL: f0:
6; CHECK:       // %bb.0: // %b0
7; CHECK-NEXT:    {
8; CHECK-NEXT:     v2 = vxor(v2,v2)
9; CHECK-NEXT:    }
10; CHECK-NEXT:    {
11; CHECK-NEXT:     v0.qf32 = vadd(v0.sf,v2.sf)
12; CHECK-NEXT:    }
13; CHECK-NEXT:    {
14; CHECK-NEXT:     v1.qf32 = vadd(v1.sf,v2.sf)
15; CHECK-NEXT:    }
16; CHECK-NEXT:    {
17; CHECK-NEXT:     v0.hf = v1:0.qf32
18; CHECK-NEXT:    }
19; CHECK-NEXT:    {
20; CHECK-NEXT:     v0.h = vdeal(v0.h)
21; CHECK-NEXT:     jumpr r31
22; CHECK-NEXT:    }
23b0:
24  %v0 = fptrunc <64 x float> %a0 to <64 x half>
25  ret <64 x half> %v0
26}
27
28define <64 x float> @f1(<64 x half> %a0) #0 {
29; CHECK-LABEL: f1:
30; CHECK:       // %bb.0: // %b0
31; CHECK-NEXT:    {
32; CHECK-NEXT:     r0 = #15360
33; CHECK-NEXT:     r7 = #-4
34; CHECK-NEXT:    }
35; CHECK-NEXT:    {
36; CHECK-NEXT:     v1.h = vsplat(r0)
37; CHECK-NEXT:    }
38; CHECK-NEXT:    {
39; CHECK-NEXT:     v1:0.qf32 = vmpy(v0.hf,v1.hf)
40; CHECK-NEXT:    }
41; CHECK-NEXT:    {
42; CHECK-NEXT:     v0.sf = v0.qf32
43; CHECK-NEXT:    }
44; CHECK-NEXT:    {
45; CHECK-NEXT:     v1.sf = v1.qf32
46; CHECK-NEXT:    }
47; CHECK-NEXT:    {
48; CHECK-NEXT:     v1:0 = vshuff(v1,v0,r7)
49; CHECK-NEXT:     jumpr r31
50; CHECK-NEXT:    }
51b0:
52  %v0 = fpext <64 x half> %a0 to <64 x float>
53  ret <64 x float> %v0
54}
55
56define <64 x half> @f2(<64 x float> %a0) #1 {
57; CHECK-LABEL: f2:
58; CHECK:       // %bb.0: // %b0
59; CHECK-NEXT:    {
60; CHECK-NEXT:     v0.hf = vcvt(v1.sf,v0.sf)
61; CHECK-NEXT:    }
62; CHECK-NEXT:    {
63; CHECK-NEXT:     v0.h = vdeal(v0.h)
64; CHECK-NEXT:     jumpr r31
65; CHECK-NEXT:    }
66b0:
67  %v0 = fptrunc <64 x float> %a0 to <64 x half>
68  ret <64 x half> %v0
69}
70
71define <64 x float> @f3(<64 x half> %a0) #1 {
72; CHECK-LABEL: f3:
73; CHECK:       // %bb.0: // %b0
74; CHECK-NEXT:    {
75; CHECK-NEXT:     v0.h = vshuff(v0.h)
76; CHECK-NEXT:    }
77; CHECK-NEXT:    {
78; CHECK-NEXT:     v1:0.sf = vcvt(v0.hf)
79; CHECK-NEXT:     jumpr r31
80; CHECK-NEXT:    }
81b0:
82  %v0 = fpext <64 x half> %a0 to <64 x float>
83  ret <64 x float> %v0
84}
85
86attributes #0 = { nounwind "target-features"="+hvxv69,+hvx-length128b,+hvx-qfloat" }
87attributes #1 = { nounwind "target-features"="+hvxv69,+hvx-length128b,+hvx-ieee-fp,-hvx-qfloat" }
88