1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -march=hexagon < %s | FileCheck %s 3 4define <64 x half> @f0(<64 x half> %a0, <64 x half> %a1) #0 { 5; CHECK-LABEL: f0: 6; CHECK: // %bb.0: // %b0 7; CHECK-NEXT: { 8; CHECK-NEXT: v0.qf16 = vadd(v0.hf,v1.hf) 9; CHECK-NEXT: } 10; CHECK-NEXT: { 11; CHECK-NEXT: v0.hf = v0.qf16 12; CHECK-NEXT: jumpr r31 13; CHECK-NEXT: } 14b0: 15 %v0 = fadd <64 x half> %a0, %a1 16 ret <64 x half> %v0 17} 18 19define <32 x float> @f1(<32 x float> %a0, <32 x float> %a1) #0 { 20; CHECK-LABEL: f1: 21; CHECK: // %bb.0: // %b0 22; CHECK-NEXT: { 23; CHECK-NEXT: v0.qf32 = vadd(v0.sf,v1.sf) 24; CHECK-NEXT: } 25; CHECK-NEXT: { 26; CHECK-NEXT: v0.sf = v0.qf32 27; CHECK-NEXT: jumpr r31 28; CHECK-NEXT: } 29b0: 30 %v0 = fadd <32 x float> %a0, %a1 31 ret <32 x float> %v0 32} 33 34define <64 x half> @f2(<64 x half> %a0, <64 x half> %a1) #0 { 35; CHECK-LABEL: f2: 36; CHECK: // %bb.0: // %b0 37; CHECK-NEXT: { 38; CHECK-NEXT: v0.qf16 = vsub(v0.hf,v1.hf) 39; CHECK-NEXT: } 40; CHECK-NEXT: { 41; CHECK-NEXT: v0.hf = v0.qf16 42; CHECK-NEXT: jumpr r31 43; CHECK-NEXT: } 44b0: 45 %v0 = fsub <64 x half> %a0, %a1 46 ret <64 x half> %v0 47} 48 49define <32 x float> @f3(<32 x float> %a0, <32 x float> %a1) #0 { 50; CHECK-LABEL: f3: 51; CHECK: // %bb.0: // %b0 52; CHECK-NEXT: { 53; CHECK-NEXT: v0.qf32 = vsub(v0.sf,v1.sf) 54; CHECK-NEXT: } 55; CHECK-NEXT: { 56; CHECK-NEXT: v0.sf = v0.qf32 57; CHECK-NEXT: jumpr r31 58; CHECK-NEXT: } 59b0: 60 %v0 = fsub <32 x float> %a0, %a1 61 ret <32 x float> %v0 62} 63 64define <64 x half> @f4(<64 x half> %a0, <64 x half> %a1) #0 { 65; CHECK-LABEL: f4: 66; CHECK: // %bb.0: // %b0 67; CHECK-NEXT: { 68; CHECK-NEXT: v0.qf16 = vmpy(v0.hf,v1.hf) 69; CHECK-NEXT: } 70; CHECK-NEXT: { 71; CHECK-NEXT: v0.hf = v0.qf16 72; CHECK-NEXT: jumpr r31 73; CHECK-NEXT: } 74b0: 75 %v0 = fmul <64 x half> %a0, %a1 76 ret <64 x half> %v0 77} 78 79define <32 x float> @f5(<32 x float> %a0, <32 x float> %a1) #0 { 80; CHECK-LABEL: f5: 81; CHECK: // %bb.0: // %b0 82; CHECK-NEXT: { 83; CHECK-NEXT: v0.qf32 = vmpy(v0.sf,v1.sf) 84; CHECK-NEXT: } 85; CHECK-NEXT: { 86; CHECK-NEXT: v0.sf = v0.qf32 87; CHECK-NEXT: jumpr r31 88; CHECK-NEXT: } 89b0: 90 %v0 = fmul <32 x float> %a0, %a1 91 ret <32 x float> %v0 92} 93 94define <64 x half> @f6(<64 x half> %a0, <64 x half> %a1) #1 { 95; CHECK-LABEL: f6: 96; CHECK: // %bb.0: // %b0 97; CHECK-NEXT: { 98; CHECK-NEXT: v0.hf = vadd(v0.hf,v1.hf) 99; CHECK-NEXT: jumpr r31 100; CHECK-NEXT: } 101b0: 102 %v0 = fadd <64 x half> %a0, %a1 103 ret <64 x half> %v0 104} 105 106define <32 x float> @f7(<32 x float> %a0, <32 x float> %a1) #1 { 107; CHECK-LABEL: f7: 108; CHECK: // %bb.0: // %b0 109; CHECK-NEXT: { 110; CHECK-NEXT: v0.sf = vadd(v0.sf,v1.sf) 111; CHECK-NEXT: jumpr r31 112; CHECK-NEXT: } 113b0: 114 %v0 = fadd <32 x float> %a0, %a1 115 ret <32 x float> %v0 116} 117 118define <64 x half> @f8(<64 x half> %a0, <64 x half> %a1) #1 { 119; CHECK-LABEL: f8: 120; CHECK: // %bb.0: // %b0 121; CHECK-NEXT: { 122; CHECK-NEXT: v0.hf = vsub(v0.hf,v1.hf) 123; CHECK-NEXT: jumpr r31 124; CHECK-NEXT: } 125b0: 126 %v0 = fsub <64 x half> %a0, %a1 127 ret <64 x half> %v0 128} 129 130define <32 x float> @f9(<32 x float> %a0, <32 x float> %a1) #1 { 131; CHECK-LABEL: f9: 132; CHECK: // %bb.0: // %b0 133; CHECK-NEXT: { 134; CHECK-NEXT: v0.sf = vsub(v0.sf,v1.sf) 135; CHECK-NEXT: jumpr r31 136; CHECK-NEXT: } 137b0: 138 %v0 = fsub <32 x float> %a0, %a1 139 ret <32 x float> %v0 140} 141 142define <64 x half> @f10(<64 x half> %a0, <64 x half> %a1) #1 { 143; CHECK-LABEL: f10: 144; CHECK: // %bb.0: // %b0 145; CHECK-NEXT: { 146; CHECK-NEXT: v0.hf = vmpy(v0.hf,v1.hf) 147; CHECK-NEXT: jumpr r31 148; CHECK-NEXT: } 149b0: 150 %v0 = fmul <64 x half> %a0, %a1 151 ret <64 x half> %v0 152} 153 154define <32 x float> @f11(<32 x float> %a0, <32 x float> %a1) #1 { 155; CHECK-LABEL: f11: 156; CHECK: // %bb.0: // %b0 157; CHECK-NEXT: { 158; CHECK-NEXT: v0.sf = vmpy(v0.sf,v1.sf) 159; CHECK-NEXT: jumpr r31 160; CHECK-NEXT: } 161b0: 162 %v0 = fmul <32 x float> %a0, %a1 163 ret <32 x float> %v0 164} 165 166attributes #0 = { nounwind "target-cpu"="hexagonv69" "target-features"="+hvxv69,+hvx-length128b,+hvx-qfloat" } 167attributes #1 = { nounwind "target-cpu"="hexagonv69" "target-features"="+hvxv69,+hvx-length128b,+hvx-ieee-fp" } 168