1; RUN: llc < %s -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 | FileCheck %s
2
3; Hexagon runs passes that renumber the basic blocks, causing this test
4; to fail.
5; XFAIL: hexagon
6
7; Bug: PR31899
8; XFAIL: avr
9
10declare void @foo()
11
12; Make sure we have the correct weight attached to each successor.
13define i32 @test2(i32 %x) nounwind uwtable readnone ssp {
14; CHECK-LABEL: Machine code for function test2:
15entry:
16  %conv = sext i32 %x to i64
17  switch i64 %conv, label %return [
18    i64 0, label %sw.bb
19    i64 1, label %sw.bb
20    i64 4, label %sw.bb
21    i64 5, label %sw.bb1
22  ], !prof !0
23; CHECK: BB#0: derived from LLVM BB %entry
24; CHECK: Successors according to CFG: BB#2({{[0-9a-fx/= ]+}}75.29%) BB#4({{[0-9a-fx/= ]+}}24.71%)
25; CHECK: BB#4: derived from LLVM BB %entry
26; CHECK: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}47.62%) BB#5({{[0-9a-fx/= ]+}}52.38%)
27; CHECK: BB#5: derived from LLVM BB %entry
28; CHECK: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}36.36%) BB#3({{[0-9a-fx/= ]+}}63.64%)
29
30sw.bb:
31; this call will prevent simplifyCFG from optimizing the block away in ARM/AArch64.
32  tail call void @foo()
33  br label %return
34
35sw.bb1:
36  br label %return
37
38return:
39  %retval.0 = phi i32 [ 5, %sw.bb1 ], [ 1, %sw.bb ], [ 0, %entry ]
40  ret i32 %retval.0
41}
42
43!0 = !{!"branch_weights", i32 7, i32 6, i32 4, i32 4, i32 64}
44
45
46declare void @g(i32)
47define void @left_leaning_weight_balanced_tree(i32 %x) {
48entry:
49  switch i32 %x, label %return [
50    i32 0,  label %bb0
51    i32 100, label %bb1
52    i32 200, label %bb2
53    i32 300, label %bb3
54    i32 400, label %bb4
55    i32 500, label %bb5
56  ], !prof !1
57bb0: tail call void @g(i32 0) br label %return
58bb1: tail call void @g(i32 1) br label %return
59bb2: tail call void @g(i32 2) br label %return
60bb3: tail call void @g(i32 3) br label %return
61bb4: tail call void @g(i32 4) br label %return
62bb5: tail call void @g(i32 5) br label %return
63return: ret void
64
65; Check that we set branch weights on the pivot cmp instruction correctly.
66; Cases {0,10,20,30} go on the left with weight 13; cases {40,50} go on the
67; right with weight 20.
68;
69; CHECK-LABEL: Machine code for function left_leaning_weight_balanced_tree:
70; CHECK: BB#0: derived from LLVM BB %entry
71; CHECK-NOT: Successors
72; CHECK: Successors according to CFG: BB#8({{[0-9a-fx/= ]+}}39.71%) BB#9({{[0-9a-fx/= ]+}}60.29%)
73}
74
75!1 = !{!"branch_weights",
76  ; Default:
77  i32 1,
78  ; Case 0, 100, 200:
79  i32 10, i32 1, i32 1,
80  ; Case 300, 400, 500:
81  i32 1, i32 10, i32 10}
82