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Revision tags: llvmorg-20.1.0, llvmorg-20.1.0-rc3, llvmorg-20.1.0-rc2, llvmorg-20.1.0-rc1, llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4, llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init, llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7, llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init, llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4, llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1, llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3, llvmorg-14.0.0-rc2, llvmorg-14.0.0-rc1, llvmorg-15-init, llvmorg-13.0.1, llvmorg-13.0.1-rc3, llvmorg-13.0.1-rc2, llvmorg-13.0.1-rc1, llvmorg-13.0.0, llvmorg-13.0.0-rc4, llvmorg-13.0.0-rc3, llvmorg-13.0.0-rc2, llvmorg-13.0.0-rc1, llvmorg-14-init, llvmorg-12.0.1, llvmorg-12.0.1-rc4, llvmorg-12.0.1-rc3, llvmorg-12.0.1-rc2, llvmorg-12.0.1-rc1, llvmorg-12.0.0, llvmorg-12.0.0-rc5, llvmorg-12.0.0-rc4, llvmorg-12.0.0-rc3, llvmorg-12.0.0-rc2, llvmorg-11.1.0, llvmorg-11.1.0-rc3, llvmorg-12.0.0-rc1, llvmorg-13-init, llvmorg-11.1.0-rc2, llvmorg-11.1.0-rc1, llvmorg-11.0.1, llvmorg-11.0.1-rc2, llvmorg-11.0.1-rc1, llvmorg-11.0.0, llvmorg-11.0.0-rc6, llvmorg-11.0.0-rc5, llvmorg-11.0.0-rc4, llvmorg-11.0.0-rc3, llvmorg-11.0.0-rc2, llvmorg-11.0.0-rc1, llvmorg-12-init, llvmorg-10.0.1, llvmorg-10.0.1-rc4, llvmorg-10.0.1-rc3, llvmorg-10.0.1-rc2, llvmorg-10.0.1-rc1, llvmorg-10.0.0, llvmorg-10.0.0-rc6, llvmorg-10.0.0-rc5, llvmorg-10.0.0-rc4, llvmorg-10.0.0-rc3, llvmorg-10.0.0-rc2, llvmorg-10.0.0-rc1, llvmorg-11-init, llvmorg-9.0.1, llvmorg-9.0.1-rc3, llvmorg-9.0.1-rc2, llvmorg-9.0.1-rc1, llvmorg-9.0.0, llvmorg-9.0.0-rc6, llvmorg-9.0.0-rc5, llvmorg-9.0.0-rc4, llvmorg-9.0.0-rc3, llvmorg-9.0.0-rc2, llvmorg-9.0.0-rc1, llvmorg-10-init, llvmorg-8.0.1, llvmorg-8.0.1-rc4, llvmorg-8.0.1-rc3 |
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| #
9cac4e6d |
| 19-Jun-2019 |
Matt Arsenault <[email protected]> |
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
This allows targets to make more decisions about reserved registers after isel. For example, now it should be certain there are call
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
This allows targets to make more decisions about reserved registers after isel. For example, now it should be certain there are calls or stack objects in the frame or not, which could have been introduced by legalization.
Patch by Matthias Braun
llvm-svn: 363757
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1933cbe8 |
| 18-Jun-2019 |
Evandro Menezes <[email protected]> |
[test] Change comment wording (NFC)
llvm-svn: 363751
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Revision tags: llvmorg-8.0.1-rc2, llvmorg-8.0.1-rc1, llvmorg-8.0.0, llvmorg-8.0.0-rc5, llvmorg-8.0.0-rc4, llvmorg-8.0.0-rc3, llvmorg-7.1.0, llvmorg-7.1.0-rc1, llvmorg-8.0.0-rc2, llvmorg-8.0.0-rc1 |
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| #
a6241a5d |
| 20-Jan-2019 |
Dylan McKay <[email protected]> |
[AVR] Remove unneeded XFAILs from the Generic CodeGen tests
These have been in place for quite a while now.
Several bugs have since been fixed, and these tests now pass.
llvm-svn: 351679
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Revision tags: llvmorg-7.0.1, llvmorg-7.0.1-rc3, llvmorg-7.0.1-rc2, llvmorg-7.0.1-rc1, llvmorg-7.0.0, llvmorg-7.0.0-rc3, llvmorg-7.0.0-rc2, llvmorg-7.0.0-rc1, llvmorg-6.0.1, llvmorg-6.0.1-rc3, llvmorg-6.0.1-rc2, llvmorg-6.0.1-rc1, llvmorg-5.0.2, llvmorg-5.0.2-rc2, llvmorg-5.0.2-rc1, llvmorg-6.0.0, llvmorg-6.0.0-rc3 |
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| #
39ec2e95 |
| 09-Feb-2018 |
Francis Visoiu Mistrih <[email protected]> |
[CodeGen] Unify the syntax of MBB successors in MIR and -debug output
Instead of:
Successors according to CFG: %bb.6(0x12492492 / 0x80000000 = 14.29%)
print:
successors: %bb.6(0x12492492); %bb.6(
[CodeGen] Unify the syntax of MBB successors in MIR and -debug output
Instead of:
Successors according to CFG: %bb.6(0x12492492 / 0x80000000 = 14.29%)
print:
successors: %bb.6(0x12492492); %bb.6(14.29%) llvm-svn: 324685
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| #
da89d181 |
| 08-Feb-2018 |
Francis Visoiu Mistrih <[email protected]> |
[CodeGen] Print MachineBasicBlock labels using MIR syntax in -debug output
Instead of:
%bb.1: derived from LLVM BB %for.body
print:
bb.1.for.body:
Also use MIR syntax for MBB attributes like "al
[CodeGen] Print MachineBasicBlock labels using MIR syntax in -debug output
Instead of:
%bb.1: derived from LLVM BB %for.body
print:
bb.1.for.body:
Also use MIR syntax for MBB attributes like "align", "landing-pad", etc.
llvm-svn: 324563
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Revision tags: llvmorg-6.0.0-rc2, llvmorg-6.0.0-rc1, llvmorg-5.0.1, llvmorg-5.0.1-rc3 |
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| #
25528d6d |
| 04-Dec-2017 |
Francis Visoiu Mistrih <[email protected]> |
[CodeGen] Unify MBB reference format in both MIR and debug output
As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'.
The MIR printer prints the IR n
[CodeGen] Unify MBB reference format in both MIR and debug output
As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'.
The MIR printer prints the IR name of a MBB only for block definitions.
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix
Differential Revision: https://reviews.llvm.org/D40422
llvm-svn: 319665
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Revision tags: llvmorg-5.0.1-rc2 |
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| #
3573d8da |
| 14-Nov-2017 |
Rong Xu <[email protected]> |
[CodeGen] Peel off the dominant case in switch statement in lowering
This patch peels off the top case in switch statement into a branch if the probability exceeds a threshold. This will help the br
[CodeGen] Peel off the dominant case in switch statement in lowering
This patch peels off the top case in switch statement into a branch if the probability exceeds a threshold. This will help the branch prediction and avoids the extra compares when lowering into chain of branches.
Differential Revision: http://reviews.llvm.org/D39262
llvm-svn: 318202
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Revision tags: llvmorg-5.0.1-rc1 |
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| #
7c79470c |
| 05-Oct-2017 |
Balaram Makam <[email protected]> |
[ARM/AARCH64] Make test MachineBranchProb.ll more robust and re-enable for ARM/AArch64
Summary: Make test robust enough to not fail due to CFG changes and re-enable for ARM/AArch64.
Reviewers: rovk
[ARM/AARCH64] Make test MachineBranchProb.ll more robust and re-enable for ARM/AArch64
Summary: Make test robust enough to not fail due to CFG changes and re-enable for ARM/AArch64.
Reviewers: rovka, fhahn
Reviewed By: fhahn
Subscribers: fhahn, aemerson, rengolin, mcrosier, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D38590
llvm-svn: 315002
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| #
45ff83ce |
| 04-Oct-2017 |
Balaram Makam <[email protected]> |
"[ARM] Mark flaky test MachineBranchProb.ll unsupported again for ARM/AArch64"
r314857 changed the CFG that resulted in the flaky test MachineBranchProb.ll to fail the bots again. Marking it as unsu
"[ARM] Mark flaky test MachineBranchProb.ll unsupported again for ARM/AArch64"
r314857 changed the CFG that resulted in the flaky test MachineBranchProb.ll to fail the bots again. Marking it as unsupported for ARM/AArch64 again until we find the cause.
llvm-svn: 314912
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Revision tags: llvmorg-5.0.0, llvmorg-5.0.0-rc5, llvmorg-5.0.0-rc4, llvmorg-5.0.0-rc3, llvmorg-5.0.0-rc2, llvmorg-5.0.0-rc1, llvmorg-4.0.1, llvmorg-4.0.1-rc3, llvmorg-4.0.1-rc2, llvmorg-4.0.1-rc1 |
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| #
edfeb773 |
| 05-Apr-2017 |
Renato Golin <[email protected]> |
[ARM] Try to re-enable MachineBranchProb.ll for ARM/AArch64
Commit r298799 changed code that made the XFAIL on MachineBranchProb.ll irrelevant, but some configurations still failed. I can't reproduc
[ARM] Try to re-enable MachineBranchProb.ll for ARM/AArch64
Commit r298799 changed code that made the XFAIL on MachineBranchProb.ll irrelevant, but some configurations still failed. I can't reproduce it locally, so I'm hoping that enabling this will tell me if some configurations will really fail or if they were just too slow.
llvm-svn: 299558
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| #
be2f7d9d |
| 27-Mar-2017 |
Renato Golin <[email protected]> |
[ARM] Mark falky test unsupported until we find the cause
llvm-svn: 298887
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Revision tags: llvmorg-4.0.0, llvmorg-4.0.0-rc4, llvmorg-4.0.0-rc3, llvmorg-4.0.0-rc2 |
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| #
db370bd6 |
| 08-Feb-2017 |
Dylan McKay <[email protected]> |
[AVR] XFAIL a set of failing CodeGen tests
There are about 3 underlying bugs causing the tests to fail.
On top of that, some tests just we're 'generic' enough. i.e. 32-bit registers.
llvm-svn: 294
[AVR] XFAIL a set of failing CodeGen tests
There are about 3 underlying bugs causing the tests to fail.
On top of that, some tests just we're 'generic' enough. i.e. 32-bit registers.
llvm-svn: 294434
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Revision tags: llvmorg-4.0.0-rc1, llvmorg-3.9.1, llvmorg-3.9.1-rc3, llvmorg-3.9.1-rc2, llvmorg-3.9.1-rc1, llvmorg-3.9.0, llvmorg-3.9.0-rc3, llvmorg-3.9.0-rc2, llvmorg-3.9.0-rc1 |
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| #
6400dec5 |
| 28-Jul-2016 |
Krzysztof Parzyszek <[email protected]> |
Fix build breaks after r277028
llvm-svn: 277031
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Revision tags: llvmorg-3.8.1, llvmorg-3.8.1-rc1 |
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| #
5e241b11 |
| 29-Mar-2016 |
Kyle Butt <[email protected]> |
[Codegen] Decrease minimum jump table density.
Minimum density for both optsize and non optsize are now options -sparse-jump-table-density (default 10) for non optsize functions -dense-jump-table-de
[Codegen] Decrease minimum jump table density.
Minimum density for both optsize and non optsize are now options -sparse-jump-table-density (default 10) for non optsize functions -dense-jump-table-density (default 40) for optsize functions, which matches the current default. This improves several benchmarks at google at the cost of a small codesize increase. For code compiled with -Os, the old behavior continues
llvm-svn: 264689
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Revision tags: llvmorg-3.8.0, llvmorg-3.8.0-rc3, llvmorg-3.8.0-rc2, llvmorg-3.8.0-rc1 |
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| #
893b781e |
| 14-Jan-2016 |
Krzysztof Parzyszek <[email protected]> |
Unxfail passing testcase on Hexagon
llvm-svn: 257770
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| #
d97c100d |
| 01-Dec-2015 |
Cong Hou <[email protected]> |
Replace all weight-based interfaces in MBB with probability-based interfaces, and update all uses of old interfaces.
(This is the second attempt to submit this patch. The first caused two assertion
Replace all weight-based interfaces in MBB with probability-based interfaces, and update all uses of old interfaces.
(This is the second attempt to submit this patch. The first caused two assertion failures and was reverted. See https://llvm.org/bugs/show_bug.cgi?id=25687)
The patch in http://reviews.llvm.org/D13745 is broken into four parts:
1. New interfaces without functional changes (http://reviews.llvm.org/D13908). 2. Use new interfaces in SelectionDAG, while in other passes treat probabilities as weights (http://reviews.llvm.org/D14361). 3. Use new interfaces in all other passes. 4. Remove old interfaces.
This patch is 3+4 above. In this patch, MBB won't provide weight-based interfaces any more, which are totally replaced by probability-based ones. The interface addSuccessor() is redesigned so that the default probability is unknown. We allow unknown probabilities but don't allow using it together with known probabilities in successor list. That is to say, we either have a list of successors with all known probabilities, or all unknown probabilities. In the latter case, we assume each successor has 1/N probability where N is the number of successors. An assertion checks if the user is attempting to add a successor with the disallowed mixed use as stated above. This can help us catch many misuses.
All uses of weight-based interfaces are now updated to use probability-based ones.
Differential revision: http://reviews.llvm.org/D14973
llvm-svn: 254377
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| #
1dbaf675 |
| 01-Dec-2015 |
Hans Wennborg <[email protected]> |
Revert r254348: "Replace all weight-based interfaces in MBB with probability-based interfaces, and update all uses of old interfaces."
and the follow-up r254356: "Fix a bug in MachineBlockPlacement
Revert r254348: "Replace all weight-based interfaces in MBB with probability-based interfaces, and update all uses of old interfaces."
and the follow-up r254356: "Fix a bug in MachineBlockPlacement that may cause assertion failure during BranchProbability construction."
Asserts were firing in Chromium builds. See PR25687.
llvm-svn: 254366
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Revision tags: llvmorg-3.7.1 |
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| #
fa1917c6 |
| 01-Dec-2015 |
Cong Hou <[email protected]> |
Replace all weight-based interfaces in MBB with probability-based interfaces, and update all uses of old interfaces.
The patch in http://reviews.llvm.org/D13745 is broken into four parts:
1. New in
Replace all weight-based interfaces in MBB with probability-based interfaces, and update all uses of old interfaces.
The patch in http://reviews.llvm.org/D13745 is broken into four parts:
1. New interfaces without functional changes (http://reviews.llvm.org/D13908). 2. Use new interfaces in SelectionDAG, while in other passes treat probabilities as weights (http://reviews.llvm.org/D14361). 3. Use new interfaces in all other passes. 4. Remove old interfaces.
This patch is 3+4 above. In this patch, MBB won't provide weight-based interfaces any more, which are totally replaced by probability-based ones. The interface addSuccessor() is redesigned so that the default probability is unknown. We allow unknown probabilities but don't allow using it together with known probabilities in successor list. That is to say, we either have a list of successors with all known probabilities, or all unknown probabilities. In the latter case, we assume each successor has 1/N probability where N is the number of successors. An assertion checks if the user is attempting to add a successor with the disallowed mixed use as stated above. This can help us catch many misuses.
All uses of weight-based interfaces are now updated to use probability-based ones.
Differential revision: http://reviews.llvm.org/D14973
llvm-svn: 254348
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| #
1938f2eb |
| 24-Nov-2015 |
Cong Hou <[email protected]> |
Let SelectionDAG start to use probability-based interface to add successors.
The patch in http://reviews.llvm.org/D13745 is broken into four parts:
1. New interfaces without functional changes. 2.
Let SelectionDAG start to use probability-based interface to add successors.
The patch in http://reviews.llvm.org/D13745 is broken into four parts:
1. New interfaces without functional changes. 2. Use new interfaces in SelectionDAG, while in other passes treat probabilities as weights. 3. Use new interfaces in all other passes. 4. Remove old interfaces.
This the second patch above. In this patch SelectionDAG starts to use probability-based interfaces in MBB to add successors but other MC passes are still using weight-based interfaces. Therefore, we need to maintain correct weight list in MBB even when probability-based interfaces are used. This is done by updating weight list in probability-based interfaces by treating the numerator of probabilities as weights. This change affects many test cases that check successor weight values. I will update those test cases once this patch looks good to you.
Differential revision: http://reviews.llvm.org/D14361
llvm-svn: 253965
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Revision tags: llvmorg-3.7.1-rc2, llvmorg-3.7.1-rc1 |
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| #
df8b0d6f |
| 29-Oct-2015 |
Weiming Zhao <[email protected]> |
Revert "[ARM] Remove XFAIL on test/CodeGen/Generic/MachineBranchProb.ll"
Summary: This reverts commit 79c37e1a4ff1e634da8f95322f080601b4c815fc. This test passes locally but fails on the com
Revert "[ARM] Remove XFAIL on test/CodeGen/Generic/MachineBranchProb.ll"
Summary: This reverts commit 79c37e1a4ff1e634da8f95322f080601b4c815fc. This test passes locally but fails on the community buildbot. So we will let it XFAIL for now.
Patched by Mandeep Singh Grang ([email protected])
Reviewers: kparzysz, weimingz
Subscribers: aemerson, rengolin, llvm-commits
Differential Revision: http://reviews.llvm.org/D14189
llvm-svn: 251664
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| #
b00cc621 |
| 29-Oct-2015 |
Weiming Zhao <[email protected]> |
[ARM] Remove XFAIL on test/CodeGen/Generic/MachineBranchProb.ll
Summary: Refer PR23377. This test was XFAIL'ed for Hexagon as well as ARM. But it has now started passing for ARM.
Reviewers: hans, r
[ARM] Remove XFAIL on test/CodeGen/Generic/MachineBranchProb.ll
Summary: Refer PR23377. This test was XFAIL'ed for Hexagon as well as ARM. But it has now started passing for ARM.
Reviewers: hans, rengolin, aemerson, kparzysz
Subscribers: aemerson, llvm-commits, rengolin
Differential Revision: http://reviews.llvm.org/D14155
llvm-svn: 251652
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| #
68d155be |
| 17-Oct-2015 |
Colin LeMahieu <[email protected]> |
[Hexagon] Reverting test file change.
llvm-svn: 250601
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| #
7c958713 |
| 17-Oct-2015 |
Colin LeMahieu <[email protected]> |
[Hexagon] Adding skeleton of HVX extension instructions.
llvm-svn: 250600
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| #
511298b9 |
| 01-Sep-2015 |
Cong Hou <[email protected]> |
Distribute the weight on the edge from switch to default statement to edges generated in lowering switch.
Currently, when edge weights are assigned to edges that are created when lowering switch sta
Distribute the weight on the edge from switch to default statement to edges generated in lowering switch.
Currently, when edge weights are assigned to edges that are created when lowering switch statement, the weight on the edge to default statement (let's call it "default weight" here) is not considered. We need to distribute this weight properly. However, without value profiling, we have no idea how to distribute it. In this patch, I applied the heuristic that this weight is evenly distributed to successors.
For example, given a switch statement with cases 1,2,3,5,10,11,20, and every edge from switch to each successor has weight 10. If there is a binary search tree built to test if n < 10, then its two out-edges will have weight 4x10+10/2 = 45 and 3x10 + 10/2 = 35 respectively (currently they are 40 and 30 without considering the default weight). Each distribution (which is 5 here) will be stored in each SwitchWorkListItem for further distribution.
There are some exceptions:
For a jump table header which doesn't have any edge to default statement, we don't distribute the default weight to it. For a bit test header which covers a contiguous range and hence has no edges to default statement, we don't distribute the default weight to it. When the branch checks a single value or a contiguous range with no edge to default statement, we don't distribute the default weight to it. In other cases, the default weight is evenly distributed to successors.
Differential Revision: http://reviews.llvm.org/D12418
llvm-svn: 246522
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Revision tags: llvmorg-3.7.0, llvmorg-3.7.0-rc4, llvmorg-3.7.0-rc3, llvmorg-3.7.0-rc2, llvmorg-3.7.0-rc1, llvmorg-3.6.2, llvmorg-3.6.2-rc1, llvmorg-3.6.1, llvmorg-3.6.1-rc1 |
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| #
bb0d7cbe |
| 01-May-2015 |
Colin LeMahieu <[email protected]> |
[Hexagon] r236351 fix does not work on builder configurations yet.
llvm-svn: 236358
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