1; RUN: llc < %s -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 | FileCheck %s
2
3; Hexagon runs passes that renumber the basic blocks, causing this test
4; to fail.
5; XFAIL: hexagon
6
7; Bug: PR31899
8; XFAIL: avr
9
10declare void @foo()
11
12; Make sure we have the correct weight attached to each successor.
13define i32 @test2(i32 %x) nounwind uwtable readnone ssp {
14; CHECK-LABEL: Machine code for function test2:
15entry:
16  %conv = sext i32 %x to i64
17  switch i64 %conv, label %return [
18    i64 0, label %sw.bb
19    i64 1, label %sw.bb
20    i64 4, label %sw.bb
21    i64 5, label %sw.bb1
22    i64 15, label %sw.bb
23  ], !prof !0
24; CHECK: %bb.0: derived from LLVM BB %entry
25; CHECK: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}92.17%) %bb.4({{[0-9a-fx/= ]+}}7.83%)
26; CHECK: %bb.4: derived from LLVM BB %entry
27; CHECK: Successors according to CFG: %bb.2({{[0-9a-fx/= ]+}}75.29%) %bb.5({{[0-9a-fx/= ]+}}24.71%)
28; CHECK: %bb.5: derived from LLVM BB %entry
29; CHECK: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}47.62%) %bb.6({{[0-9a-fx/= ]+}}52.38%)
30; CHECK: %bb.6: derived from LLVM BB %entry
31; CHECK: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}36.36%) %bb.3({{[0-9a-fx/= ]+}}63.64%)
32
33sw.bb:
34; this call will prevent simplifyCFG from optimizing the block away in ARM/AArch64.
35  tail call void @foo()
36  br label %return
37
38sw.bb1:
39  br label %return
40
41return:
42  %retval.0 = phi i32 [ 5, %sw.bb1 ], [ 1, %sw.bb ], [ 0, %entry ]
43  ret i32 %retval.0
44}
45
46!0 = !{!"branch_weights", i32 7, i32 6, i32 4, i32 4, i32 64, i21 1000}
47
48
49declare void @g(i32)
50define void @left_leaning_weight_balanced_tree(i32 %x) {
51entry:
52  switch i32 %x, label %return [
53    i32 0,  label %bb0
54    i32 100, label %bb1
55    i32 200, label %bb2
56    i32 300, label %bb3
57    i32 400, label %bb4
58    i32 500, label %bb5
59  ], !prof !1
60bb0: tail call void @g(i32 0) br label %return
61bb1: tail call void @g(i32 1) br label %return
62bb2: tail call void @g(i32 2) br label %return
63bb3: tail call void @g(i32 3) br label %return
64bb4: tail call void @g(i32 4) br label %return
65bb5: tail call void @g(i32 5) br label %return
66return: ret void
67
68; Check that we set branch weights on the pivot cmp instruction correctly.
69; Cases {0,10,20,30} go on the left with weight 13; cases {40,50} go on the
70; right with weight 20.
71;
72; CHECK-LABEL: Machine code for function left_leaning_weight_balanced_tree:
73; CHECK: %bb.0: derived from LLVM BB %entry
74; CHECK-NOT: Successors
75; CHECK: Successors according to CFG: %bb.8({{[0-9a-fx/= ]+}}39.71%) %bb.9({{[0-9a-fx/= ]+}}60.29%)
76}
77
78!1 = !{!"branch_weights",
79  ; Default:
80  i32 1,
81  ; Case 0, 100, 200:
82  i32 10, i32 1, i32 1,
83  ; Case 300, 400, 500:
84  i32 1, i32 10, i32 10}
85