1; RUN: llc < %s -print-machineinstrs=expand-isel-pseudos -o /dev/null 2>&1 | FileCheck %s
2
3; ARM & AArch64 run an extra SimplifyCFG which disrupts this test.
4; XFAIL: arm,aarch64
5
6; Hexagon runs passes that renumber the basic blocks, causing this test
7; to fail.
8; XFAIL: hexagon
9
10; Bug: PR31899
11; XFAIL: avr
12
13; Make sure we have the correct weight attached to each successor.
14define i32 @test2(i32 %x) nounwind uwtable readnone ssp {
15; CHECK-LABEL: Machine code for function test2:
16entry:
17  %conv = sext i32 %x to i64
18  switch i64 %conv, label %return [
19    i64 0, label %sw.bb
20    i64 1, label %sw.bb
21    i64 4, label %sw.bb
22    i64 5, label %sw.bb1
23  ], !prof !0
24; CHECK: BB#0: derived from LLVM BB %entry
25; CHECK: Successors according to CFG: BB#2({{[0-9a-fx/= ]+}}75.29%) BB#4({{[0-9a-fx/= ]+}}24.71%)
26; CHECK: BB#4: derived from LLVM BB %entry
27; CHECK: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}47.62%) BB#5({{[0-9a-fx/= ]+}}52.38%)
28; CHECK: BB#5: derived from LLVM BB %entry
29; CHECK: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}36.36%) BB#3({{[0-9a-fx/= ]+}}63.64%)
30
31sw.bb:
32  br label %return
33
34sw.bb1:
35  br label %return
36
37return:
38  %retval.0 = phi i32 [ 5, %sw.bb1 ], [ 1, %sw.bb ], [ 0, %entry ]
39  ret i32 %retval.0
40}
41
42!0 = !{!"branch_weights", i32 7, i32 6, i32 4, i32 4, i32 64}
43
44
45declare void @g(i32)
46define void @left_leaning_weight_balanced_tree(i32 %x) {
47entry:
48  switch i32 %x, label %return [
49    i32 0,  label %bb0
50    i32 100, label %bb1
51    i32 200, label %bb2
52    i32 300, label %bb3
53    i32 400, label %bb4
54    i32 500, label %bb5
55  ], !prof !1
56bb0: tail call void @g(i32 0) br label %return
57bb1: tail call void @g(i32 1) br label %return
58bb2: tail call void @g(i32 2) br label %return
59bb3: tail call void @g(i32 3) br label %return
60bb4: tail call void @g(i32 4) br label %return
61bb5: tail call void @g(i32 5) br label %return
62return: ret void
63
64; Check that we set branch weights on the pivot cmp instruction correctly.
65; Cases {0,10,20,30} go on the left with weight 13; cases {40,50} go on the
66; right with weight 20.
67;
68; CHECK-LABEL: Machine code for function left_leaning_weight_balanced_tree:
69; CHECK: BB#0: derived from LLVM BB %entry
70; CHECK-NOT: Successors
71; CHECK: Successors according to CFG: BB#8({{[0-9a-fx/= ]+}}39.71%) BB#9({{[0-9a-fx/= ]+}}60.29%)
72}
73
74!1 = !{!"branch_weights",
75  ; Default:
76  i32 1,
77  ; Case 0, 100, 200:
78  i32 10, i32 1, i32 1,
79  ; Case 300, 400, 500:
80  i32 1, i32 10, i32 10}
81