1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -pre-RA-sched=source | FileCheck %s 3; Test that we correctly align elements when using va_arg 4 5define i64 @test1(i32 %i, ...) nounwind optsize { 6; CHECK-LABEL: test1: 7; CHECK: @ %bb.0: @ %entry 8; CHECK-NEXT: .pad #16 9; CHECK-NEXT: sub sp, sp, #16 10; CHECK-NEXT: add r0, sp, #4 11; CHECK-NEXT: stmib sp, {r1, r2, r3} 12; CHECK-NEXT: add r0, r0, #7 13; CHECK-NEXT: bic r1, r0, #7 14; CHECK-NEXT: orr r0, r1, #4 15; CHECK-NEXT: str r0, [sp] 16; CHECK-NEXT: ldr r0, [r1] 17; CHECK-NEXT: add r2, r1, #8 18; CHECK-NEXT: str r2, [sp] 19; CHECK-NEXT: ldr r1, [r1, #4] 20; CHECK-NEXT: add sp, sp, #16 21; CHECK-NEXT: bx lr 22entry: 23 %g = alloca i8*, align 4 24 %g1 = bitcast i8** %g to i8* 25 call void @llvm.va_start(i8* %g1) 26 %0 = va_arg i8** %g, i64 27 call void @llvm.va_end(i8* %g1) 28 ret i64 %0 29} 30 31define double @test2(i32 %a, i32* %b, ...) nounwind optsize { 32; CHECK-LABEL: test2: 33; CHECK: @ %bb.0: @ %entry 34; CHECK-NEXT: .pad #12 35; CHECK-NEXT: sub sp, sp, #12 36; CHECK-NEXT: add r0, sp, #4 37; CHECK-NEXT: stmib sp, {r2, r3} 38; CHECK-NEXT: add r0, r0, #11 39; CHECK-NEXT: bic r0, r0, #3 40; CHECK-NEXT: str r2, [r1] 41; CHECK-NEXT: add r1, r0, #8 42; CHECK-NEXT: str r1, [sp] 43; CHECK-NEXT: vldr d16, [r0] 44; CHECK-NEXT: vmov r0, r1, d16 45; CHECK-NEXT: add sp, sp, #12 46; CHECK-NEXT: bx lr 47entry: 48 %ap = alloca i8*, align 4 ; <i8**> [#uses=3] 49 %ap1 = bitcast i8** %ap to i8* ; <i8*> [#uses=2] 50 call void @llvm.va_start(i8* %ap1) 51 %0 = va_arg i8** %ap, i32 ; <i32> [#uses=0] 52 store i32 %0, i32* %b 53 %1 = va_arg i8** %ap, double ; <double> [#uses=1] 54 call void @llvm.va_end(i8* %ap1) 55 ret double %1 56} 57 58 59declare void @llvm.va_start(i8*) nounwind 60 61declare void @llvm.va_end(i8*) nounwind 62