1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s 3 4; Optimize expanded SRL/SHL used as an input of 5; SETCC comparing it with zero by removing rotation. 6; 7; See https://bugs.llvm.org/show_bug.cgi?id=50197 8define i64 @opt_setcc_lt_power_of_2(i64 %a) nounwind { 9; CHECK-LABEL: opt_setcc_lt_power_of_2: 10; CHECK: @ %bb.0: 11; CHECK-NEXT: .LBB0_1: @ %loop 12; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 13; CHECK-NEXT: adds r0, r0, #1 14; CHECK-NEXT: adc r1, r1, #0 15; CHECK-NEXT: lsr r2, r0, #16 16; CHECK-NEXT: orr r2, r2, r1, lsl #16 17; CHECK-NEXT: orr r2, r2, r1, lsr #16 18; CHECK-NEXT: cmp r2, #0 19; CHECK-NEXT: bne .LBB0_1 20; CHECK-NEXT: @ %bb.2: @ %exit 21; CHECK-NEXT: bx lr 22 br label %loop 23 24loop: 25 %phi.a = phi i64 [ %a, %0 ], [ %inc, %loop ] 26 %inc = add i64 %phi.a, 1 27 %cmp = icmp ult i64 %inc, 65536 28 br i1 %cmp, label %exit, label %loop 29 30exit: 31 ret i64 %inc 32} 33 34define i1 @opt_setcc_srl_eq_zero(i64 %a) nounwind { 35; CHECK-LABEL: opt_setcc_srl_eq_zero: 36; CHECK: @ %bb.0: 37; CHECK-NEXT: lsr r0, r0, #17 38; CHECK-NEXT: orr r0, r0, r1, lsl #15 39; CHECK-NEXT: orr r0, r0, r1, lsr #17 40; CHECK-NEXT: clz r0, r0 41; CHECK-NEXT: lsr r0, r0, #5 42; CHECK-NEXT: bx lr 43 %srl = lshr i64 %a, 17 44 %cmp = icmp eq i64 %srl, 0 45 ret i1 %cmp 46} 47 48define i1 @opt_setcc_srl_ne_zero(i64 %a) nounwind { 49; CHECK-LABEL: opt_setcc_srl_ne_zero: 50; CHECK: @ %bb.0: 51; CHECK-NEXT: lsr r0, r0, #17 52; CHECK-NEXT: orr r0, r0, r1, lsl #15 53; CHECK-NEXT: orr r0, r0, r1, lsr #17 54; CHECK-NEXT: cmp r0, #0 55; CHECK-NEXT: movwne r0, #1 56; CHECK-NEXT: bx lr 57 %srl = lshr i64 %a, 17 58 %cmp = icmp ne i64 %srl, 0 59 ret i1 %cmp 60} 61 62define i1 @opt_setcc_shl_eq_zero(i64 %a) nounwind { 63; CHECK-LABEL: opt_setcc_shl_eq_zero: 64; CHECK: @ %bb.0: 65; CHECK-NEXT: lsl r1, r1, #17 66; CHECK-NEXT: orr r1, r1, r0, lsr #15 67; CHECK-NEXT: orr r0, r1, r0, lsl #17 68; CHECK-NEXT: clz r0, r0 69; CHECK-NEXT: lsr r0, r0, #5 70; CHECK-NEXT: bx lr 71 %shl = shl i64 %a, 17 72 %cmp = icmp eq i64 %shl, 0 73 ret i1 %cmp 74} 75 76define i1 @opt_setcc_shl_ne_zero(i64 %a) nounwind { 77; CHECK-LABEL: opt_setcc_shl_ne_zero: 78; CHECK: @ %bb.0: 79; CHECK-NEXT: lsl r1, r1, #17 80; CHECK-NEXT: orr r1, r1, r0, lsr #15 81; CHECK-NEXT: orr r0, r1, r0, lsl #17 82; CHECK-NEXT: cmp r0, #0 83; CHECK-NEXT: movwne r0, #1 84; CHECK-NEXT: bx lr 85 %shl = shl i64 %a, 17 86 %cmp = icmp ne i64 %shl, 0 87 ret i1 %cmp 88} 89 90; Negative test: optimization should not be applied if shift has multiple users. 91define i1 @opt_setcc_shl_eq_zero_multiple_shl_users(i64 %a) nounwind { 92; CHECK-LABEL: opt_setcc_shl_eq_zero_multiple_shl_users: 93; CHECK: @ %bb.0: 94; CHECK-NEXT: push {r4, r5, r11, lr} 95; CHECK-NEXT: mov r4, r0 96; CHECK-NEXT: lsl r0, r1, #17 97; CHECK-NEXT: orr r5, r0, r4, lsr #15 98; CHECK-NEXT: lsl r0, r4, #17 99; CHECK-NEXT: mov r1, r5 100; CHECK-NEXT: bl use 101; CHECK-NEXT: orr r0, r5, r4, lsl #17 102; CHECK-NEXT: clz r0, r0 103; CHECK-NEXT: lsr r0, r0, #5 104; CHECK-NEXT: pop {r4, r5, r11, pc} 105 %shl = shl i64 %a, 17 106 %cmp = icmp eq i64 %shl, 0 107 call void @use(i64 %shl) 108 ret i1 %cmp 109} 110 111; Check that optimization is applied to DAG having appropriate shape 112; even if there were no actual shift's expansion. 113define i1 @opt_setcc_expanded_shl_correct_shifts(i32 %a, i32 %b) nounwind { 114; CHECK-LABEL: opt_setcc_expanded_shl_correct_shifts: 115; CHECK: @ %bb.0: 116; CHECK-NEXT: lsl r0, r0, #17 117; CHECK-NEXT: orr r0, r0, r1, lsr #15 118; CHECK-NEXT: orr r0, r0, r1, lsl #17 119; CHECK-NEXT: clz r0, r0 120; CHECK-NEXT: lsr r0, r0, #5 121; CHECK-NEXT: bx lr 122 %shl.a = shl i32 %a, 17 123 %srl.b = lshr i32 %b, 15 124 %or.0 = or i32 %shl.a, %srl.b 125 %shl.b = shl i32 %b, 17 126 %or.1 = or i32 %or.0, %shl.b 127 %cmp = icmp eq i32 %or.1, 0 128 ret i1 %cmp 129} 130 131; Negative test: optimization should not be applied as 132; constants used in shifts do not match. 133define i1 @opt_setcc_expanded_shl_wrong_shifts(i32 %a, i32 %b) nounwind { 134; CHECK-LABEL: opt_setcc_expanded_shl_wrong_shifts: 135; CHECK: @ %bb.0: 136; CHECK-NEXT: lsl r0, r0, #17 137; CHECK-NEXT: orr r0, r0, r1, lsr #15 138; CHECK-NEXT: orr r0, r0, r1, lsl #18 139; CHECK-NEXT: clz r0, r0 140; CHECK-NEXT: lsr r0, r0, #5 141; CHECK-NEXT: bx lr 142 %shl.a = shl i32 %a, 17 143 %srl.b = lshr i32 %b, 15 144 %or.0 = or i32 %shl.a, %srl.b 145 %shl.b = shl i32 %b, 18 146 %or.1 = or i32 %or.0, %shl.b 147 %cmp = icmp eq i32 %or.1, 0 148 ret i1 %cmp 149} 150 151define i1 @opt_setcc_shl_ne_zero_i128(i128 %a) nounwind { 152; CHECK-LABEL: opt_setcc_shl_ne_zero_i128: 153; CHECK: @ %bb.0: 154; CHECK-NEXT: lsl r3, r3, #17 155; CHECK-NEXT: orr r12, r3, r2, lsr #15 156; CHECK-NEXT: lsl r3, r1, #17 157; CHECK-NEXT: lsl r2, r2, #17 158; CHECK-NEXT: orr r3, r3, r0, lsr #15 159; CHECK-NEXT: orr r1, r2, r1, lsr #15 160; CHECK-NEXT: orr r3, r3, r12 161; CHECK-NEXT: orr r0, r1, r0, lsl #17 162; CHECK-NEXT: orrs r0, r0, r3 163; CHECK-NEXT: movwne r0, #1 164; CHECK-NEXT: bx lr 165 %shl = shl i128 %a, 17 166 %cmp = icmp ne i128 %shl, 0 167 ret i1 %cmp 168} 169 170declare void @use(i64 %a) 171