1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=armv7 %s -o - | FileCheck %s 3 4; Optimize expanded SRL/SHL used as an input of 5; SETCC comparing it with zero by removing rotation. 6; 7; See https://bugs.llvm.org/show_bug.cgi?id=50197 8define i64 @opt_setcc_lt_power_of_2(i64 %a) nounwind { 9; CHECK-LABEL: opt_setcc_lt_power_of_2: 10; CHECK: @ %bb.0: 11; CHECK-NEXT: .LBB0_1: @ %loop 12; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 13; CHECK-NEXT: adds r0, r0, #1 14; CHECK-NEXT: adc r1, r1, #0 15; CHECK-NEXT: orr r2, r1, r0, lsr #16 16; CHECK-NEXT: cmp r2, #0 17; CHECK-NEXT: bne .LBB0_1 18; CHECK-NEXT: @ %bb.2: @ %exit 19; CHECK-NEXT: bx lr 20 br label %loop 21 22loop: 23 %phi.a = phi i64 [ %a, %0 ], [ %inc, %loop ] 24 %inc = add i64 %phi.a, 1 25 %cmp = icmp ult i64 %inc, 65536 26 br i1 %cmp, label %exit, label %loop 27 28exit: 29 ret i64 %inc 30} 31 32define i1 @opt_setcc_srl_eq_zero(i64 %a) nounwind { 33; CHECK-LABEL: opt_setcc_srl_eq_zero: 34; CHECK: @ %bb.0: 35; CHECK-NEXT: orr r0, r1, r0, lsr #17 36; CHECK-NEXT: clz r0, r0 37; CHECK-NEXT: lsr r0, r0, #5 38; CHECK-NEXT: bx lr 39 %srl = lshr i64 %a, 17 40 %cmp = icmp eq i64 %srl, 0 41 ret i1 %cmp 42} 43 44define i1 @opt_setcc_srl_ne_zero(i64 %a) nounwind { 45; CHECK-LABEL: opt_setcc_srl_ne_zero: 46; CHECK: @ %bb.0: 47; CHECK-NEXT: orr r0, r1, r0, lsr #17 48; CHECK-NEXT: cmp r0, #0 49; CHECK-NEXT: movwne r0, #1 50; CHECK-NEXT: bx lr 51 %srl = lshr i64 %a, 17 52 %cmp = icmp ne i64 %srl, 0 53 ret i1 %cmp 54} 55 56define i1 @opt_setcc_shl_eq_zero(i64 %a) nounwind { 57; CHECK-LABEL: opt_setcc_shl_eq_zero: 58; CHECK: @ %bb.0: 59; CHECK-NEXT: orr r0, r0, r1, lsl #17 60; CHECK-NEXT: clz r0, r0 61; CHECK-NEXT: lsr r0, r0, #5 62; CHECK-NEXT: bx lr 63 %shl = shl i64 %a, 17 64 %cmp = icmp eq i64 %shl, 0 65 ret i1 %cmp 66} 67 68define i1 @opt_setcc_shl_ne_zero(i64 %a) nounwind { 69; CHECK-LABEL: opt_setcc_shl_ne_zero: 70; CHECK: @ %bb.0: 71; CHECK-NEXT: orr r0, r0, r1, lsl #17 72; CHECK-NEXT: cmp r0, #0 73; CHECK-NEXT: movwne r0, #1 74; CHECK-NEXT: bx lr 75 %shl = shl i64 %a, 17 76 %cmp = icmp ne i64 %shl, 0 77 ret i1 %cmp 78} 79 80; Negative test: optimization should not be applied if shift has multiple users. 81define i1 @opt_setcc_shl_eq_zero_multiple_shl_users(i64 %a) nounwind { 82; CHECK-LABEL: opt_setcc_shl_eq_zero_multiple_shl_users: 83; CHECK: @ %bb.0: 84; CHECK-NEXT: push {r4, r5, r11, lr} 85; CHECK-NEXT: mov r4, r0 86; CHECK-NEXT: lsl r0, r1, #17 87; CHECK-NEXT: orr r5, r0, r4, lsr #15 88; CHECK-NEXT: lsl r0, r4, #17 89; CHECK-NEXT: mov r1, r5 90; CHECK-NEXT: bl use 91; CHECK-NEXT: orr r0, r5, r4, lsl #17 92; CHECK-NEXT: clz r0, r0 93; CHECK-NEXT: lsr r0, r0, #5 94; CHECK-NEXT: pop {r4, r5, r11, pc} 95 %shl = shl i64 %a, 17 96 %cmp = icmp eq i64 %shl, 0 97 call void @use(i64 %shl) 98 ret i1 %cmp 99} 100 101; Check that optimization is applied to DAG having appropriate shape 102; even if there were no actual shift's expansion. 103define i1 @opt_setcc_expanded_shl_correct_shifts(i32 %a, i32 %b) nounwind { 104; CHECK-LABEL: opt_setcc_expanded_shl_correct_shifts: 105; CHECK: @ %bb.0: 106; CHECK-NEXT: orr r0, r1, r0, lsl #17 107; CHECK-NEXT: clz r0, r0 108; CHECK-NEXT: lsr r0, r0, #5 109; CHECK-NEXT: bx lr 110 %shl.a = shl i32 %a, 17 111 %srl.b = lshr i32 %b, 15 112 %or.0 = or i32 %shl.a, %srl.b 113 %shl.b = shl i32 %b, 17 114 %or.1 = or i32 %or.0, %shl.b 115 %cmp = icmp eq i32 %or.1, 0 116 ret i1 %cmp 117} 118 119; Negative test: optimization should not be applied as 120; constants used in shifts do not match. 121define i1 @opt_setcc_expanded_shl_wrong_shifts(i32 %a, i32 %b) nounwind { 122; CHECK-LABEL: opt_setcc_expanded_shl_wrong_shifts: 123; CHECK: @ %bb.0: 124; CHECK-NEXT: lsl r0, r0, #17 125; CHECK-NEXT: orr r0, r0, r1, lsr #15 126; CHECK-NEXT: orr r0, r0, r1, lsl #18 127; CHECK-NEXT: clz r0, r0 128; CHECK-NEXT: lsr r0, r0, #5 129; CHECK-NEXT: bx lr 130 %shl.a = shl i32 %a, 17 131 %srl.b = lshr i32 %b, 15 132 %or.0 = or i32 %shl.a, %srl.b 133 %shl.b = shl i32 %b, 18 134 %or.1 = or i32 %or.0, %shl.b 135 %cmp = icmp eq i32 %or.1, 0 136 ret i1 %cmp 137} 138 139define i1 @opt_setcc_shl_ne_zero_i128(i128 %a) nounwind { 140; CHECK-LABEL: opt_setcc_shl_ne_zero_i128: 141; CHECK: @ %bb.0: 142; CHECK-NEXT: lsl r3, r3, #17 143; CHECK-NEXT: orr r12, r3, r2, lsr #15 144; CHECK-NEXT: lsl r3, r1, #17 145; CHECK-NEXT: orr r3, r3, r0, lsr #15 146; CHECK-NEXT: orr r0, r2, r0 147; CHECK-NEXT: orr r3, r3, r12 148; CHECK-NEXT: lsl r0, r0, #17 149; CHECK-NEXT: orr r0, r0, r1, lsr #15 150; CHECK-NEXT: orrs r0, r0, r3 151; CHECK-NEXT: movwne r0, #1 152; CHECK-NEXT: bx lr 153 %shl = shl i128 %a, 17 154 %cmp = icmp ne i128 %shl, 0 155 ret i1 %cmp 156} 157 158declare void @use(i64 %a) 159