1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc %s -o - -mtriple=thumbv8m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
3; RUN:   FileCheck %s --check-prefix=CHECK-8M --check-prefix=CHECK-8M-LE
4; RUN: llc %s -o - -mtriple=thumbebv8m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
5; RUN:   FileCheck %s --check-prefix=CHECK-8M --check-prefix=CHECK-8M-BE
6; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
7; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-NO-MVE --check-prefix=CHECK-81M-LE
8; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
9; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-NO-MVE --check-prefix=CHECK-81M-BE
10; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mattr=+mve.fp -float-abi=hard | \
11; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-MVE --check-prefix=CHECK-81M-LE
12; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+mve.fp -float-abi=hard | \
13; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-MVE --check-prefix=CHECK-81M-BE
14
15define float @f1(float (float)* nocapture %fptr) #0 {
16; CHECK-8M-LABEL: f1:
17; CHECK-8M:       @ %bb.0: @ %entry
18; CHECK-8M-NEXT:    push {r7, lr}
19; CHECK-8M-NEXT:    vmov.f32 s0, #1.000000e+01
20; CHECK-8M-NEXT:    blx r0
21; CHECK-8M-NEXT:    pop.w {r7, lr}
22; CHECK-8M-NEXT:    mrs r12, control
23; CHECK-8M-NEXT:    tst.w r12, #8
24; CHECK-8M-NEXT:    beq .LBB0_2
25; CHECK-8M-NEXT:  @ %bb.1: @ %entry
26; CHECK-8M-NEXT:    vmrs r12, fpscr
27; CHECK-8M-NEXT:    vmov s1, lr
28; CHECK-8M-NEXT:    vmov d1, lr, lr
29; CHECK-8M-NEXT:    vmov d2, lr, lr
30; CHECK-8M-NEXT:    vmov d3, lr, lr
31; CHECK-8M-NEXT:    vmov d4, lr, lr
32; CHECK-8M-NEXT:    vmov d5, lr, lr
33; CHECK-8M-NEXT:    vmov d6, lr, lr
34; CHECK-8M-NEXT:    vmov d7, lr, lr
35; CHECK-8M-NEXT:    bic r12, r12, #159
36; CHECK-8M-NEXT:    bic r12, r12, #4026531840
37; CHECK-8M-NEXT:    vmsr fpscr, r12
38; CHECK-8M-NEXT:  .LBB0_2: @ %entry
39; CHECK-8M-NEXT:    mov r0, lr
40; CHECK-8M-NEXT:    mov r1, lr
41; CHECK-8M-NEXT:    mov r2, lr
42; CHECK-8M-NEXT:    mov r3, lr
43; CHECK-8M-NEXT:    mov r12, lr
44; CHECK-8M-NEXT:    msr apsr_nzcvqg, lr
45; CHECK-8M-NEXT:    bxns lr
46;
47; CHECK-81M-LABEL: f1:
48; CHECK-81M:       @ %bb.0: @ %entry
49; CHECK-81M-NEXT:    vstr fpcxtns, [sp, #-4]!
50; CHECK-81M-NEXT:    push {r7, lr}
51; CHECK-81M-NEXT:    sub sp, #4
52; CHECK-81M-NEXT:    vmov.f32 s0, #1.000000e+01
53; CHECK-81M-NEXT:    blx r0
54; CHECK-81M-NEXT:    add sp, #4
55; CHECK-81M-NEXT:    pop.w {r7, lr}
56; CHECK-81M-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
57; CHECK-81M-NEXT:    vldr fpcxtns, [sp], #4
58; CHECK-81M-NEXT:    clrm {r0, r1, r2, r3, r12, apsr}
59; CHECK-81M-NEXT:    bxns lr
60entry:
61  %call = call float %fptr(float 10.0) #1
62  ret float %call
63}
64
65attributes #0 = { "cmse_nonsecure_entry" nounwind }
66attributes #1 = { nounwind }
67
68define double @d1(double (double)* nocapture %fptr) #0 {
69; CHECK-8M-LE-LABEL: d1:
70; CHECK-8M-LE:       @ %bb.0: @ %entry
71; CHECK-8M-LE-NEXT:    push {r7, lr}
72; CHECK-8M-LE-NEXT:    vldr d0, .LCPI1_0
73; CHECK-8M-LE-NEXT:    blx r0
74; CHECK-8M-LE-NEXT:    pop.w {r7, lr}
75; CHECK-8M-LE-NEXT:    mrs r12, control
76; CHECK-8M-LE-NEXT:    tst.w r12, #8
77; CHECK-8M-LE-NEXT:    beq .LBB1_2
78; CHECK-8M-LE-NEXT:  @ %bb.1: @ %entry
79; CHECK-8M-LE-NEXT:    vmrs r12, fpscr
80; CHECK-8M-LE-NEXT:    vmov d1, lr, lr
81; CHECK-8M-LE-NEXT:    vmov d2, lr, lr
82; CHECK-8M-LE-NEXT:    vmov d3, lr, lr
83; CHECK-8M-LE-NEXT:    vmov d4, lr, lr
84; CHECK-8M-LE-NEXT:    vmov d5, lr, lr
85; CHECK-8M-LE-NEXT:    vmov d6, lr, lr
86; CHECK-8M-LE-NEXT:    vmov d7, lr, lr
87; CHECK-8M-LE-NEXT:    bic r12, r12, #159
88; CHECK-8M-LE-NEXT:    bic r12, r12, #4026531840
89; CHECK-8M-LE-NEXT:    vmsr fpscr, r12
90; CHECK-8M-LE-NEXT:  .LBB1_2: @ %entry
91; CHECK-8M-LE-NEXT:    mov r0, lr
92; CHECK-8M-LE-NEXT:    mov r1, lr
93; CHECK-8M-LE-NEXT:    mov r2, lr
94; CHECK-8M-LE-NEXT:    mov r3, lr
95; CHECK-8M-LE-NEXT:    mov r12, lr
96; CHECK-8M-LE-NEXT:    msr apsr_nzcvqg, lr
97; CHECK-8M-LE-NEXT:    bxns lr
98; CHECK-8M-LE-NEXT:    .p2align 3
99; CHECK-8M-LE-NEXT:  @ %bb.3:
100; CHECK-8M-LE-NEXT:  .LCPI1_0:
101; CHECK-8M-LE-NEXT:    .long 0 @ double 10
102; CHECK-8M-LE-NEXT:    .long 1076101120
103;
104; CHECK-8M-BE-LABEL: d1:
105; CHECK-8M-BE:       @ %bb.0: @ %entry
106; CHECK-8M-BE-NEXT:    push {r7, lr}
107; CHECK-8M-BE-NEXT:    vldr d0, .LCPI1_0
108; CHECK-8M-BE-NEXT:    blx r0
109; CHECK-8M-BE-NEXT:    pop.w {r7, lr}
110; CHECK-8M-BE-NEXT:    mrs r12, control
111; CHECK-8M-BE-NEXT:    tst.w r12, #8
112; CHECK-8M-BE-NEXT:    beq .LBB1_2
113; CHECK-8M-BE-NEXT:  @ %bb.1: @ %entry
114; CHECK-8M-BE-NEXT:    vmrs r12, fpscr
115; CHECK-8M-BE-NEXT:    vmov d1, lr, lr
116; CHECK-8M-BE-NEXT:    vmov d2, lr, lr
117; CHECK-8M-BE-NEXT:    vmov d3, lr, lr
118; CHECK-8M-BE-NEXT:    vmov d4, lr, lr
119; CHECK-8M-BE-NEXT:    vmov d5, lr, lr
120; CHECK-8M-BE-NEXT:    vmov d6, lr, lr
121; CHECK-8M-BE-NEXT:    vmov d7, lr, lr
122; CHECK-8M-BE-NEXT:    bic r12, r12, #159
123; CHECK-8M-BE-NEXT:    bic r12, r12, #4026531840
124; CHECK-8M-BE-NEXT:    vmsr fpscr, r12
125; CHECK-8M-BE-NEXT:  .LBB1_2: @ %entry
126; CHECK-8M-BE-NEXT:    mov r0, lr
127; CHECK-8M-BE-NEXT:    mov r1, lr
128; CHECK-8M-BE-NEXT:    mov r2, lr
129; CHECK-8M-BE-NEXT:    mov r3, lr
130; CHECK-8M-BE-NEXT:    mov r12, lr
131; CHECK-8M-BE-NEXT:    msr apsr_nzcvqg, lr
132; CHECK-8M-BE-NEXT:    bxns lr
133; CHECK-8M-BE-NEXT:    .p2align 3
134; CHECK-8M-BE-NEXT:  @ %bb.3:
135; CHECK-8M-BE-NEXT:  .LCPI1_0:
136; CHECK-8M-BE-NEXT:    .long 1076101120 @ double 10
137; CHECK-8M-BE-NEXT:    .long 0
138;
139; CHECK-81M-LE-LABEL: d1:
140; CHECK-81M-LE:       @ %bb.0: @ %entry
141; CHECK-81M-LE-NEXT:    vstr fpcxtns, [sp, #-4]!
142; CHECK-81M-LE-NEXT:    push {r7, lr}
143; CHECK-81M-LE-NEXT:    sub sp, #4
144; CHECK-81M-LE-NEXT:    vldr d0, .LCPI1_0
145; CHECK-81M-LE-NEXT:    blx r0
146; CHECK-81M-LE-NEXT:    add sp, #4
147; CHECK-81M-LE-NEXT:    pop.w {r7, lr}
148; CHECK-81M-LE-NEXT:    vscclrm {s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
149; CHECK-81M-LE-NEXT:    vldr fpcxtns, [sp], #4
150; CHECK-81M-LE-NEXT:    clrm {r0, r1, r2, r3, r12, apsr}
151; CHECK-81M-LE-NEXT:    bxns lr
152; CHECK-81M-LE-NEXT:    .p2align 3
153; CHECK-81M-LE-NEXT:  @ %bb.1:
154; CHECK-81M-LE-NEXT:  .LCPI1_0:
155; CHECK-81M-LE-NEXT:    .long 0 @ double 10
156; CHECK-81M-LE-NEXT:    .long 1076101120
157;
158; CHECK-81M-BE-LABEL: d1:
159; CHECK-81M-BE:       @ %bb.0: @ %entry
160; CHECK-81M-BE-NEXT:    vstr fpcxtns, [sp, #-4]!
161; CHECK-81M-BE-NEXT:    push {r7, lr}
162; CHECK-81M-BE-NEXT:    sub sp, #4
163; CHECK-81M-BE-NEXT:    vldr d0, .LCPI1_0
164; CHECK-81M-BE-NEXT:    blx r0
165; CHECK-81M-BE-NEXT:    add sp, #4
166; CHECK-81M-BE-NEXT:    pop.w {r7, lr}
167; CHECK-81M-BE-NEXT:    vscclrm {s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
168; CHECK-81M-BE-NEXT:    vldr fpcxtns, [sp], #4
169; CHECK-81M-BE-NEXT:    clrm {r0, r1, r2, r3, r12, apsr}
170; CHECK-81M-BE-NEXT:    bxns lr
171; CHECK-81M-BE-NEXT:    .p2align 3
172; CHECK-81M-BE-NEXT:  @ %bb.1:
173; CHECK-81M-BE-NEXT:  .LCPI1_0:
174; CHECK-81M-BE-NEXT:    .long 1076101120 @ double 10
175; CHECK-81M-BE-NEXT:    .long 0
176entry:
177  %call = call double %fptr(double 10.0) #1
178  ret double %call
179}
180
181define float @f2(float (float)* nocapture %fptr) #2 {
182; CHECK-8M-LABEL: f2:
183; CHECK-8M:       @ %bb.0: @ %entry
184; CHECK-8M-NEXT:    push {r7, lr}
185; CHECK-8M-NEXT:    vmov.f32 s0, #1.000000e+01
186; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
187; CHECK-8M-NEXT:    bic r0, r0, #1
188; CHECK-8M-NEXT:    sub sp, #136
189; CHECK-8M-NEXT:    vmov r12, s0
190; CHECK-8M-NEXT:    vlstm sp
191; CHECK-8M-NEXT:    vmov s0, r12
192; CHECK-8M-NEXT:    ldr r1, [sp, #64]
193; CHECK-8M-NEXT:    bic r1, r1, #159
194; CHECK-8M-NEXT:    bic r1, r1, #4026531840
195; CHECK-8M-NEXT:    vmsr fpscr, r1
196; CHECK-8M-NEXT:    mov r1, r0
197; CHECK-8M-NEXT:    mov r2, r0
198; CHECK-8M-NEXT:    mov r3, r0
199; CHECK-8M-NEXT:    mov r4, r0
200; CHECK-8M-NEXT:    mov r5, r0
201; CHECK-8M-NEXT:    mov r6, r0
202; CHECK-8M-NEXT:    mov r7, r0
203; CHECK-8M-NEXT:    mov r8, r0
204; CHECK-8M-NEXT:    mov r9, r0
205; CHECK-8M-NEXT:    mov r10, r0
206; CHECK-8M-NEXT:    mov r11, r0
207; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
208; CHECK-8M-NEXT:    blxns r0
209; CHECK-8M-NEXT:    vmov r12, s0
210; CHECK-8M-NEXT:    vlldm sp
211; CHECK-8M-NEXT:    vmov s0, r12
212; CHECK-8M-NEXT:    add sp, #136
213; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
214; CHECK-8M-NEXT:    pop {r7, pc}
215;
216; CHECK-81M-LABEL: f2:
217; CHECK-81M:       @ %bb.0: @ %entry
218; CHECK-81M-NEXT:    push {r7, lr}
219; CHECK-81M-NEXT:    vmov.f32 s0, #1.000000e+01
220; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
221; CHECK-81M-NEXT:    bic r0, r0, #1
222; CHECK-81M-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
223; CHECK-81M-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
224; CHECK-81M-NEXT:    vstr fpcxts, [sp, #-8]!
225; CHECK-81M-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
226; CHECK-81M-NEXT:    blxns r0
227; CHECK-81M-NEXT:    vldr fpcxts, [sp], #8
228; CHECK-81M-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
229; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
230; CHECK-81M-NEXT:    pop {r7, pc}
231entry:
232  %call = call float %fptr(float 10.0) #3
233  ret float %call
234}
235
236attributes #2 = { nounwind }
237attributes #3 = { "cmse_nonsecure_call" nounwind }
238
239define double @d2(double (double)* nocapture %fptr) #2 {
240; CHECK-8M-LE-LABEL: d2:
241; CHECK-8M-LE:       @ %bb.0: @ %entry
242; CHECK-8M-LE-NEXT:    push {r7, lr}
243; CHECK-8M-LE-NEXT:    vldr d0, .LCPI3_0
244; CHECK-8M-LE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
245; CHECK-8M-LE-NEXT:    bic r0, r0, #1
246; CHECK-8M-LE-NEXT:    sub sp, #136
247; CHECK-8M-LE-NEXT:    vmov r11, r12, d0
248; CHECK-8M-LE-NEXT:    vlstm sp
249; CHECK-8M-LE-NEXT:    vmov d0, r11, r12
250; CHECK-8M-LE-NEXT:    ldr r1, [sp, #64]
251; CHECK-8M-LE-NEXT:    bic r1, r1, #159
252; CHECK-8M-LE-NEXT:    bic r1, r1, #4026531840
253; CHECK-8M-LE-NEXT:    vmsr fpscr, r1
254; CHECK-8M-LE-NEXT:    mov r1, r0
255; CHECK-8M-LE-NEXT:    mov r2, r0
256; CHECK-8M-LE-NEXT:    mov r3, r0
257; CHECK-8M-LE-NEXT:    mov r4, r0
258; CHECK-8M-LE-NEXT:    mov r5, r0
259; CHECK-8M-LE-NEXT:    mov r6, r0
260; CHECK-8M-LE-NEXT:    mov r7, r0
261; CHECK-8M-LE-NEXT:    mov r8, r0
262; CHECK-8M-LE-NEXT:    mov r9, r0
263; CHECK-8M-LE-NEXT:    mov r10, r0
264; CHECK-8M-LE-NEXT:    msr apsr_nzcvqg, r0
265; CHECK-8M-LE-NEXT:    blxns r0
266; CHECK-8M-LE-NEXT:    vmov r11, r12, d0
267; CHECK-8M-LE-NEXT:    vlldm sp
268; CHECK-8M-LE-NEXT:    vmov d0, r11, r12
269; CHECK-8M-LE-NEXT:    add sp, #136
270; CHECK-8M-LE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
271; CHECK-8M-LE-NEXT:    pop {r7, pc}
272; CHECK-8M-LE-NEXT:    .p2align 3
273; CHECK-8M-LE-NEXT:  @ %bb.1:
274; CHECK-8M-LE-NEXT:  .LCPI3_0:
275; CHECK-8M-LE-NEXT:    .long 0 @ double 10
276; CHECK-8M-LE-NEXT:    .long 1076101120
277;
278; CHECK-8M-BE-LABEL: d2:
279; CHECK-8M-BE:       @ %bb.0: @ %entry
280; CHECK-8M-BE-NEXT:    push {r7, lr}
281; CHECK-8M-BE-NEXT:    vldr d0, .LCPI3_0
282; CHECK-8M-BE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
283; CHECK-8M-BE-NEXT:    bic r0, r0, #1
284; CHECK-8M-BE-NEXT:    sub sp, #136
285; CHECK-8M-BE-NEXT:    vmov r11, r12, d0
286; CHECK-8M-BE-NEXT:    vlstm sp
287; CHECK-8M-BE-NEXT:    vmov d0, r11, r12
288; CHECK-8M-BE-NEXT:    ldr r1, [sp, #64]
289; CHECK-8M-BE-NEXT:    bic r1, r1, #159
290; CHECK-8M-BE-NEXT:    bic r1, r1, #4026531840
291; CHECK-8M-BE-NEXT:    vmsr fpscr, r1
292; CHECK-8M-BE-NEXT:    mov r1, r0
293; CHECK-8M-BE-NEXT:    mov r2, r0
294; CHECK-8M-BE-NEXT:    mov r3, r0
295; CHECK-8M-BE-NEXT:    mov r4, r0
296; CHECK-8M-BE-NEXT:    mov r5, r0
297; CHECK-8M-BE-NEXT:    mov r6, r0
298; CHECK-8M-BE-NEXT:    mov r7, r0
299; CHECK-8M-BE-NEXT:    mov r8, r0
300; CHECK-8M-BE-NEXT:    mov r9, r0
301; CHECK-8M-BE-NEXT:    mov r10, r0
302; CHECK-8M-BE-NEXT:    msr apsr_nzcvqg, r0
303; CHECK-8M-BE-NEXT:    blxns r0
304; CHECK-8M-BE-NEXT:    vmov r11, r12, d0
305; CHECK-8M-BE-NEXT:    vlldm sp
306; CHECK-8M-BE-NEXT:    vmov d0, r11, r12
307; CHECK-8M-BE-NEXT:    add sp, #136
308; CHECK-8M-BE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
309; CHECK-8M-BE-NEXT:    pop {r7, pc}
310; CHECK-8M-BE-NEXT:    .p2align 3
311; CHECK-8M-BE-NEXT:  @ %bb.1:
312; CHECK-8M-BE-NEXT:  .LCPI3_0:
313; CHECK-8M-BE-NEXT:    .long 1076101120 @ double 10
314; CHECK-8M-BE-NEXT:    .long 0
315;
316; CHECK-81M-LE-LABEL: d2:
317; CHECK-81M-LE:       @ %bb.0: @ %entry
318; CHECK-81M-LE-NEXT:    push {r7, lr}
319; CHECK-81M-LE-NEXT:    vldr d0, .LCPI3_0
320; CHECK-81M-LE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
321; CHECK-81M-LE-NEXT:    bic r0, r0, #1
322; CHECK-81M-LE-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
323; CHECK-81M-LE-NEXT:    vscclrm {s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
324; CHECK-81M-LE-NEXT:    vstr fpcxts, [sp, #-8]!
325; CHECK-81M-LE-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
326; CHECK-81M-LE-NEXT:    blxns r0
327; CHECK-81M-LE-NEXT:    vldr fpcxts, [sp], #8
328; CHECK-81M-LE-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
329; CHECK-81M-LE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
330; CHECK-81M-LE-NEXT:    pop {r7, pc}
331; CHECK-81M-LE-NEXT:    .p2align 3
332; CHECK-81M-LE-NEXT:  @ %bb.1:
333; CHECK-81M-LE-NEXT:  .LCPI3_0:
334; CHECK-81M-LE-NEXT:    .long 0 @ double 10
335; CHECK-81M-LE-NEXT:    .long 1076101120
336;
337; CHECK-81M-BE-LABEL: d2:
338; CHECK-81M-BE:       @ %bb.0: @ %entry
339; CHECK-81M-BE-NEXT:    push {r7, lr}
340; CHECK-81M-BE-NEXT:    vldr d0, .LCPI3_0
341; CHECK-81M-BE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
342; CHECK-81M-BE-NEXT:    bic r0, r0, #1
343; CHECK-81M-BE-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
344; CHECK-81M-BE-NEXT:    vscclrm {s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
345; CHECK-81M-BE-NEXT:    vstr fpcxts, [sp, #-8]!
346; CHECK-81M-BE-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
347; CHECK-81M-BE-NEXT:    blxns r0
348; CHECK-81M-BE-NEXT:    vldr fpcxts, [sp], #8
349; CHECK-81M-BE-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
350; CHECK-81M-BE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
351; CHECK-81M-BE-NEXT:    pop {r7, pc}
352; CHECK-81M-BE-NEXT:    .p2align 3
353; CHECK-81M-BE-NEXT:  @ %bb.1:
354; CHECK-81M-BE-NEXT:  .LCPI3_0:
355; CHECK-81M-BE-NEXT:    .long 1076101120 @ double 10
356; CHECK-81M-BE-NEXT:    .long 0
357entry:
358  %call = call double %fptr(double 10.0) #3
359  ret double %call
360}
361
362define float @f3(float (float)* nocapture %fptr) #4 {
363; CHECK-8M-LABEL: f3:
364; CHECK-8M:       @ %bb.0: @ %entry
365; CHECK-8M-NEXT:    push {r7, lr}
366; CHECK-8M-NEXT:    vmov.f32 s0, #1.000000e+01
367; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
368; CHECK-8M-NEXT:    bic r0, r0, #1
369; CHECK-8M-NEXT:    sub sp, #136
370; CHECK-8M-NEXT:    vmov r12, s0
371; CHECK-8M-NEXT:    vlstm sp
372; CHECK-8M-NEXT:    vmov s0, r12
373; CHECK-8M-NEXT:    ldr r1, [sp, #64]
374; CHECK-8M-NEXT:    bic r1, r1, #159
375; CHECK-8M-NEXT:    bic r1, r1, #4026531840
376; CHECK-8M-NEXT:    vmsr fpscr, r1
377; CHECK-8M-NEXT:    mov r1, r0
378; CHECK-8M-NEXT:    mov r2, r0
379; CHECK-8M-NEXT:    mov r3, r0
380; CHECK-8M-NEXT:    mov r4, r0
381; CHECK-8M-NEXT:    mov r5, r0
382; CHECK-8M-NEXT:    mov r6, r0
383; CHECK-8M-NEXT:    mov r7, r0
384; CHECK-8M-NEXT:    mov r8, r0
385; CHECK-8M-NEXT:    mov r9, r0
386; CHECK-8M-NEXT:    mov r10, r0
387; CHECK-8M-NEXT:    mov r11, r0
388; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
389; CHECK-8M-NEXT:    blxns r0
390; CHECK-8M-NEXT:    vmov r12, s0
391; CHECK-8M-NEXT:    vlldm sp
392; CHECK-8M-NEXT:    vmov s0, r12
393; CHECK-8M-NEXT:    add sp, #136
394; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
395; CHECK-8M-NEXT:    pop {r7, pc}
396;
397; CHECK-81M-LABEL: f3:
398; CHECK-81M:       @ %bb.0: @ %entry
399; CHECK-81M-NEXT:    push {r7, lr}
400; CHECK-81M-NEXT:    vmov.f32 s0, #1.000000e+01
401; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
402; CHECK-81M-NEXT:    bic r0, r0, #1
403; CHECK-81M-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
404; CHECK-81M-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
405; CHECK-81M-NEXT:    vstr fpcxts, [sp, #-8]!
406; CHECK-81M-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
407; CHECK-81M-NEXT:    blxns r0
408; CHECK-81M-NEXT:    vldr fpcxts, [sp], #8
409; CHECK-81M-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
410; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
411; CHECK-81M-NEXT:    pop {r7, pc}
412entry:
413  %call = tail call float %fptr(float 10.0) #5
414  ret float %call
415}
416
417attributes #4 = { nounwind }
418attributes #5 = { "cmse_nonsecure_call" nounwind }
419
420define double @d3(double (double)* nocapture %fptr) #4 {
421; CHECK-8M-LE-LABEL: d3:
422; CHECK-8M-LE:       @ %bb.0: @ %entry
423; CHECK-8M-LE-NEXT:    push {r7, lr}
424; CHECK-8M-LE-NEXT:    vldr d0, .LCPI5_0
425; CHECK-8M-LE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
426; CHECK-8M-LE-NEXT:    bic r0, r0, #1
427; CHECK-8M-LE-NEXT:    sub sp, #136
428; CHECK-8M-LE-NEXT:    vmov r11, r12, d0
429; CHECK-8M-LE-NEXT:    vlstm sp
430; CHECK-8M-LE-NEXT:    vmov d0, r11, r12
431; CHECK-8M-LE-NEXT:    ldr r1, [sp, #64]
432; CHECK-8M-LE-NEXT:    bic r1, r1, #159
433; CHECK-8M-LE-NEXT:    bic r1, r1, #4026531840
434; CHECK-8M-LE-NEXT:    vmsr fpscr, r1
435; CHECK-8M-LE-NEXT:    mov r1, r0
436; CHECK-8M-LE-NEXT:    mov r2, r0
437; CHECK-8M-LE-NEXT:    mov r3, r0
438; CHECK-8M-LE-NEXT:    mov r4, r0
439; CHECK-8M-LE-NEXT:    mov r5, r0
440; CHECK-8M-LE-NEXT:    mov r6, r0
441; CHECK-8M-LE-NEXT:    mov r7, r0
442; CHECK-8M-LE-NEXT:    mov r8, r0
443; CHECK-8M-LE-NEXT:    mov r9, r0
444; CHECK-8M-LE-NEXT:    mov r10, r0
445; CHECK-8M-LE-NEXT:    msr apsr_nzcvqg, r0
446; CHECK-8M-LE-NEXT:    blxns r0
447; CHECK-8M-LE-NEXT:    vmov r11, r12, d0
448; CHECK-8M-LE-NEXT:    vlldm sp
449; CHECK-8M-LE-NEXT:    vmov d0, r11, r12
450; CHECK-8M-LE-NEXT:    add sp, #136
451; CHECK-8M-LE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
452; CHECK-8M-LE-NEXT:    pop {r7, pc}
453; CHECK-8M-LE-NEXT:    .p2align 3
454; CHECK-8M-LE-NEXT:  @ %bb.1:
455; CHECK-8M-LE-NEXT:  .LCPI5_0:
456; CHECK-8M-LE-NEXT:    .long 0 @ double 10
457; CHECK-8M-LE-NEXT:    .long 1076101120
458;
459; CHECK-8M-BE-LABEL: d3:
460; CHECK-8M-BE:       @ %bb.0: @ %entry
461; CHECK-8M-BE-NEXT:    push {r7, lr}
462; CHECK-8M-BE-NEXT:    vldr d0, .LCPI5_0
463; CHECK-8M-BE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
464; CHECK-8M-BE-NEXT:    bic r0, r0, #1
465; CHECK-8M-BE-NEXT:    sub sp, #136
466; CHECK-8M-BE-NEXT:    vmov r11, r12, d0
467; CHECK-8M-BE-NEXT:    vlstm sp
468; CHECK-8M-BE-NEXT:    vmov d0, r11, r12
469; CHECK-8M-BE-NEXT:    ldr r1, [sp, #64]
470; CHECK-8M-BE-NEXT:    bic r1, r1, #159
471; CHECK-8M-BE-NEXT:    bic r1, r1, #4026531840
472; CHECK-8M-BE-NEXT:    vmsr fpscr, r1
473; CHECK-8M-BE-NEXT:    mov r1, r0
474; CHECK-8M-BE-NEXT:    mov r2, r0
475; CHECK-8M-BE-NEXT:    mov r3, r0
476; CHECK-8M-BE-NEXT:    mov r4, r0
477; CHECK-8M-BE-NEXT:    mov r5, r0
478; CHECK-8M-BE-NEXT:    mov r6, r0
479; CHECK-8M-BE-NEXT:    mov r7, r0
480; CHECK-8M-BE-NEXT:    mov r8, r0
481; CHECK-8M-BE-NEXT:    mov r9, r0
482; CHECK-8M-BE-NEXT:    mov r10, r0
483; CHECK-8M-BE-NEXT:    msr apsr_nzcvqg, r0
484; CHECK-8M-BE-NEXT:    blxns r0
485; CHECK-8M-BE-NEXT:    vmov r11, r12, d0
486; CHECK-8M-BE-NEXT:    vlldm sp
487; CHECK-8M-BE-NEXT:    vmov d0, r11, r12
488; CHECK-8M-BE-NEXT:    add sp, #136
489; CHECK-8M-BE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
490; CHECK-8M-BE-NEXT:    pop {r7, pc}
491; CHECK-8M-BE-NEXT:    .p2align 3
492; CHECK-8M-BE-NEXT:  @ %bb.1:
493; CHECK-8M-BE-NEXT:  .LCPI5_0:
494; CHECK-8M-BE-NEXT:    .long 1076101120 @ double 10
495; CHECK-8M-BE-NEXT:    .long 0
496;
497; CHECK-81M-LE-LABEL: d3:
498; CHECK-81M-LE:       @ %bb.0: @ %entry
499; CHECK-81M-LE-NEXT:    push {r7, lr}
500; CHECK-81M-LE-NEXT:    vldr d0, .LCPI5_0
501; CHECK-81M-LE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
502; CHECK-81M-LE-NEXT:    bic r0, r0, #1
503; CHECK-81M-LE-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
504; CHECK-81M-LE-NEXT:    vscclrm {s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
505; CHECK-81M-LE-NEXT:    vstr fpcxts, [sp, #-8]!
506; CHECK-81M-LE-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
507; CHECK-81M-LE-NEXT:    blxns r0
508; CHECK-81M-LE-NEXT:    vldr fpcxts, [sp], #8
509; CHECK-81M-LE-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
510; CHECK-81M-LE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
511; CHECK-81M-LE-NEXT:    pop {r7, pc}
512; CHECK-81M-LE-NEXT:    .p2align 3
513; CHECK-81M-LE-NEXT:  @ %bb.1:
514; CHECK-81M-LE-NEXT:  .LCPI5_0:
515; CHECK-81M-LE-NEXT:    .long 0 @ double 10
516; CHECK-81M-LE-NEXT:    .long 1076101120
517;
518; CHECK-81M-BE-LABEL: d3:
519; CHECK-81M-BE:       @ %bb.0: @ %entry
520; CHECK-81M-BE-NEXT:    push {r7, lr}
521; CHECK-81M-BE-NEXT:    vldr d0, .LCPI5_0
522; CHECK-81M-BE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
523; CHECK-81M-BE-NEXT:    bic r0, r0, #1
524; CHECK-81M-BE-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
525; CHECK-81M-BE-NEXT:    vscclrm {s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
526; CHECK-81M-BE-NEXT:    vstr fpcxts, [sp, #-8]!
527; CHECK-81M-BE-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
528; CHECK-81M-BE-NEXT:    blxns r0
529; CHECK-81M-BE-NEXT:    vldr fpcxts, [sp], #8
530; CHECK-81M-BE-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
531; CHECK-81M-BE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
532; CHECK-81M-BE-NEXT:    pop {r7, pc}
533; CHECK-81M-BE-NEXT:    .p2align 3
534; CHECK-81M-BE-NEXT:  @ %bb.1:
535; CHECK-81M-BE-NEXT:  .LCPI5_0:
536; CHECK-81M-BE-NEXT:    .long 1076101120 @ double 10
537; CHECK-81M-BE-NEXT:    .long 0
538entry:
539  %call = tail call double %fptr(double 10.0) #5
540  ret double %call
541}
542
543define float @f4(float ()* nocapture %fptr) #6 {
544; CHECK-8M-LABEL: f4:
545; CHECK-8M:       @ %bb.0: @ %entry
546; CHECK-8M-NEXT:    push {r7, lr}
547; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
548; CHECK-8M-NEXT:    bic r0, r0, #1
549; CHECK-8M-NEXT:    sub sp, #136
550; CHECK-8M-NEXT:    vlstm sp
551; CHECK-8M-NEXT:    mov r1, r0
552; CHECK-8M-NEXT:    mov r2, r0
553; CHECK-8M-NEXT:    mov r3, r0
554; CHECK-8M-NEXT:    mov r4, r0
555; CHECK-8M-NEXT:    mov r5, r0
556; CHECK-8M-NEXT:    mov r6, r0
557; CHECK-8M-NEXT:    mov r7, r0
558; CHECK-8M-NEXT:    mov r8, r0
559; CHECK-8M-NEXT:    mov r9, r0
560; CHECK-8M-NEXT:    mov r10, r0
561; CHECK-8M-NEXT:    mov r11, r0
562; CHECK-8M-NEXT:    mov r12, r0
563; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
564; CHECK-8M-NEXT:    blxns r0
565; CHECK-8M-NEXT:    vmov r12, s0
566; CHECK-8M-NEXT:    vlldm sp
567; CHECK-8M-NEXT:    vmov s0, r12
568; CHECK-8M-NEXT:    add sp, #136
569; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
570; CHECK-8M-NEXT:    pop {r7, pc}
571;
572; CHECK-81M-LABEL: f4:
573; CHECK-81M:       @ %bb.0: @ %entry
574; CHECK-81M-NEXT:    push {r7, lr}
575; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
576; CHECK-81M-NEXT:    bic r0, r0, #1
577; CHECK-81M-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
578; CHECK-81M-NEXT:    vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
579; CHECK-81M-NEXT:    vstr fpcxts, [sp, #-8]!
580; CHECK-81M-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
581; CHECK-81M-NEXT:    blxns r0
582; CHECK-81M-NEXT:    vldr fpcxts, [sp], #8
583; CHECK-81M-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
584; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
585; CHECK-81M-NEXT:    pop {r7, pc}
586entry:
587  %call = call float %fptr() #7
588  ret float %call
589}
590
591attributes #6 = { nounwind }
592attributes #7 = { "cmse_nonsecure_call" nounwind }
593
594define double @d4(double ()* nocapture %fptr) #6 {
595; CHECK-8M-LABEL: d4:
596; CHECK-8M:       @ %bb.0: @ %entry
597; CHECK-8M-NEXT:    push {r7, lr}
598; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
599; CHECK-8M-NEXT:    bic r0, r0, #1
600; CHECK-8M-NEXT:    sub sp, #136
601; CHECK-8M-NEXT:    vlstm sp
602; CHECK-8M-NEXT:    mov r1, r0
603; CHECK-8M-NEXT:    mov r2, r0
604; CHECK-8M-NEXT:    mov r3, r0
605; CHECK-8M-NEXT:    mov r4, r0
606; CHECK-8M-NEXT:    mov r5, r0
607; CHECK-8M-NEXT:    mov r6, r0
608; CHECK-8M-NEXT:    mov r7, r0
609; CHECK-8M-NEXT:    mov r8, r0
610; CHECK-8M-NEXT:    mov r9, r0
611; CHECK-8M-NEXT:    mov r10, r0
612; CHECK-8M-NEXT:    mov r11, r0
613; CHECK-8M-NEXT:    mov r12, r0
614; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
615; CHECK-8M-NEXT:    blxns r0
616; CHECK-8M-NEXT:    vmov r11, r12, d0
617; CHECK-8M-NEXT:    vlldm sp
618; CHECK-8M-NEXT:    vmov d0, r11, r12
619; CHECK-8M-NEXT:    add sp, #136
620; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
621; CHECK-8M-NEXT:    pop {r7, pc}
622;
623; CHECK-81M-LABEL: d4:
624; CHECK-81M:       @ %bb.0: @ %entry
625; CHECK-81M-NEXT:    push {r7, lr}
626; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
627; CHECK-81M-NEXT:    bic r0, r0, #1
628; CHECK-81M-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
629; CHECK-81M-NEXT:    vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
630; CHECK-81M-NEXT:    vstr fpcxts, [sp, #-8]!
631; CHECK-81M-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
632; CHECK-81M-NEXT:    blxns r0
633; CHECK-81M-NEXT:    vldr fpcxts, [sp], #8
634; CHECK-81M-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
635; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
636; CHECK-81M-NEXT:    pop {r7, pc}
637entry:
638  %call = call double %fptr() #7
639  ret double %call
640}
641
642define void @fd(void (float, double)* %f, float %a, double %b) #8 {
643; CHECK-8M-LABEL: fd:
644; CHECK-8M:       @ %bb.0: @ %entry
645; CHECK-8M-NEXT:    push {r7, lr}
646; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
647; CHECK-8M-NEXT:    bic r0, r0, #1
648; CHECK-8M-NEXT:    sub sp, #136
649; CHECK-8M-NEXT:    vmov r12, s0
650; CHECK-8M-NEXT:    mov r2, r0
651; CHECK-8M-NEXT:    vmov r10, r11, d1
652; CHECK-8M-NEXT:    vlstm sp
653; CHECK-8M-NEXT:    vmov s0, r12
654; CHECK-8M-NEXT:    vmov d1, r10, r11
655; CHECK-8M-NEXT:    ldr r1, [sp, #64]
656; CHECK-8M-NEXT:    bic r1, r1, #159
657; CHECK-8M-NEXT:    bic r1, r1, #4026531840
658; CHECK-8M-NEXT:    vmsr fpscr, r1
659; CHECK-8M-NEXT:    mov r1, r0
660; CHECK-8M-NEXT:    mov r3, r0
661; CHECK-8M-NEXT:    mov r4, r0
662; CHECK-8M-NEXT:    mov r5, r0
663; CHECK-8M-NEXT:    mov r6, r0
664; CHECK-8M-NEXT:    mov r7, r0
665; CHECK-8M-NEXT:    mov r8, r0
666; CHECK-8M-NEXT:    mov r9, r0
667; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
668; CHECK-8M-NEXT:    blxns r0
669; CHECK-8M-NEXT:    vlldm sp
670; CHECK-8M-NEXT:    add sp, #136
671; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
672; CHECK-8M-NEXT:    pop {r7, pc}
673;
674; CHECK-81M-LABEL: fd:
675; CHECK-81M:       @ %bb.0: @ %entry
676; CHECK-81M-NEXT:    push {r7, lr}
677; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
678; CHECK-81M-NEXT:    bic r0, r0, #1
679; CHECK-81M-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
680; CHECK-81M-NEXT:    vscclrm {s1, vpr}
681; CHECK-81M-NEXT:    vscclrm {s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
682; CHECK-81M-NEXT:    vstr fpcxts, [sp, #-8]!
683; CHECK-81M-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
684; CHECK-81M-NEXT:    blxns r0
685; CHECK-81M-NEXT:    vldr fpcxts, [sp], #8
686; CHECK-81M-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
687; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
688; CHECK-81M-NEXT:    pop {r7, pc}
689entry:
690  call void %f(float %a, double %b) #9
691  ret void
692}
693
694attributes #8 = { nounwind }
695attributes #9 = { "cmse_nonsecure_call" nounwind }
696
697define void @fdff(void (float, double, float, float)* %f, float %a, double %b, float %c, float %d) #8 {
698; CHECK-8M-LABEL: fdff:
699; CHECK-8M:       @ %bb.0: @ %entry
700; CHECK-8M-NEXT:    push {r7, lr}
701; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
702; CHECK-8M-NEXT:    bic r0, r0, #1
703; CHECK-8M-NEXT:    sub sp, #136
704; CHECK-8M-NEXT:    vmov r12, s0
705; CHECK-8M-NEXT:    mov r2, r0
706; CHECK-8M-NEXT:    vmov r10, r11, d1
707; CHECK-8M-NEXT:    mov r3, r0
708; CHECK-8M-NEXT:    vmov r9, s1
709; CHECK-8M-NEXT:    mov r4, r0
710; CHECK-8M-NEXT:    vmov r8, s4
711; CHECK-8M-NEXT:    vlstm sp
712; CHECK-8M-NEXT:    vmov s0, r12
713; CHECK-8M-NEXT:    vmov d1, r10, r11
714; CHECK-8M-NEXT:    vmov s1, r9
715; CHECK-8M-NEXT:    vmov s4, r8
716; CHECK-8M-NEXT:    ldr r1, [sp, #64]
717; CHECK-8M-NEXT:    bic r1, r1, #159
718; CHECK-8M-NEXT:    bic r1, r1, #4026531840
719; CHECK-8M-NEXT:    vmsr fpscr, r1
720; CHECK-8M-NEXT:    mov r1, r0
721; CHECK-8M-NEXT:    mov r5, r0
722; CHECK-8M-NEXT:    mov r6, r0
723; CHECK-8M-NEXT:    mov r7, r0
724; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
725; CHECK-8M-NEXT:    blxns r0
726; CHECK-8M-NEXT:    vlldm sp
727; CHECK-8M-NEXT:    add sp, #136
728; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
729; CHECK-8M-NEXT:    pop {r7, pc}
730;
731; CHECK-81M-LABEL: fdff:
732; CHECK-81M:       @ %bb.0: @ %entry
733; CHECK-81M-NEXT:    push {r7, lr}
734; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
735; CHECK-81M-NEXT:    bic r0, r0, #1
736; CHECK-81M-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
737; CHECK-81M-NEXT:    vscclrm {s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
738; CHECK-81M-NEXT:    vstr fpcxts, [sp, #-8]!
739; CHECK-81M-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
740; CHECK-81M-NEXT:    blxns r0
741; CHECK-81M-NEXT:    vldr fpcxts, [sp], #8
742; CHECK-81M-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
743; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
744; CHECK-81M-NEXT:    pop {r7, pc}
745entry:
746  call void %f(float %a, double %b, float %c, float %d) #9
747  ret void
748}
749
750define void @fidififid(void (float, i32, double, i32, float, i32, float, i32, double)* %fu, float %a, i32 %b, double %c, i32 %d, float %e, i32 %f, float %g, i32 %h, double %i) #8 {
751; CHECK-8M-LABEL: fidififid:
752; CHECK-8M:       @ %bb.0: @ %entry
753; CHECK-8M-NEXT:    push {r7, lr}
754; CHECK-8M-NEXT:    mov lr, r3
755; CHECK-8M-NEXT:    mov r12, r0
756; CHECK-8M-NEXT:    mov r0, r1
757; CHECK-8M-NEXT:    mov r1, r2
758; CHECK-8M-NEXT:    ldr r3, [sp, #8]
759; CHECK-8M-NEXT:    mov r2, lr
760; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
761; CHECK-8M-NEXT:    bic r12, r12, #1
762; CHECK-8M-NEXT:    sub sp, #136
763; CHECK-8M-NEXT:    vmov r11, s0
764; CHECK-8M-NEXT:    vmov r9, r10, d1
765; CHECK-8M-NEXT:    vmov r8, s1
766; CHECK-8M-NEXT:    vmov r7, s4
767; CHECK-8M-NEXT:    vmov r5, r6, d3
768; CHECK-8M-NEXT:    vlstm sp
769; CHECK-8M-NEXT:    vmov s0, r11
770; CHECK-8M-NEXT:    vmov d1, r9, r10
771; CHECK-8M-NEXT:    vmov s1, r8
772; CHECK-8M-NEXT:    vmov s4, r7
773; CHECK-8M-NEXT:    vmov d3, r5, r6
774; CHECK-8M-NEXT:    ldr r4, [sp, #64]
775; CHECK-8M-NEXT:    bic r4, r4, #159
776; CHECK-8M-NEXT:    bic r4, r4, #4026531840
777; CHECK-8M-NEXT:    vmsr fpscr, r4
778; CHECK-8M-NEXT:    mov r4, r12
779; CHECK-8M-NEXT:    msr apsr_nzcvqg, r12
780; CHECK-8M-NEXT:    blxns r12
781; CHECK-8M-NEXT:    vlldm sp
782; CHECK-8M-NEXT:    add sp, #136
783; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
784; CHECK-8M-NEXT:    pop {r7, pc}
785;
786; CHECK-81M-LABEL: fidififid:
787; CHECK-81M:       @ %bb.0: @ %entry
788; CHECK-81M-NEXT:    push {r7, lr}
789; CHECK-81M-NEXT:    mov lr, r3
790; CHECK-81M-NEXT:    mov r12, r0
791; CHECK-81M-NEXT:    mov r0, r1
792; CHECK-81M-NEXT:    mov r1, r2
793; CHECK-81M-NEXT:    ldr r3, [sp, #8]
794; CHECK-81M-NEXT:    mov r2, lr
795; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
796; CHECK-81M-NEXT:    bic r12, r12, #1
797; CHECK-81M-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
798; CHECK-81M-NEXT:    vscclrm {s5, vpr}
799; CHECK-81M-NEXT:    vscclrm {s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
800; CHECK-81M-NEXT:    vstr fpcxts, [sp, #-8]!
801; CHECK-81M-NEXT:    clrm {r4, r5, r6, r7, r8, r9, r10, r11, apsr}
802; CHECK-81M-NEXT:    blxns r12
803; CHECK-81M-NEXT:    vldr fpcxts, [sp], #8
804; CHECK-81M-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
805; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
806; CHECK-81M-NEXT:    pop {r7, pc}
807entry:
808  call void %fu(float %a, i32 %b, double %c, i32 %d, float %e, i32 %f, float %g, i32 %h, double %i) #9
809  ret void
810}
811
812define half @h1(half (half)* nocapture %hptr) "cmse_nonsecure_entry" nounwind {
813; CHECK-8M-LABEL: h1:
814; CHECK-8M:       @ %bb.0:
815; CHECK-8M-NEXT:    push {r7, lr}
816; CHECK-8M-NEXT:    vldr s0, .LCPI11_0
817; CHECK-8M-NEXT:    blx r0
818; CHECK-8M-NEXT:    vmov r0, s0
819; CHECK-8M-NEXT:    uxth r0, r0
820; CHECK-8M-NEXT:    vmov s0, r0
821; CHECK-8M-NEXT:    pop.w {r7, lr}
822; CHECK-8M-NEXT:    mrs r12, control
823; CHECK-8M-NEXT:    tst.w r12, #8
824; CHECK-8M-NEXT:    beq .LBB11_2
825; CHECK-8M-NEXT:  @ %bb.1:
826; CHECK-8M-NEXT:    vmrs r12, fpscr
827; CHECK-8M-NEXT:    vmov s1, lr
828; CHECK-8M-NEXT:    vmov d1, lr, lr
829; CHECK-8M-NEXT:    vmov d2, lr, lr
830; CHECK-8M-NEXT:    vmov d3, lr, lr
831; CHECK-8M-NEXT:    vmov d4, lr, lr
832; CHECK-8M-NEXT:    vmov d5, lr, lr
833; CHECK-8M-NEXT:    vmov d6, lr, lr
834; CHECK-8M-NEXT:    vmov d7, lr, lr
835; CHECK-8M-NEXT:    bic r12, r12, #159
836; CHECK-8M-NEXT:    bic r12, r12, #4026531840
837; CHECK-8M-NEXT:    vmsr fpscr, r12
838; CHECK-8M-NEXT:  .LBB11_2:
839; CHECK-8M-NEXT:    mov r0, lr
840; CHECK-8M-NEXT:    mov r1, lr
841; CHECK-8M-NEXT:    mov r2, lr
842; CHECK-8M-NEXT:    mov r3, lr
843; CHECK-8M-NEXT:    mov r12, lr
844; CHECK-8M-NEXT:    msr apsr_nzcvqg, lr
845; CHECK-8M-NEXT:    bxns lr
846; CHECK-8M-NEXT:    .p2align 2
847; CHECK-8M-NEXT:  @ %bb.3:
848; CHECK-8M-NEXT:  .LCPI11_0:
849; CHECK-8M-NEXT:    .long 0x00004900 @ float 2.61874657E-41
850;
851; CHECK-NO-MVE-LABEL: h1:
852; CHECK-NO-MVE:       @ %bb.0:
853; CHECK-NO-MVE-NEXT:    vstr fpcxtns, [sp, #-4]!
854; CHECK-NO-MVE-NEXT:    push {r7, lr}
855; CHECK-NO-MVE-NEXT:    sub sp, #4
856; CHECK-NO-MVE-NEXT:    vldr s0, .LCPI11_0
857; CHECK-NO-MVE-NEXT:    blx r0
858; CHECK-NO-MVE-NEXT:    vmov r0, s0
859; CHECK-NO-MVE-NEXT:    uxth r0, r0
860; CHECK-NO-MVE-NEXT:    vmov s0, r0
861; CHECK-NO-MVE-NEXT:    add sp, #4
862; CHECK-NO-MVE-NEXT:    pop.w {r7, lr}
863; CHECK-NO-MVE-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
864; CHECK-NO-MVE-NEXT:    vldr fpcxtns, [sp], #4
865; CHECK-NO-MVE-NEXT:    clrm {r0, r1, r2, r3, r12, apsr}
866; CHECK-NO-MVE-NEXT:    bxns lr
867; CHECK-NO-MVE-NEXT:    .p2align 2
868; CHECK-NO-MVE-NEXT:  @ %bb.1:
869; CHECK-NO-MVE-NEXT:  .LCPI11_0:
870; CHECK-NO-MVE-NEXT:    .long 0x00004900 @ float 2.61874657E-41
871;
872; CHECK-MVE-LABEL: h1:
873; CHECK-MVE:       @ %bb.0:
874; CHECK-MVE-NEXT:    vstr fpcxtns, [sp, #-4]!
875; CHECK-MVE-NEXT:    push {r7, lr}
876; CHECK-MVE-NEXT:    sub sp, #4
877; CHECK-MVE-NEXT:    vmov.f16 s0, #1.000000e+01
878; CHECK-MVE-NEXT:    blx r0
879; CHECK-MVE-NEXT:    vmov.f16 r0, s0
880; CHECK-MVE-NEXT:    vmov s0, r0
881; CHECK-MVE-NEXT:    add sp, #4
882; CHECK-MVE-NEXT:    pop.w {r7, lr}
883; CHECK-MVE-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
884; CHECK-MVE-NEXT:    vldr fpcxtns, [sp], #4
885; CHECK-MVE-NEXT:    clrm {r0, r1, r2, r3, r12, apsr}
886; CHECK-MVE-NEXT:    bxns lr
887  %call = call half %hptr(half 10.0) nounwind
888  ret half %call
889}
890
891define half @h2(half (half)* nocapture %hptr) nounwind {
892; CHECK-8M-LABEL: h2:
893; CHECK-8M:       @ %bb.0: @ %entry
894; CHECK-8M-NEXT:    push {r7, lr}
895; CHECK-8M-NEXT:    vldr s0, .LCPI12_0
896; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
897; CHECK-8M-NEXT:    bic r0, r0, #1
898; CHECK-8M-NEXT:    sub sp, #136
899; CHECK-8M-NEXT:    vmov r12, s0
900; CHECK-8M-NEXT:    vlstm sp
901; CHECK-8M-NEXT:    vmov s0, r12
902; CHECK-8M-NEXT:    ldr r1, [sp, #64]
903; CHECK-8M-NEXT:    bic r1, r1, #159
904; CHECK-8M-NEXT:    bic r1, r1, #4026531840
905; CHECK-8M-NEXT:    vmsr fpscr, r1
906; CHECK-8M-NEXT:    mov r1, r0
907; CHECK-8M-NEXT:    mov r2, r0
908; CHECK-8M-NEXT:    mov r3, r0
909; CHECK-8M-NEXT:    mov r4, r0
910; CHECK-8M-NEXT:    mov r5, r0
911; CHECK-8M-NEXT:    mov r6, r0
912; CHECK-8M-NEXT:    mov r7, r0
913; CHECK-8M-NEXT:    mov r8, r0
914; CHECK-8M-NEXT:    mov r9, r0
915; CHECK-8M-NEXT:    mov r10, r0
916; CHECK-8M-NEXT:    mov r11, r0
917; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
918; CHECK-8M-NEXT:    blxns r0
919; CHECK-8M-NEXT:    vmov r12, s0
920; CHECK-8M-NEXT:    vlldm sp
921; CHECK-8M-NEXT:    vmov s0, r12
922; CHECK-8M-NEXT:    add sp, #136
923; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
924; CHECK-8M-NEXT:    pop {r7, pc}
925; CHECK-8M-NEXT:    .p2align 2
926; CHECK-8M-NEXT:  @ %bb.1:
927; CHECK-8M-NEXT:  .LCPI12_0:
928; CHECK-8M-NEXT:    .long 0x00004900 @ float 2.61874657E-41
929;
930; CHECK-NO-MVE-LABEL: h2:
931; CHECK-NO-MVE:       @ %bb.0: @ %entry
932; CHECK-NO-MVE-NEXT:    push {r7, lr}
933; CHECK-NO-MVE-NEXT:    vldr s0, .LCPI12_0
934; CHECK-NO-MVE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
935; CHECK-NO-MVE-NEXT:    bic r0, r0, #1
936; CHECK-NO-MVE-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
937; CHECK-NO-MVE-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
938; CHECK-NO-MVE-NEXT:    vstr fpcxts, [sp, #-8]!
939; CHECK-NO-MVE-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
940; CHECK-NO-MVE-NEXT:    blxns r0
941; CHECK-NO-MVE-NEXT:    vldr fpcxts, [sp], #8
942; CHECK-NO-MVE-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
943; CHECK-NO-MVE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
944; CHECK-NO-MVE-NEXT:    pop {r7, pc}
945; CHECK-NO-MVE-NEXT:    .p2align 2
946; CHECK-NO-MVE-NEXT:  @ %bb.1:
947; CHECK-NO-MVE-NEXT:  .LCPI12_0:
948; CHECK-NO-MVE-NEXT:    .long 0x00004900 @ float 2.61874657E-41
949;
950; CHECK-MVE-LABEL: h2:
951; CHECK-MVE:       @ %bb.0: @ %entry
952; CHECK-MVE-NEXT:    push {r7, lr}
953; CHECK-MVE-NEXT:    vmov.f16 s0, #1.000000e+01
954; CHECK-MVE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
955; CHECK-MVE-NEXT:    bic r0, r0, #1
956; CHECK-MVE-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
957; CHECK-MVE-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
958; CHECK-MVE-NEXT:    vstr fpcxts, [sp, #-8]!
959; CHECK-MVE-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
960; CHECK-MVE-NEXT:    blxns r0
961; CHECK-MVE-NEXT:    vldr fpcxts, [sp], #8
962; CHECK-MVE-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
963; CHECK-MVE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
964; CHECK-MVE-NEXT:    pop {r7, pc}
965entry:
966  %call = call half %hptr(half 10.0) "cmse_nonsecure_call" nounwind
967  ret half %call
968}
969
970define half @h3(half (half)* nocapture %hptr) nounwind {
971; CHECK-8M-LABEL: h3:
972; CHECK-8M:       @ %bb.0: @ %entry
973; CHECK-8M-NEXT:    push {r7, lr}
974; CHECK-8M-NEXT:    vldr s0, .LCPI13_0
975; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
976; CHECK-8M-NEXT:    bic r0, r0, #1
977; CHECK-8M-NEXT:    sub sp, #136
978; CHECK-8M-NEXT:    vmov r12, s0
979; CHECK-8M-NEXT:    vlstm sp
980; CHECK-8M-NEXT:    vmov s0, r12
981; CHECK-8M-NEXT:    ldr r1, [sp, #64]
982; CHECK-8M-NEXT:    bic r1, r1, #159
983; CHECK-8M-NEXT:    bic r1, r1, #4026531840
984; CHECK-8M-NEXT:    vmsr fpscr, r1
985; CHECK-8M-NEXT:    mov r1, r0
986; CHECK-8M-NEXT:    mov r2, r0
987; CHECK-8M-NEXT:    mov r3, r0
988; CHECK-8M-NEXT:    mov r4, r0
989; CHECK-8M-NEXT:    mov r5, r0
990; CHECK-8M-NEXT:    mov r6, r0
991; CHECK-8M-NEXT:    mov r7, r0
992; CHECK-8M-NEXT:    mov r8, r0
993; CHECK-8M-NEXT:    mov r9, r0
994; CHECK-8M-NEXT:    mov r10, r0
995; CHECK-8M-NEXT:    mov r11, r0
996; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
997; CHECK-8M-NEXT:    blxns r0
998; CHECK-8M-NEXT:    vmov r12, s0
999; CHECK-8M-NEXT:    vlldm sp
1000; CHECK-8M-NEXT:    vmov s0, r12
1001; CHECK-8M-NEXT:    add sp, #136
1002; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
1003; CHECK-8M-NEXT:    pop {r7, pc}
1004; CHECK-8M-NEXT:    .p2align 2
1005; CHECK-8M-NEXT:  @ %bb.1:
1006; CHECK-8M-NEXT:  .LCPI13_0:
1007; CHECK-8M-NEXT:    .long 0x00004900 @ float 2.61874657E-41
1008;
1009; CHECK-NO-MVE-LABEL: h3:
1010; CHECK-NO-MVE:       @ %bb.0: @ %entry
1011; CHECK-NO-MVE-NEXT:    push {r7, lr}
1012; CHECK-NO-MVE-NEXT:    vldr s0, .LCPI13_0
1013; CHECK-NO-MVE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
1014; CHECK-NO-MVE-NEXT:    bic r0, r0, #1
1015; CHECK-NO-MVE-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1016; CHECK-NO-MVE-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
1017; CHECK-NO-MVE-NEXT:    vstr fpcxts, [sp, #-8]!
1018; CHECK-NO-MVE-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
1019; CHECK-NO-MVE-NEXT:    blxns r0
1020; CHECK-NO-MVE-NEXT:    vldr fpcxts, [sp], #8
1021; CHECK-NO-MVE-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1022; CHECK-NO-MVE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
1023; CHECK-NO-MVE-NEXT:    pop {r7, pc}
1024; CHECK-NO-MVE-NEXT:    .p2align 2
1025; CHECK-NO-MVE-NEXT:  @ %bb.1:
1026; CHECK-NO-MVE-NEXT:  .LCPI13_0:
1027; CHECK-NO-MVE-NEXT:    .long 0x00004900 @ float 2.61874657E-41
1028;
1029; CHECK-MVE-LABEL: h3:
1030; CHECK-MVE:       @ %bb.0: @ %entry
1031; CHECK-MVE-NEXT:    push {r7, lr}
1032; CHECK-MVE-NEXT:    vmov.f16 s0, #1.000000e+01
1033; CHECK-MVE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
1034; CHECK-MVE-NEXT:    bic r0, r0, #1
1035; CHECK-MVE-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1036; CHECK-MVE-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
1037; CHECK-MVE-NEXT:    vstr fpcxts, [sp, #-8]!
1038; CHECK-MVE-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
1039; CHECK-MVE-NEXT:    blxns r0
1040; CHECK-MVE-NEXT:    vldr fpcxts, [sp], #8
1041; CHECK-MVE-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1042; CHECK-MVE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
1043; CHECK-MVE-NEXT:    pop {r7, pc}
1044entry:
1045  %call = tail call half %hptr(half 10.0) "cmse_nonsecure_call" nounwind
1046  ret half %call
1047}
1048
1049define half @h4(half ()* nocapture %hptr) nounwind {
1050; CHECK-8M-LABEL: h4:
1051; CHECK-8M:       @ %bb.0: @ %entry
1052; CHECK-8M-NEXT:    push {r7, lr}
1053; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
1054; CHECK-8M-NEXT:    bic r0, r0, #1
1055; CHECK-8M-NEXT:    sub sp, #136
1056; CHECK-8M-NEXT:    vlstm sp
1057; CHECK-8M-NEXT:    mov r1, r0
1058; CHECK-8M-NEXT:    mov r2, r0
1059; CHECK-8M-NEXT:    mov r3, r0
1060; CHECK-8M-NEXT:    mov r4, r0
1061; CHECK-8M-NEXT:    mov r5, r0
1062; CHECK-8M-NEXT:    mov r6, r0
1063; CHECK-8M-NEXT:    mov r7, r0
1064; CHECK-8M-NEXT:    mov r8, r0
1065; CHECK-8M-NEXT:    mov r9, r0
1066; CHECK-8M-NEXT:    mov r10, r0
1067; CHECK-8M-NEXT:    mov r11, r0
1068; CHECK-8M-NEXT:    mov r12, r0
1069; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
1070; CHECK-8M-NEXT:    blxns r0
1071; CHECK-8M-NEXT:    vmov r12, s0
1072; CHECK-8M-NEXT:    vlldm sp
1073; CHECK-8M-NEXT:    vmov s0, r12
1074; CHECK-8M-NEXT:    add sp, #136
1075; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
1076; CHECK-8M-NEXT:    pop {r7, pc}
1077;
1078; CHECK-81M-LABEL: h4:
1079; CHECK-81M:       @ %bb.0: @ %entry
1080; CHECK-81M-NEXT:    push {r7, lr}
1081; CHECK-81M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
1082; CHECK-81M-NEXT:    bic r0, r0, #1
1083; CHECK-81M-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1084; CHECK-81M-NEXT:    vscclrm {s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
1085; CHECK-81M-NEXT:    vstr fpcxts, [sp, #-8]!
1086; CHECK-81M-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
1087; CHECK-81M-NEXT:    blxns r0
1088; CHECK-81M-NEXT:    vldr fpcxts, [sp], #8
1089; CHECK-81M-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1090; CHECK-81M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
1091; CHECK-81M-NEXT:    pop {r7, pc}
1092entry:
1093  %call = call half %hptr() "cmse_nonsecure_call" nounwind
1094  ret half %call
1095}
1096
1097define half @h1_minsize(half (half)* nocapture %hptr) "cmse_nonsecure_entry" minsize nounwind {
1098; CHECK-8M-LABEL: h1_minsize:
1099; CHECK-8M:       @ %bb.0: @ %entry
1100; CHECK-8M-NEXT:    push {r7, lr}
1101; CHECK-8M-NEXT:    vldr s0, .LCPI15_0
1102; CHECK-8M-NEXT:    blx r0
1103; CHECK-8M-NEXT:    vmov r0, s0
1104; CHECK-8M-NEXT:    uxth r0, r0
1105; CHECK-8M-NEXT:    vmov s0, r0
1106; CHECK-8M-NEXT:    pop.w {r7, lr}
1107; CHECK-8M-NEXT:    vmrs r12, fpscr
1108; CHECK-8M-NEXT:    vmov s1, lr
1109; CHECK-8M-NEXT:    vmov d1, lr, lr
1110; CHECK-8M-NEXT:    mov r0, lr
1111; CHECK-8M-NEXT:    vmov d2, lr, lr
1112; CHECK-8M-NEXT:    mov r1, lr
1113; CHECK-8M-NEXT:    vmov d3, lr, lr
1114; CHECK-8M-NEXT:    mov r2, lr
1115; CHECK-8M-NEXT:    vmov d4, lr, lr
1116; CHECK-8M-NEXT:    mov r3, lr
1117; CHECK-8M-NEXT:    vmov d5, lr, lr
1118; CHECK-8M-NEXT:    vmov d6, lr, lr
1119; CHECK-8M-NEXT:    vmov d7, lr, lr
1120; CHECK-8M-NEXT:    bic r12, r12, #159
1121; CHECK-8M-NEXT:    bic r12, r12, #4026531840
1122; CHECK-8M-NEXT:    vmsr fpscr, r12
1123; CHECK-8M-NEXT:    mov r12, lr
1124; CHECK-8M-NEXT:    msr apsr_nzcvqg, lr
1125; CHECK-8M-NEXT:    bxns lr
1126; CHECK-8M-NEXT:    .p2align 2
1127; CHECK-8M-NEXT:  @ %bb.1:
1128; CHECK-8M-NEXT:  .LCPI15_0:
1129; CHECK-8M-NEXT:    .long 0x00004900 @ float 2.61874657E-41
1130;
1131; CHECK-NO-MVE-LABEL: h1_minsize:
1132; CHECK-NO-MVE:       @ %bb.0: @ %entry
1133; CHECK-NO-MVE-NEXT:    vstr fpcxtns, [sp, #-4]!
1134; CHECK-NO-MVE-NEXT:    push {r6, r7, lr}
1135; CHECK-NO-MVE-NEXT:    vldr s0, .LCPI15_0
1136; CHECK-NO-MVE-NEXT:    blx r0
1137; CHECK-NO-MVE-NEXT:    vmov r0, s0
1138; CHECK-NO-MVE-NEXT:    uxth r0, r0
1139; CHECK-NO-MVE-NEXT:    vmov s0, r0
1140; CHECK-NO-MVE-NEXT:    pop.w {r3, r7, lr}
1141; CHECK-NO-MVE-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
1142; CHECK-NO-MVE-NEXT:    vldr fpcxtns, [sp], #4
1143; CHECK-NO-MVE-NEXT:    clrm {r0, r1, r2, r3, r12, apsr}
1144; CHECK-NO-MVE-NEXT:    bxns lr
1145; CHECK-NO-MVE-NEXT:    .p2align 2
1146; CHECK-NO-MVE-NEXT:  @ %bb.1:
1147; CHECK-NO-MVE-NEXT:  .LCPI15_0:
1148; CHECK-NO-MVE-NEXT:    .long 0x00004900 @ float 2.61874657E-41
1149;
1150; CHECK-MVE-LABEL: h1_minsize:
1151; CHECK-MVE:       @ %bb.0: @ %entry
1152; CHECK-MVE-NEXT:    vstr fpcxtns, [sp, #-4]!
1153; CHECK-MVE-NEXT:    push {r6, r7, lr}
1154; CHECK-MVE-NEXT:    vmov.f16 s0, #1.000000e+01
1155; CHECK-MVE-NEXT:    blx r0
1156; CHECK-MVE-NEXT:    vmov.f16 r0, s0
1157; CHECK-MVE-NEXT:    vmov s0, r0
1158; CHECK-MVE-NEXT:    pop.w {r3, r7, lr}
1159; CHECK-MVE-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
1160; CHECK-MVE-NEXT:    vldr fpcxtns, [sp], #4
1161; CHECK-MVE-NEXT:    clrm {r0, r1, r2, r3, r12, apsr}
1162; CHECK-MVE-NEXT:    bxns lr
1163entry:
1164  %call = call half %hptr(half 10.0) nounwind
1165  ret half %call
1166}
1167
1168define half @h1_arg(half (half)* nocapture %hptr, half %harg) nounwind {
1169; CHECK-8M-LABEL: h1_arg:
1170; CHECK-8M:       @ %bb.0: @ %entry
1171; CHECK-8M-NEXT:    push {r7, lr}
1172; CHECK-8M-NEXT:    vmov r1, s0
1173; CHECK-8M-NEXT:    uxth r1, r1
1174; CHECK-8M-NEXT:    vmov s0, r1
1175; CHECK-8M-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
1176; CHECK-8M-NEXT:    bic r0, r0, #1
1177; CHECK-8M-NEXT:    sub sp, #136
1178; CHECK-8M-NEXT:    vmov r12, s0
1179; CHECK-8M-NEXT:    vlstm sp
1180; CHECK-8M-NEXT:    vmov s0, r12
1181; CHECK-8M-NEXT:    ldr r1, [sp, #64]
1182; CHECK-8M-NEXT:    bic r1, r1, #159
1183; CHECK-8M-NEXT:    bic r1, r1, #4026531840
1184; CHECK-8M-NEXT:    vmsr fpscr, r1
1185; CHECK-8M-NEXT:    mov r1, r0
1186; CHECK-8M-NEXT:    mov r2, r0
1187; CHECK-8M-NEXT:    mov r3, r0
1188; CHECK-8M-NEXT:    mov r4, r0
1189; CHECK-8M-NEXT:    mov r5, r0
1190; CHECK-8M-NEXT:    mov r6, r0
1191; CHECK-8M-NEXT:    mov r7, r0
1192; CHECK-8M-NEXT:    mov r8, r0
1193; CHECK-8M-NEXT:    mov r9, r0
1194; CHECK-8M-NEXT:    mov r10, r0
1195; CHECK-8M-NEXT:    mov r11, r0
1196; CHECK-8M-NEXT:    msr apsr_nzcvqg, r0
1197; CHECK-8M-NEXT:    blxns r0
1198; CHECK-8M-NEXT:    vmov r12, s0
1199; CHECK-8M-NEXT:    vlldm sp
1200; CHECK-8M-NEXT:    vmov s0, r12
1201; CHECK-8M-NEXT:    add sp, #136
1202; CHECK-8M-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
1203; CHECK-8M-NEXT:    pop {r7, pc}
1204;
1205; CHECK-NO-MVE-LABEL: h1_arg:
1206; CHECK-NO-MVE:       @ %bb.0: @ %entry
1207; CHECK-NO-MVE-NEXT:    push {r7, lr}
1208; CHECK-NO-MVE-NEXT:    vmov r1, s0
1209; CHECK-NO-MVE-NEXT:    uxth r1, r1
1210; CHECK-NO-MVE-NEXT:    vmov s0, r1
1211; CHECK-NO-MVE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
1212; CHECK-NO-MVE-NEXT:    bic r0, r0, #1
1213; CHECK-NO-MVE-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1214; CHECK-NO-MVE-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
1215; CHECK-NO-MVE-NEXT:    vstr fpcxts, [sp, #-8]!
1216; CHECK-NO-MVE-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
1217; CHECK-NO-MVE-NEXT:    blxns r0
1218; CHECK-NO-MVE-NEXT:    vldr fpcxts, [sp], #8
1219; CHECK-NO-MVE-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1220; CHECK-NO-MVE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
1221; CHECK-NO-MVE-NEXT:    pop {r7, pc}
1222;
1223; CHECK-MVE-LABEL: h1_arg:
1224; CHECK-MVE:       @ %bb.0: @ %entry
1225; CHECK-MVE-NEXT:    push {r7, lr}
1226; CHECK-MVE-NEXT:    vmov.f16 r1, s0
1227; CHECK-MVE-NEXT:    vmov s0, r1
1228; CHECK-MVE-NEXT:    push.w {r4, r5, r6, r7, r8, r9, r10, r11}
1229; CHECK-MVE-NEXT:    bic r0, r0, #1
1230; CHECK-MVE-NEXT:    vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1231; CHECK-MVE-NEXT:    vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
1232; CHECK-MVE-NEXT:    vstr fpcxts, [sp, #-8]!
1233; CHECK-MVE-NEXT:    clrm {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, apsr}
1234; CHECK-MVE-NEXT:    blxns r0
1235; CHECK-MVE-NEXT:    vldr fpcxts, [sp], #8
1236; CHECK-MVE-NEXT:    vpop {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
1237; CHECK-MVE-NEXT:    pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
1238; CHECK-MVE-NEXT:    pop {r7, pc}
1239entry:
1240  %call = call half %hptr(half %harg) "cmse_nonsecure_call" nounwind
1241  ret half %call
1242}
1243
1244