1; RUN: llc -O0 -march=amdgcn -mcpu=gfx900 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-O0 %s
2; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-O3 %s
3
4; NOTE: llvm.amdgcn.wwm is deprecated, use llvm.amdgcn.strict.wwm instead.
5
6; GFX9-LABEL: {{^}}no_cfg:
7define amdgpu_cs void @no_cfg(<4 x i32> inreg %tmp14) {
8  %tmp100 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %tmp14, i32 0, i32 0, i32 0)
9  %tmp101 = bitcast <2 x float> %tmp100 to <2 x i32>
10  %tmp102 = extractelement <2 x i32> %tmp101, i32 0
11  %tmp103 = extractelement <2 x i32> %tmp101, i32 1
12  %tmp105 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp102, i32 0)
13  %tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp103, i32 0)
14
15; GFX9: s_or_saveexec_b64 s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, -1
16
17; GFX9-DAG: v_mov_b32_dpp v[[FIRST_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf
18; GFX9-O3-DAG: v_add_u32_e32 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]]
19; GFX9-O0-DAG: v_add_u32_e64 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]]
20; GFX9-DAG: v_mov_b32_e32 v[[FIRST:[0-9]+]], v[[FIRST_ADD]]
21  %tmp120 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp105, i32 323, i32 12, i32 15, i1 false)
22  %tmp121 = add i32 %tmp105, %tmp120
23  %tmp122 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp121)
24
25; GFX9-DAG: v_mov_b32_dpp v[[SECOND_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf
26; GFX9-O3-DAG: v_add_u32_e32 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]]
27; GFX9-O0-DAG: v_add_u32_e64 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]]
28; GFX9-DAG: v_mov_b32_e32 v[[SECOND:[0-9]+]], v[[SECOND_ADD]]
29  %tmp135 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp107, i32 323, i32 12, i32 15, i1 false)
30  %tmp136 = add i32 %tmp107, %tmp135
31  %tmp137 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp136)
32
33; GFX9-O3: v_cmp_eq_u32_e32 vcc, v[[FIRST]], v[[SECOND]]
34; GFX9-O0: v_cmp_eq_u32_e64 s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v[[FIRST]], v[[SECOND]]
35  %tmp138 = icmp eq i32 %tmp122, %tmp137
36  %tmp139 = sext i1 %tmp138 to i32
37  %tmp140 = shl nsw i32 %tmp139, 1
38  %tmp141 = and i32 %tmp140, 2
39  %tmp145 = bitcast i32 %tmp141 to float
40  call void @llvm.amdgcn.raw.buffer.store.f32(float %tmp145, <4 x i32> %tmp14, i32 4, i32 0, i32 0)
41  ret void
42}
43
44; GFX9-LABEL: {{^}}cfg:
45define amdgpu_cs void @cfg(<4 x i32> inreg %tmp14, i32 %arg) {
46entry:
47  %tmp100 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %tmp14, i32 0, i32 0, i32 0)
48  %tmp101 = bitcast <2 x float> %tmp100 to <2 x i32>
49  %tmp102 = extractelement <2 x i32> %tmp101, i32 0
50  %tmp105 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp102, i32 0)
51
52; GFX9: v_mov_b32_dpp v[[FIRST_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf
53; GFX9-O3: v_add_u32_e32 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]]
54; GFX9-O0: v_add_u32_e64 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]]
55; GFX9: v_mov_b32_e32 v[[FIRST:[0-9]+]], v[[FIRST_ADD]]
56; GFX9-O0: buffer_store_dword v[[FIRST]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[FIRST_IMM_OFFSET:[0-9]+]]
57  %tmp120 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp105, i32 323, i32 12, i32 15, i1 false)
58  %tmp121 = add i32 %tmp105, %tmp120
59  %tmp122 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp121)
60
61  %cond = icmp eq i32 %arg, 0
62  br i1 %cond, label %if, label %merge
63if:
64  %tmp103 = extractelement <2 x i32> %tmp101, i32 1
65  %tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp103, i32 0)
66
67; GFX9: v_mov_b32_dpp v[[SECOND_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf
68; GFX9-O3: v_add_u32_e32 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]]
69; GFX9-O0: v_add_u32_e64 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]]
70; GFX9: v_mov_b32_e32 v[[SECOND:[0-9]+]], v[[SECOND_ADD]]
71; GFX9-O0: buffer_store_dword v[[SECOND]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[SECOND_IMM_OFFSET:[0-9]+]]
72  %tmp135 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp107, i32 323, i32 12, i32 15, i1 false)
73  %tmp136 = add i32 %tmp107, %tmp135
74  %tmp137 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp136)
75  br label %merge
76
77merge:
78  %merge_value = phi i32 [ 0, %entry ], [%tmp137, %if ]
79; GFX9-O3: v_cmp_eq_u32_e32 vcc, v[[FIRST]], v[[SECOND]]
80; GFX9-O0: buffer_load_dword v[[FIRST:[0-9]+]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[FIRST_IMM_OFFSET]]
81; GFX9-O0: buffer_load_dword v[[SECOND:[0-9]+]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[SECOND_IMM_OFFSET]]
82; GFX9-O0: v_cmp_eq_u32_e64 s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v[[FIRST]], v[[SECOND]]
83  %tmp138 = icmp eq i32 %tmp122, %merge_value
84  %tmp139 = sext i1 %tmp138 to i32
85  %tmp140 = shl nsw i32 %tmp139, 1
86  %tmp141 = and i32 %tmp140, 2
87  %tmp145 = bitcast i32 %tmp141 to float
88  call void @llvm.amdgcn.raw.buffer.store.f32(float %tmp145, <4 x i32> %tmp14, i32 4, i32 0, i32 0)
89  ret void
90}
91
92; GFX9-LABEL: {{^}}called:
93define hidden i32 @called(i32 %a) noinline {
94; GFX9-O3: v_add_u32_e32 v1, v0, v0
95; GFX9-O0: v_add_u32_e64 v1, v0, v0
96  %add = add i32 %a, %a
97; GFX9: v_mul_lo_u32 v0, v1, v0
98  %mul = mul i32 %add, %a
99; GFX9-O3: v_sub_u32_e32 v0, v0, v1
100; GFX9-O0: v_sub_u32_e64 v0, v0, v1
101  %sub = sub i32 %mul, %add
102  ret i32 %sub
103}
104
105; GFX9-LABEL: {{^}}call:
106define amdgpu_kernel void @call(<4 x i32> inreg %tmp14, i32 inreg %arg) {
107; GFX9-DAG: s_load_dword [[ARG:s[0-9]+]]
108; GFX9-O0-DAG: s_mov_b32 s4, 0{{$}}
109; GFX9-O0-DAG: v_mov_b32_e32 v0, [[ARG]]
110; GFX9-O0-DAG: v_mov_b32_e32 v2, v0
111
112; GFX9-O3: v_mov_b32_e32 v2, [[ARG]]
113
114; GFX9-NEXT: s_not_b64 exec, exec
115; GFX9-O0-NEXT: v_mov_b32_e32 v2, s4
116; GFX9-O3-NEXT: v_mov_b32_e32 v2, 0
117; GFX9-NEXT: s_not_b64 exec, exec
118  %tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %arg, i32 0)
119; GFX9: v_mov_b32_e32 v0, v2
120; GFX9: s_swappc_b64
121  %tmp134 = call i32 @called(i32 %tmp107)
122; GFX9: v_mov_b32_e32 v1, v0
123; GFX9-O3: v_add_u32_e32 v1, v1, v2
124; GFX9-O0: v_add_u32_e64 v1, v1, v2
125  %tmp136 = add i32 %tmp134, %tmp107
126  %tmp137 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp136)
127; GFX9: buffer_store_dword v0
128  call void @llvm.amdgcn.raw.buffer.store.i32(i32 %tmp137, <4 x i32> %tmp14, i32 4, i32 0, i32 0)
129  ret void
130}
131
132; GFX9-LABEL: {{^}}called_i64:
133define i64 @called_i64(i64 %a) noinline {
134  %add = add i64 %a, %a
135  %mul = mul i64 %add, %a
136  %sub = sub i64 %mul, %add
137  ret i64 %sub
138}
139
140; GFX9-LABEL: {{^}}call_i64:
141define amdgpu_kernel void @call_i64(<4 x i32> inreg %tmp14, i64 inreg %arg) {
142; GFX9: s_load_dwordx2 s{{\[}}[[ARG_LO:[0-9]+]]:[[ARG_HI:[0-9]+]]{{\]}}
143
144; GFX9-O0: s_mov_b64 s{{\[}}[[ZERO_LO:[0-9]+]]:[[ZERO_HI:[0-9]+]]{{\]}}, 0{{$}}
145; GFX9-O0: v_mov_b32_e32 v0, s[[ARG_LO]]
146; GFX9-O0: v_mov_b32_e32 v1, s[[ARG_HI]]
147; GFX9-O0-DAG: v_mov_b32_e32 v10, v1
148; GFX9-O0-DAG: v_mov_b32_e32 v9, v0
149
150; GFX9-O3-DAG: v_mov_b32_e32 v7, s[[ARG_HI]]
151; GFX9-O3-DAG: v_mov_b32_e32 v6, s[[ARG_LO]]
152
153; GFX9: s_not_b64 exec, exec
154; GFX9-O0-NEXT: v_mov_b32_e32 v9, s[[ZERO_LO]]
155; GFX9-O0-NEXT: v_mov_b32_e32 v10, s[[ZERO_HI]]
156; GFX9-O3-NEXT: v_mov_b32_e32 v6, 0
157; GFX9-O3-NEXT: v_mov_b32_e32 v7, 0
158; GFX9-NEXT: s_not_b64 exec, exec
159  %tmp107 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %arg, i64 0)
160; GFX9: s_swappc_b64
161  %tmp134 = call i64 @called_i64(i64 %tmp107)
162  %tmp136 = add i64 %tmp134, %tmp107
163  %tmp137 = tail call i64 @llvm.amdgcn.wwm.i64(i64 %tmp136)
164  %tmp138 = bitcast i64 %tmp137 to <2 x i32>
165; GFX9: buffer_store_dwordx2
166  call void @llvm.amdgcn.raw.buffer.store.v2i32(<2 x i32> %tmp138, <4 x i32> %tmp14, i32 4, i32 0, i32 0)
167  ret void
168}
169
170; GFX9-LABEL: {{^}}_amdgpu_cs_main:
171define amdgpu_cs void @_amdgpu_cs_main(<4 x i32> inreg %desc, i32 %index) {
172  %tmp17 = shl i32 %index, 5
173; GFX9: buffer_load_dwordx4
174  %tmp18 = tail call <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32> %desc, i32 %tmp17, i32 0)
175  %.i0.upto1.bc = bitcast <4 x i32> %tmp18 to <2 x i64>
176  %tmp19 = or i32 %tmp17, 16
177; GFX9: buffer_load_dwordx2
178  %tmp20 = tail call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %desc, i32 %tmp19, i32 0)
179  %.i0.upto1.extract = extractelement <2 x i64> %.i0.upto1.bc, i32 0
180  %tmp22 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %.i0.upto1.extract, i64 9223372036854775807)
181  %tmp97 = tail call i64 @llvm.amdgcn.wwm.i64(i64 %tmp22)
182  %.i1.upto1.extract = extractelement <2 x i64> %.i0.upto1.bc, i32 1
183  %tmp99 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %.i1.upto1.extract, i64 9223372036854775807)
184  %tmp174 = tail call i64 @llvm.amdgcn.wwm.i64(i64 %tmp99)
185  %.i25 = bitcast <2 x i32> %tmp20 to i64
186  %tmp176 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %.i25, i64 9223372036854775807)
187  %tmp251 = tail call i64 @llvm.amdgcn.wwm.i64(i64 %tmp176)
188  %.cast = bitcast i64 %tmp97 to <2 x float>
189  %.cast6 = bitcast i64 %tmp174 to <2 x float>
190  %.cast7 = bitcast i64 %tmp251 to <2 x float>
191  %tmp254 = shufflevector <2 x float> %.cast, <2 x float> %.cast6, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
192; GFX9: buffer_store_dwordx4
193  tail call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %tmp254, <4 x i32> %desc, i32 %tmp17, i32 0, i32 0)
194  ; GFX9: buffer_store_dwordx2
195  tail call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %.cast7, <4 x i32> %desc, i32 %tmp19, i32 0, i32 0)
196  ret void
197}
198
199
200; GFX9-LABEL: {{^}}strict_wwm_no_cfg:
201define amdgpu_cs void @strict_wwm_no_cfg(<4 x i32> inreg %tmp14) {
202  %tmp100 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %tmp14, i32 0, i32 0, i32 0)
203  %tmp101 = bitcast <2 x float> %tmp100 to <2 x i32>
204  %tmp102 = extractelement <2 x i32> %tmp101, i32 0
205  %tmp103 = extractelement <2 x i32> %tmp101, i32 1
206  %tmp105 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp102, i32 0)
207  %tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp103, i32 0)
208
209; GFX9: s_or_saveexec_b64 s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, -1
210
211; GFX9-DAG: v_mov_b32_dpp v[[FIRST_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf
212; GFX9-O3-DAG: v_add_u32_e32 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]]
213; GFX9-O0-DAG: v_add_u32_e64 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]]
214; GFX9-DAG: v_mov_b32_e32 v[[FIRST:[0-9]+]], v[[FIRST_ADD]]
215  %tmp120 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp105, i32 323, i32 12, i32 15, i1 false)
216  %tmp121 = add i32 %tmp105, %tmp120
217  %tmp122 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp121)
218
219; GFX9-DAG: v_mov_b32_dpp v[[SECOND_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf
220; GFX9-O3-DAG: v_add_u32_e32 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]]
221; GFX9-O0-DAG: v_add_u32_e64 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]]
222; GFX9-DAG: v_mov_b32_e32 v[[SECOND:[0-9]+]], v[[SECOND_ADD]]
223  %tmp135 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp107, i32 323, i32 12, i32 15, i1 false)
224  %tmp136 = add i32 %tmp107, %tmp135
225  %tmp137 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp136)
226
227; GFX9-O3: v_cmp_eq_u32_e32 vcc, v[[FIRST]], v[[SECOND]]
228; GFX9-O0: v_cmp_eq_u32_e64 s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v[[FIRST]], v[[SECOND]]
229  %tmp138 = icmp eq i32 %tmp122, %tmp137
230  %tmp139 = sext i1 %tmp138 to i32
231  %tmp140 = shl nsw i32 %tmp139, 1
232  %tmp141 = and i32 %tmp140, 2
233  %tmp145 = bitcast i32 %tmp141 to float
234  call void @llvm.amdgcn.raw.buffer.store.f32(float %tmp145, <4 x i32> %tmp14, i32 4, i32 0, i32 0)
235  ret void
236}
237
238; GFX9-LABEL: {{^}}strict_wwm_cfg:
239define amdgpu_cs void @strict_wwm_cfg(<4 x i32> inreg %tmp14, i32 %arg) {
240entry:
241  %tmp100 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %tmp14, i32 0, i32 0, i32 0)
242  %tmp101 = bitcast <2 x float> %tmp100 to <2 x i32>
243  %tmp102 = extractelement <2 x i32> %tmp101, i32 0
244  %tmp105 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp102, i32 0)
245
246; GFX9: v_mov_b32_dpp v[[FIRST_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf
247; GFX9-O3: v_add_u32_e32 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]]
248; GFX9-O0: v_add_u32_e64 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]]
249; GFX9: v_mov_b32_e32 v[[FIRST:[0-9]+]], v[[FIRST_ADD]]
250; GFX9-O0: buffer_store_dword v[[FIRST]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[FIRST_IMM_OFFSET:[0-9]+]]
251  %tmp120 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp105, i32 323, i32 12, i32 15, i1 false)
252  %tmp121 = add i32 %tmp105, %tmp120
253  %tmp122 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp121)
254
255  %cond = icmp eq i32 %arg, 0
256  br i1 %cond, label %if, label %merge
257if:
258  %tmp103 = extractelement <2 x i32> %tmp101, i32 1
259  %tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp103, i32 0)
260
261; GFX9: v_mov_b32_dpp v[[SECOND_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf
262; GFX9-O3: v_add_u32_e32 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]]
263; GFX9-O0: v_add_u32_e64 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]]
264; GFX9: v_mov_b32_e32 v[[SECOND:[0-9]+]], v[[SECOND_ADD]]
265; GFX9-O0: buffer_store_dword v[[SECOND]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[SECOND_IMM_OFFSET:[0-9]+]]
266  %tmp135 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp107, i32 323, i32 12, i32 15, i1 false)
267  %tmp136 = add i32 %tmp107, %tmp135
268  %tmp137 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp136)
269  br label %merge
270
271merge:
272  %merge_value = phi i32 [ 0, %entry ], [%tmp137, %if ]
273; GFX9-O3: v_cmp_eq_u32_e32 vcc, v[[FIRST]], v[[SECOND]]
274; GFX9-O0: buffer_load_dword v[[FIRST:[0-9]+]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[FIRST_IMM_OFFSET]]
275; GFX9-O0: buffer_load_dword v[[SECOND:[0-9]+]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[SECOND_IMM_OFFSET]]
276; GFX9-O0: v_cmp_eq_u32_e64 s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v[[FIRST]], v[[SECOND]]
277  %tmp138 = icmp eq i32 %tmp122, %merge_value
278  %tmp139 = sext i1 %tmp138 to i32
279  %tmp140 = shl nsw i32 %tmp139, 1
280  %tmp141 = and i32 %tmp140, 2
281  %tmp145 = bitcast i32 %tmp141 to float
282  call void @llvm.amdgcn.raw.buffer.store.f32(float %tmp145, <4 x i32> %tmp14, i32 4, i32 0, i32 0)
283  ret void
284}
285
286; GFX9-LABEL: {{^}}strict_wwm_called:
287define hidden i32 @strict_wwm_called(i32 %a) noinline {
288; GFX9-O3: v_add_u32_e32 v1, v0, v0
289; GFX9-O0: v_add_u32_e64 v1, v0, v0
290  %add = add i32 %a, %a
291; GFX9: v_mul_lo_u32 v0, v1, v0
292  %mul = mul i32 %add, %a
293; GFX9-O3: v_sub_u32_e32 v0, v0, v1
294; GFX9-O0: v_sub_u32_e64 v0, v0, v1
295  %sub = sub i32 %mul, %add
296  ret i32 %sub
297}
298
299; GFX9-LABEL: {{^}}strict_wwm_call:
300define amdgpu_kernel void @strict_wwm_call(<4 x i32> inreg %tmp14, i32 inreg %arg) {
301; GFX9-DAG: s_load_dword [[ARG:s[0-9]+]]
302; GFX9-O0-DAG: s_mov_b32 s4, 0{{$}}
303; GFX9-O0-DAG: v_mov_b32_e32 v0, [[ARG]]
304; GFX9-O0-DAG: v_mov_b32_e32 v2, v0
305
306; GFX9-O3: v_mov_b32_e32 v2, [[ARG]]
307
308; GFX9-NEXT: s_not_b64 exec, exec
309; GFX9-O0-NEXT: v_mov_b32_e32 v2, s4
310; GFX9-O3-NEXT: v_mov_b32_e32 v2, 0
311; GFX9-NEXT: s_not_b64 exec, exec
312  %tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %arg, i32 0)
313; GFX9: v_mov_b32_e32 v0, v2
314; GFX9: s_swappc_b64
315  %tmp134 = call i32 @strict_wwm_called(i32 %tmp107)
316; GFX9: v_mov_b32_e32 v1, v0
317; GFX9-O3: v_add_u32_e32 v1, v1, v2
318; GFX9-O0: v_add_u32_e64 v1, v1, v2
319  %tmp136 = add i32 %tmp134, %tmp107
320  %tmp137 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp136)
321; GFX9: buffer_store_dword v0
322  call void @llvm.amdgcn.raw.buffer.store.i32(i32 %tmp137, <4 x i32> %tmp14, i32 4, i32 0, i32 0)
323  ret void
324}
325
326; GFX9-LABEL: {{^}}strict_wwm_called_i64:
327define i64 @strict_wwm_called_i64(i64 %a) noinline {
328  %add = add i64 %a, %a
329  %mul = mul i64 %add, %a
330  %sub = sub i64 %mul, %add
331  ret i64 %sub
332}
333
334; GFX9-LABEL: {{^}}strict_wwm_call_i64:
335define amdgpu_kernel void @strict_wwm_call_i64(<4 x i32> inreg %tmp14, i64 inreg %arg) {
336; GFX9: s_load_dwordx2 s{{\[}}[[ARG_LO:[0-9]+]]:[[ARG_HI:[0-9]+]]{{\]}}
337
338; GFX9-O0: s_mov_b64 s{{\[}}[[ZERO_LO:[0-9]+]]:[[ZERO_HI:[0-9]+]]{{\]}}, 0{{$}}
339; GFX9-O0: v_mov_b32_e32 v0, s[[ARG_LO]]
340; GFX9-O0: v_mov_b32_e32 v1, s[[ARG_HI]]
341; GFX9-O0-DAG: v_mov_b32_e32 v10, v1
342; GFX9-O0-DAG: v_mov_b32_e32 v9, v0
343
344; GFX9-O3-DAG: v_mov_b32_e32 v7, s[[ARG_HI]]
345; GFX9-O3-DAG: v_mov_b32_e32 v6, s[[ARG_LO]]
346
347; GFX9: s_not_b64 exec, exec
348; GFX9-O0-NEXT: v_mov_b32_e32 v9, s[[ZERO_LO]]
349; GFX9-O0-NEXT: v_mov_b32_e32 v10, s[[ZERO_HI]]
350; GFX9-O3-NEXT: v_mov_b32_e32 v6, 0
351; GFX9-O3-NEXT: v_mov_b32_e32 v7, 0
352; GFX9-NEXT: s_not_b64 exec, exec
353  %tmp107 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %arg, i64 0)
354; GFX9: s_swappc_b64
355  %tmp134 = call i64 @strict_wwm_called_i64(i64 %tmp107)
356  %tmp136 = add i64 %tmp134, %tmp107
357  %tmp137 = tail call i64 @llvm.amdgcn.strict.wwm.i64(i64 %tmp136)
358  %tmp138 = bitcast i64 %tmp137 to <2 x i32>
359; GFX9: buffer_store_dwordx2
360  call void @llvm.amdgcn.raw.buffer.store.v2i32(<2 x i32> %tmp138, <4 x i32> %tmp14, i32 4, i32 0, i32 0)
361  ret void
362}
363
364; GFX9-LABEL: {{^}}strict_wwm_amdgpu_cs_main:
365define amdgpu_cs void @strict_wwm_amdgpu_cs_main(<4 x i32> inreg %desc, i32 %index) {
366  %tmp17 = shl i32 %index, 5
367; GFX9: buffer_load_dwordx4
368  %tmp18 = tail call <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32> %desc, i32 %tmp17, i32 0)
369  %.i0.upto1.bc = bitcast <4 x i32> %tmp18 to <2 x i64>
370  %tmp19 = or i32 %tmp17, 16
371; GFX9: buffer_load_dwordx2
372  %tmp20 = tail call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %desc, i32 %tmp19, i32 0)
373  %.i0.upto1.extract = extractelement <2 x i64> %.i0.upto1.bc, i32 0
374  %tmp22 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %.i0.upto1.extract, i64 9223372036854775807)
375  %tmp97 = tail call i64 @llvm.amdgcn.strict.wwm.i64(i64 %tmp22)
376  %.i1.upto1.extract = extractelement <2 x i64> %.i0.upto1.bc, i32 1
377  %tmp99 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %.i1.upto1.extract, i64 9223372036854775807)
378  %tmp174 = tail call i64 @llvm.amdgcn.strict.wwm.i64(i64 %tmp99)
379  %.i25 = bitcast <2 x i32> %tmp20 to i64
380  %tmp176 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %.i25, i64 9223372036854775807)
381  %tmp251 = tail call i64 @llvm.amdgcn.strict.wwm.i64(i64 %tmp176)
382  %.cast = bitcast i64 %tmp97 to <2 x float>
383  %.cast6 = bitcast i64 %tmp174 to <2 x float>
384  %.cast7 = bitcast i64 %tmp251 to <2 x float>
385  %tmp254 = shufflevector <2 x float> %.cast, <2 x float> %.cast6, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
386; GFX9: buffer_store_dwordx4
387  tail call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %tmp254, <4 x i32> %desc, i32 %tmp17, i32 0, i32 0)
388  ; GFX9: buffer_store_dwordx2
389  tail call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %.cast7, <4 x i32> %desc, i32 %tmp19, i32 0, i32 0)
390  ret void
391}
392
393declare i32 @llvm.amdgcn.strict.wwm.i32(i32)
394declare i64 @llvm.amdgcn.strict.wwm.i64(i64)
395declare i32 @llvm.amdgcn.wwm.i32(i32)
396declare i64 @llvm.amdgcn.wwm.i64(i64)
397declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32)
398declare i64 @llvm.amdgcn.set.inactive.i64(i64, i64)
399declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1)
400declare <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32>, i32, i32, i32)
401declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32)
402declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32)
403declare void @llvm.amdgcn.raw.buffer.store.v2i32(<2 x i32>, <4 x i32>, i32, i32, i32)
404declare void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float>, <4 x i32>, i32, i32, i32)
405declare void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i32)
406declare <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32>, i32, i32)
407declare <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32>, i32, i32)
408