1; RUN: llc -O0 -march=amdgcn -mcpu=gfx900 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-O0 %s 2; RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-O3 %s 3 4; NOTE: llvm.amdgcn.wwm is deprecated, use llvm.amdgcn.strict.wwm instead. 5 6; GFX9-LABEL: {{^}}no_cfg: 7define amdgpu_cs void @no_cfg(<4 x i32> inreg %tmp14) { 8 %tmp100 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %tmp14, i32 0, i32 0, i32 0) 9 %tmp101 = bitcast <2 x float> %tmp100 to <2 x i32> 10 %tmp102 = extractelement <2 x i32> %tmp101, i32 0 11 %tmp103 = extractelement <2 x i32> %tmp101, i32 1 12 %tmp105 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp102, i32 0) 13 %tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp103, i32 0) 14 15; GFX9: s_or_saveexec_b64 s[{{[0-9]+}}:{{[0-9]+}}], -1 16 17; GFX9-DAG: v_mov_b32_dpp v[[FIRST_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf 18; GFX9-O3-DAG: v_add_u32_e32 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]] 19; GFX9-O0-DAG: v_add_u32_e64 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]] 20; GFX9-DAG: v_mov_b32_e32 v[[FIRST:[0-9]+]], v[[FIRST_ADD]] 21 %tmp120 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp105, i32 323, i32 12, i32 15, i1 false) 22 %tmp121 = add i32 %tmp105, %tmp120 23 %tmp122 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp121) 24 25; GFX9-DAG: v_mov_b32_dpp v[[SECOND_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf 26; GFX9-O3-DAG: v_add_u32_e32 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]] 27; GFX9-O0-DAG: v_add_u32_e64 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]] 28; GFX9-DAG: v_mov_b32_e32 v[[SECOND:[0-9]+]], v[[SECOND_ADD]] 29 %tmp135 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp107, i32 323, i32 12, i32 15, i1 false) 30 %tmp136 = add i32 %tmp107, %tmp135 31 %tmp137 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp136) 32 33; GFX9-O3: v_cmp_eq_u32_e32 vcc, v[[FIRST]], v[[SECOND]] 34; GFX9-O0: v_cmp_eq_u32_e64 s[{{[0-9]+}}:{{[0-9]+}}], v[[FIRST]], v[[SECOND]] 35 %tmp138 = icmp eq i32 %tmp122, %tmp137 36 %tmp139 = sext i1 %tmp138 to i32 37 %tmp140 = shl nsw i32 %tmp139, 1 38 %tmp141 = and i32 %tmp140, 2 39 %tmp145 = bitcast i32 %tmp141 to float 40 call void @llvm.amdgcn.raw.buffer.store.f32(float %tmp145, <4 x i32> %tmp14, i32 4, i32 0, i32 0) 41 ret void 42} 43 44; GFX9-LABEL: {{^}}cfg: 45define amdgpu_cs void @cfg(<4 x i32> inreg %tmp14, i32 %arg) { 46entry: 47 %tmp100 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %tmp14, i32 0, i32 0, i32 0) 48 %tmp101 = bitcast <2 x float> %tmp100 to <2 x i32> 49 %tmp102 = extractelement <2 x i32> %tmp101, i32 0 50 %tmp105 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp102, i32 0) 51 52; GFX9: v_mov_b32_dpp v[[FIRST_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf 53; GFX9-O3: v_add_u32_e32 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]] 54; GFX9-O0: v_add_u32_e64 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]] 55; GFX9: v_mov_b32_e32 v[[FIRST:[0-9]+]], v[[FIRST_ADD]] 56; GFX9-O0: buffer_store_dword v[[FIRST]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:[[FIRST_IMM_OFFSET:[0-9]+]] 57 %tmp120 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp105, i32 323, i32 12, i32 15, i1 false) 58 %tmp121 = add i32 %tmp105, %tmp120 59 %tmp122 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp121) 60 61 %cond = icmp eq i32 %arg, 0 62 br i1 %cond, label %if, label %merge 63if: 64 %tmp103 = extractelement <2 x i32> %tmp101, i32 1 65 %tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp103, i32 0) 66 67; GFX9: v_mov_b32_dpp v[[SECOND_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf 68; GFX9-O3: v_add_u32_e32 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]] 69; GFX9-O0: v_add_u32_e64 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]] 70; GFX9: v_mov_b32_e32 v[[SECOND:[0-9]+]], v[[SECOND_ADD]] 71; GFX9-O0: buffer_store_dword v[[SECOND]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:[[SECOND_IMM_OFFSET:[0-9]+]] 72 %tmp135 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp107, i32 323, i32 12, i32 15, i1 false) 73 %tmp136 = add i32 %tmp107, %tmp135 74 %tmp137 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp136) 75 br label %merge 76 77merge: 78 %merge_value = phi i32 [ 0, %entry ], [%tmp137, %if ] 79; GFX9-O3: v_cmp_eq_u32_e32 vcc, v[[FIRST]], v[[SECOND]] 80; GFX9-O0: buffer_load_dword v[[FIRST:[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:[[FIRST_IMM_OFFSET]] 81; GFX9-O0: buffer_load_dword v[[SECOND:[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:[[SECOND_IMM_OFFSET]] 82; GFX9-O0: v_cmp_eq_u32_e64 s[{{[0-9]+}}:{{[0-9]+}}], v[[FIRST]], v[[SECOND]] 83 %tmp138 = icmp eq i32 %tmp122, %merge_value 84 %tmp139 = sext i1 %tmp138 to i32 85 %tmp140 = shl nsw i32 %tmp139, 1 86 %tmp141 = and i32 %tmp140, 2 87 %tmp145 = bitcast i32 %tmp141 to float 88 call void @llvm.amdgcn.raw.buffer.store.f32(float %tmp145, <4 x i32> %tmp14, i32 4, i32 0, i32 0) 89 ret void 90} 91 92; GFX9-LABEL: {{^}}called: 93define hidden i32 @called(i32 %a) noinline { 94; GFX9-O3: v_add_u32_e32 v1, v0, v0 95; GFX9-O0: v_add_u32_e64 v1, v0, v0 96 %add = add i32 %a, %a 97; GFX9: v_mul_lo_u32 v0, v1, v0 98 %mul = mul i32 %add, %a 99; GFX9-O3: v_sub_u32_e32 v0, v0, v1 100; GFX9-O0: v_sub_u32_e64 v0, v0, v1 101 %sub = sub i32 %mul, %add 102 ret i32 %sub 103} 104 105; GFX9-LABEL: {{^}}call: 106define amdgpu_kernel void @call(<4 x i32> inreg %tmp14, i32 inreg %arg) { 107; GFX9-DAG: s_load_dword [[ARG:s[0-9]+]] 108; GFX9-O0-DAG: s_mov_b32 s4, 0{{$}} 109; GFX9-O0-DAG: v_mov_b32_e32 v2, [[ARG]] 110 111; GFX9-O3: v_mov_b32_e32 v2, [[ARG]] 112 113; GFX9-NEXT: s_not_b64 exec, exec 114; GFX9-O0-NEXT: v_mov_b32_e32 v2, s4 115; GFX9-O3-NEXT: v_mov_b32_e32 v2, 0 116; GFX9-NEXT: s_not_b64 exec, exec 117 %tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %arg, i32 0) 118; GFX9: v_mov_b32_e32 v0, v2 119; GFX9: s_swappc_b64 120 %tmp134 = call i32 @called(i32 %tmp107) 121; GFX9: v_mov_b32_e32 v1, v0 122; GFX9-O3: v_add_u32_e32 v1, v1, v2 123; GFX9-O0: v_add_u32_e64 v1, v1, v2 124 %tmp136 = add i32 %tmp134, %tmp107 125 %tmp137 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp136) 126; GFX9: buffer_store_dword v0 127 call void @llvm.amdgcn.raw.buffer.store.i32(i32 %tmp137, <4 x i32> %tmp14, i32 4, i32 0, i32 0) 128 ret void 129} 130 131; GFX9-LABEL: {{^}}called_i64: 132define i64 @called_i64(i64 %a) noinline { 133 %add = add i64 %a, %a 134 %mul = mul i64 %add, %a 135 %sub = sub i64 %mul, %add 136 ret i64 %sub 137} 138 139; GFX9-LABEL: {{^}}call_i64: 140define amdgpu_kernel void @call_i64(<4 x i32> inreg %tmp14, i64 inreg %arg) { 141; GFX9: s_load_dwordx2 s[[[ARG_LO:[0-9]+]]:[[ARG_HI:[0-9]+]]] 142 143; GFX9-O0: s_mov_b64 s[[[ZERO_LO:[0-9]+]]:[[ZERO_HI:[0-9]+]]], 0{{$}} 144; GFX9-O0-DAG: v_mov_b32_e32 v9, s[[ARG_HI]] 145; GFX9-O0-DAG: v_mov_b32_e32 v8, s[[ARG_LO]] 146 147; GFX9-O3-DAG: v_mov_b32_e32 v7, s[[ARG_HI]] 148; GFX9-O3-DAG: v_mov_b32_e32 v6, s[[ARG_LO]] 149 150; GFX9: s_not_b64 exec, exec 151; GFX9-O0-NEXT: v_mov_b32_e32 v8, s[[ZERO_LO]] 152; GFX9-O0-NEXT: v_mov_b32_e32 v9, s[[ZERO_HI]] 153; GFX9-O3-NEXT: v_mov_b32_e32 v6, 0 154; GFX9-O3-NEXT: v_mov_b32_e32 v7, 0 155; GFX9-NEXT: s_not_b64 exec, exec 156 %tmp107 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %arg, i64 0) 157; GFX9: s_swappc_b64 158 %tmp134 = call i64 @called_i64(i64 %tmp107) 159 %tmp136 = add i64 %tmp134, %tmp107 160 %tmp137 = tail call i64 @llvm.amdgcn.wwm.i64(i64 %tmp136) 161 %tmp138 = bitcast i64 %tmp137 to <2 x i32> 162; GFX9: buffer_store_dwordx2 163 call void @llvm.amdgcn.raw.buffer.store.v2i32(<2 x i32> %tmp138, <4 x i32> %tmp14, i32 4, i32 0, i32 0) 164 ret void 165} 166 167; GFX9-LABEL: {{^}}_amdgpu_cs_main: 168define amdgpu_cs void @_amdgpu_cs_main(<4 x i32> inreg %desc, i32 %index) { 169 %tmp17 = shl i32 %index, 5 170; GFX9: buffer_load_dwordx4 171 %tmp18 = tail call <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32> %desc, i32 %tmp17, i32 0) 172 %.i0.upto1.bc = bitcast <4 x i32> %tmp18 to <2 x i64> 173 %tmp19 = or i32 %tmp17, 16 174; GFX9: buffer_load_dwordx2 175 %tmp20 = tail call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %desc, i32 %tmp19, i32 0) 176 %.i0.upto1.extract = extractelement <2 x i64> %.i0.upto1.bc, i32 0 177 %tmp22 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %.i0.upto1.extract, i64 9223372036854775807) 178 %tmp97 = tail call i64 @llvm.amdgcn.wwm.i64(i64 %tmp22) 179 %.i1.upto1.extract = extractelement <2 x i64> %.i0.upto1.bc, i32 1 180 %tmp99 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %.i1.upto1.extract, i64 9223372036854775807) 181 %tmp174 = tail call i64 @llvm.amdgcn.wwm.i64(i64 %tmp99) 182 %.i25 = bitcast <2 x i32> %tmp20 to i64 183 %tmp176 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %.i25, i64 9223372036854775807) 184 %tmp251 = tail call i64 @llvm.amdgcn.wwm.i64(i64 %tmp176) 185 %.cast = bitcast i64 %tmp97 to <2 x float> 186 %.cast6 = bitcast i64 %tmp174 to <2 x float> 187 %.cast7 = bitcast i64 %tmp251 to <2 x float> 188 %tmp254 = shufflevector <2 x float> %.cast, <2 x float> %.cast6, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 189; GFX9: buffer_store_dwordx4 190 tail call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %tmp254, <4 x i32> %desc, i32 %tmp17, i32 0, i32 0) 191 ; GFX9: buffer_store_dwordx2 192 tail call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %.cast7, <4 x i32> %desc, i32 %tmp19, i32 0, i32 0) 193 ret void 194} 195 196 197; GFX9-LABEL: {{^}}strict_wwm_no_cfg: 198define amdgpu_cs void @strict_wwm_no_cfg(<4 x i32> inreg %tmp14) { 199 %tmp100 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %tmp14, i32 0, i32 0, i32 0) 200 %tmp101 = bitcast <2 x float> %tmp100 to <2 x i32> 201 %tmp102 = extractelement <2 x i32> %tmp101, i32 0 202 %tmp103 = extractelement <2 x i32> %tmp101, i32 1 203 %tmp105 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp102, i32 0) 204 %tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp103, i32 0) 205 206; GFX9: s_or_saveexec_b64 s[{{[0-9]+}}:{{[0-9]+}}], -1 207 208; GFX9-DAG: v_mov_b32_dpp v[[FIRST_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf 209; GFX9-O3-DAG: v_add_u32_e32 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]] 210; GFX9-O0-DAG: v_add_u32_e64 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]] 211; GFX9-DAG: v_mov_b32_e32 v[[FIRST:[0-9]+]], v[[FIRST_ADD]] 212 %tmp120 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp105, i32 323, i32 12, i32 15, i1 false) 213 %tmp121 = add i32 %tmp105, %tmp120 214 %tmp122 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp121) 215 216; GFX9-DAG: v_mov_b32_dpp v[[SECOND_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf 217; GFX9-O3-DAG: v_add_u32_e32 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]] 218; GFX9-O0-DAG: v_add_u32_e64 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]] 219; GFX9-DAG: v_mov_b32_e32 v[[SECOND:[0-9]+]], v[[SECOND_ADD]] 220 %tmp135 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp107, i32 323, i32 12, i32 15, i1 false) 221 %tmp136 = add i32 %tmp107, %tmp135 222 %tmp137 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp136) 223 224; GFX9-O3: v_cmp_eq_u32_e32 vcc, v[[FIRST]], v[[SECOND]] 225; GFX9-O0: v_cmp_eq_u32_e64 s[{{[0-9]+}}:{{[0-9]+}}], v[[FIRST]], v[[SECOND]] 226 %tmp138 = icmp eq i32 %tmp122, %tmp137 227 %tmp139 = sext i1 %tmp138 to i32 228 %tmp140 = shl nsw i32 %tmp139, 1 229 %tmp141 = and i32 %tmp140, 2 230 %tmp145 = bitcast i32 %tmp141 to float 231 call void @llvm.amdgcn.raw.buffer.store.f32(float %tmp145, <4 x i32> %tmp14, i32 4, i32 0, i32 0) 232 ret void 233} 234 235; GFX9-LABEL: {{^}}strict_wwm_cfg: 236define amdgpu_cs void @strict_wwm_cfg(<4 x i32> inreg %tmp14, i32 %arg) { 237entry: 238 %tmp100 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %tmp14, i32 0, i32 0, i32 0) 239 %tmp101 = bitcast <2 x float> %tmp100 to <2 x i32> 240 %tmp102 = extractelement <2 x i32> %tmp101, i32 0 241 %tmp105 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp102, i32 0) 242 243; GFX9: v_mov_b32_dpp v[[FIRST_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf 244; GFX9-O3: v_add_u32_e32 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]] 245; GFX9-O0: v_add_u32_e64 v[[FIRST_ADD:[0-9]+]], v{{[0-9]+}}, v[[FIRST_MOV]] 246; GFX9: v_mov_b32_e32 v[[FIRST:[0-9]+]], v[[FIRST_ADD]] 247; GFX9-O0: buffer_store_dword v[[FIRST]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:[[FIRST_IMM_OFFSET:[0-9]+]] 248 %tmp120 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp105, i32 323, i32 12, i32 15, i1 false) 249 %tmp121 = add i32 %tmp105, %tmp120 250 %tmp122 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp121) 251 252 %cond = icmp eq i32 %arg, 0 253 br i1 %cond, label %if, label %merge 254if: 255 %tmp103 = extractelement <2 x i32> %tmp101, i32 1 256 %tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %tmp103, i32 0) 257 258; GFX9: v_mov_b32_dpp v[[SECOND_MOV:[0-9]+]], v{{[0-9]+}} row_bcast:31 row_mask:0xc bank_mask:0xf 259; GFX9-O3: v_add_u32_e32 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]] 260; GFX9-O0: v_add_u32_e64 v[[SECOND_ADD:[0-9]+]], v{{[0-9]+}}, v[[SECOND_MOV]] 261; GFX9: v_mov_b32_e32 v[[SECOND:[0-9]+]], v[[SECOND_ADD]] 262; GFX9-O0: buffer_store_dword v[[SECOND]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:[[SECOND_IMM_OFFSET:[0-9]+]] 263 %tmp135 = tail call i32 @llvm.amdgcn.update.dpp.i32(i32 0, i32 %tmp107, i32 323, i32 12, i32 15, i1 false) 264 %tmp136 = add i32 %tmp107, %tmp135 265 %tmp137 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp136) 266 br label %merge 267 268merge: 269 %merge_value = phi i32 [ 0, %entry ], [%tmp137, %if ] 270; GFX9-O3: v_cmp_eq_u32_e32 vcc, v[[FIRST]], v[[SECOND]] 271; GFX9-O0: buffer_load_dword v[[FIRST:[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:[[FIRST_IMM_OFFSET]] 272; GFX9-O0: buffer_load_dword v[[SECOND:[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:[[SECOND_IMM_OFFSET]] 273; GFX9-O0: v_cmp_eq_u32_e64 s[{{[0-9]+}}:{{[0-9]+}}], v[[FIRST]], v[[SECOND]] 274 %tmp138 = icmp eq i32 %tmp122, %merge_value 275 %tmp139 = sext i1 %tmp138 to i32 276 %tmp140 = shl nsw i32 %tmp139, 1 277 %tmp141 = and i32 %tmp140, 2 278 %tmp145 = bitcast i32 %tmp141 to float 279 call void @llvm.amdgcn.raw.buffer.store.f32(float %tmp145, <4 x i32> %tmp14, i32 4, i32 0, i32 0) 280 ret void 281} 282 283; GFX9-LABEL: {{^}}strict_wwm_called: 284define hidden i32 @strict_wwm_called(i32 %a) noinline { 285; GFX9-O3: v_add_u32_e32 v1, v0, v0 286; GFX9-O0: v_add_u32_e64 v1, v0, v0 287 %add = add i32 %a, %a 288; GFX9: v_mul_lo_u32 v0, v1, v0 289 %mul = mul i32 %add, %a 290; GFX9-O3: v_sub_u32_e32 v0, v0, v1 291; GFX9-O0: v_sub_u32_e64 v0, v0, v1 292 %sub = sub i32 %mul, %add 293 ret i32 %sub 294} 295 296; GFX9-LABEL: {{^}}strict_wwm_call: 297define amdgpu_kernel void @strict_wwm_call(<4 x i32> inreg %tmp14, i32 inreg %arg) { 298; GFX9-DAG: s_load_dword [[ARG:s[0-9]+]] 299; GFX9-O0-DAG: s_mov_b32 s4, 0{{$}} 300; GFX9-O0-DAG: v_mov_b32_e32 v2, [[ARG]] 301 302; GFX9-O3: v_mov_b32_e32 v2, [[ARG]] 303 304; GFX9-NEXT: s_not_b64 exec, exec 305; GFX9-O0-NEXT: v_mov_b32_e32 v2, s4 306; GFX9-O3-NEXT: v_mov_b32_e32 v2, 0 307; GFX9-NEXT: s_not_b64 exec, exec 308 %tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %arg, i32 0) 309; GFX9: v_mov_b32_e32 v0, v2 310; GFX9: s_swappc_b64 311 %tmp134 = call i32 @strict_wwm_called(i32 %tmp107) 312; GFX9: v_mov_b32_e32 v1, v0 313; GFX9-O3: v_add_u32_e32 v1, v1, v2 314; GFX9-O0: v_add_u32_e64 v1, v1, v2 315 %tmp136 = add i32 %tmp134, %tmp107 316 %tmp137 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp136) 317; GFX9: buffer_store_dword v0 318 call void @llvm.amdgcn.raw.buffer.store.i32(i32 %tmp137, <4 x i32> %tmp14, i32 4, i32 0, i32 0) 319 ret void 320} 321 322; GFX9-LABEL: {{^}}strict_wwm_called_i64: 323define i64 @strict_wwm_called_i64(i64 %a) noinline { 324 %add = add i64 %a, %a 325 %mul = mul i64 %add, %a 326 %sub = sub i64 %mul, %add 327 ret i64 %sub 328} 329 330; GFX9-LABEL: {{^}}strict_wwm_call_i64: 331define amdgpu_kernel void @strict_wwm_call_i64(<4 x i32> inreg %tmp14, i64 inreg %arg) { 332; GFX9: s_load_dwordx2 s[[[ARG_LO:[0-9]+]]:[[ARG_HI:[0-9]+]]] 333 334; GFX9-O0: s_mov_b64 s[[[ZERO_LO:[0-9]+]]:[[ZERO_HI:[0-9]+]]], 0{{$}} 335; GFX9-O0-DAG: v_mov_b32_e32 v9, s[[ARG_HI]] 336; GFX9-O0-DAG: v_mov_b32_e32 v8, s[[ARG_LO]] 337 338; GFX9-O3-DAG: v_mov_b32_e32 v7, s[[ARG_HI]] 339; GFX9-O3-DAG: v_mov_b32_e32 v6, s[[ARG_LO]] 340 341; GFX9: s_not_b64 exec, exec 342; GFX9-O0-NEXT: v_mov_b32_e32 v8, s[[ZERO_LO]] 343; GFX9-O0-NEXT: v_mov_b32_e32 v9, s[[ZERO_HI]] 344; GFX9-O3-NEXT: v_mov_b32_e32 v6, 0 345; GFX9-O3-NEXT: v_mov_b32_e32 v7, 0 346; GFX9-NEXT: s_not_b64 exec, exec 347 %tmp107 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %arg, i64 0) 348; GFX9: s_swappc_b64 349 %tmp134 = call i64 @strict_wwm_called_i64(i64 %tmp107) 350 %tmp136 = add i64 %tmp134, %tmp107 351 %tmp137 = tail call i64 @llvm.amdgcn.strict.wwm.i64(i64 %tmp136) 352 %tmp138 = bitcast i64 %tmp137 to <2 x i32> 353; GFX9: buffer_store_dwordx2 354 call void @llvm.amdgcn.raw.buffer.store.v2i32(<2 x i32> %tmp138, <4 x i32> %tmp14, i32 4, i32 0, i32 0) 355 ret void 356} 357 358; GFX9-LABEL: {{^}}strict_wwm_amdgpu_cs_main: 359define amdgpu_cs void @strict_wwm_amdgpu_cs_main(<4 x i32> inreg %desc, i32 %index) { 360 %tmp17 = shl i32 %index, 5 361; GFX9: buffer_load_dwordx4 362 %tmp18 = tail call <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32> %desc, i32 %tmp17, i32 0) 363 %.i0.upto1.bc = bitcast <4 x i32> %tmp18 to <2 x i64> 364 %tmp19 = or i32 %tmp17, 16 365; GFX9: buffer_load_dwordx2 366 %tmp20 = tail call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %desc, i32 %tmp19, i32 0) 367 %.i0.upto1.extract = extractelement <2 x i64> %.i0.upto1.bc, i32 0 368 %tmp22 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %.i0.upto1.extract, i64 9223372036854775807) 369 %tmp97 = tail call i64 @llvm.amdgcn.strict.wwm.i64(i64 %tmp22) 370 %.i1.upto1.extract = extractelement <2 x i64> %.i0.upto1.bc, i32 1 371 %tmp99 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %.i1.upto1.extract, i64 9223372036854775807) 372 %tmp174 = tail call i64 @llvm.amdgcn.strict.wwm.i64(i64 %tmp99) 373 %.i25 = bitcast <2 x i32> %tmp20 to i64 374 %tmp176 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %.i25, i64 9223372036854775807) 375 %tmp251 = tail call i64 @llvm.amdgcn.strict.wwm.i64(i64 %tmp176) 376 %.cast = bitcast i64 %tmp97 to <2 x float> 377 %.cast6 = bitcast i64 %tmp174 to <2 x float> 378 %.cast7 = bitcast i64 %tmp251 to <2 x float> 379 %tmp254 = shufflevector <2 x float> %.cast, <2 x float> %.cast6, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 380; GFX9: buffer_store_dwordx4 381 tail call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %tmp254, <4 x i32> %desc, i32 %tmp17, i32 0, i32 0) 382 ; GFX9: buffer_store_dwordx2 383 tail call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %.cast7, <4 x i32> %desc, i32 %tmp19, i32 0, i32 0) 384 ret void 385} 386 387declare i32 @llvm.amdgcn.strict.wwm.i32(i32) 388declare i64 @llvm.amdgcn.strict.wwm.i64(i64) 389declare i32 @llvm.amdgcn.wwm.i32(i32) 390declare i64 @llvm.amdgcn.wwm.i64(i64) 391declare i32 @llvm.amdgcn.set.inactive.i32(i32, i32) 392declare i64 @llvm.amdgcn.set.inactive.i64(i64, i64) 393declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1) 394declare <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32>, i32, i32, i32) 395declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32) 396declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32) 397declare void @llvm.amdgcn.raw.buffer.store.v2i32(<2 x i32>, <4 x i32>, i32, i32, i32) 398declare void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float>, <4 x i32>, i32, i32, i32) 399declare void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i32) 400declare <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32>, i32, i32) 401declare <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32>, i32, i32) 402