1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_urem_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_urem_i64:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
9; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
10; GCN-NEXT:    v_mov_b32_e32 v2, 0
11; GCN-NEXT:    s_mov_b32 s7, 0xf000
12; GCN-NEXT:    s_mov_b32 s6, -1
13; GCN-NEXT:    s_waitcnt lgkmcnt(0)
14; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
15; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
16; GCN-NEXT:    s_sub_u32 s2, 0, s12
17; GCN-NEXT:    s_subb_u32 s3, 0, s13
18; GCN-NEXT:    s_mov_b32 s4, s8
19; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
20; GCN-NEXT:    v_rcp_f32_e32 v0, v0
21; GCN-NEXT:    v_mov_b32_e32 v1, 0
22; GCN-NEXT:    s_mov_b32 s5, s9
23; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
24; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
25; GCN-NEXT:    v_trunc_f32_e32 v3, v3
26; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
27; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
28; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
29; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
30; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
31; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
32; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
33; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
34; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
35; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
36; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
37; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
38; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
39; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
40; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
41; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
42; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
43; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
44; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
45; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
46; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v1, vcc
47; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
48; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
49; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
50; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
51; GCN-NEXT:    v_mul_lo_u32 v6, s2, v4
52; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
53; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
54; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
55; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
56; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
57; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
58; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
59; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
60; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
61; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
62; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
63; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
64; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
65; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
66; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
67; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
68; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
69; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
70; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
71; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
72; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
73; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
74; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
75; GCN-NEXT:    v_mul_lo_u32 v4, s10, v3
76; GCN-NEXT:    v_mul_hi_u32 v5, s10, v0
77; GCN-NEXT:    v_mul_hi_u32 v6, s10, v3
78; GCN-NEXT:    v_mul_hi_u32 v7, s11, v3
79; GCN-NEXT:    v_mul_lo_u32 v3, s11, v3
80; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
81; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
82; GCN-NEXT:    v_mul_lo_u32 v6, s11, v0
83; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
84; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
85; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
86; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
87; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
88; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
89; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
90; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
91; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
92; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
93; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
94; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
95; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
96; GCN-NEXT:    v_mov_b32_e32 v3, s13
97; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s10, v0
98; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
99; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
100; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
101; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
102; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
103; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
104; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
105; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
106; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
107; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
108; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
109; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
110; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
111; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
112; GCN-NEXT:    v_mov_b32_e32 v5, s11
113; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
114; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
115; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
116; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
117; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
118; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
119; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
120; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
121; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
122; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
123; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
124; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
125; GCN-NEXT:    s_endpgm
126;
127; GCN-IR-LABEL: s_test_urem_i64:
128; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
129; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
130; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
131; GCN-IR-NEXT:    s_mov_b64 s[2:3], 0
132; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
133; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
134; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[0:1], 0
135; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s0
136; GCN-IR-NEXT:    s_or_b64 s[14:15], s[8:9], s[10:11]
137; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s6
138; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
139; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s1
140; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
141; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s7
142; GCN-IR-NEXT:    s_min_u32 s8, s12, s8
143; GCN-IR-NEXT:    s_min_u32 s12, s10, s11
144; GCN-IR-NEXT:    s_sub_u32 s10, s8, s12
145; GCN-IR-NEXT:    s_subb_u32 s11, 0, 0
146; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[16:17], s[10:11], 63
147; GCN-IR-NEXT:    s_mov_b32 s9, 0
148; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[16:17]
149; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[16:17], s[10:11], 63
150; GCN-IR-NEXT:    s_xor_b64 s[18:19], s[14:15], -1
151; GCN-IR-NEXT:    s_and_b64 s[16:17], s[18:19], s[16:17]
152; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
153; GCN-IR-NEXT:    s_cbranch_vccz BB0_5
154; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
155; GCN-IR-NEXT:    s_add_u32 s14, s10, 1
156; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
157; GCN-IR-NEXT:    s_addc_u32 s15, s11, 0
158; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
159; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1]
160; GCN-IR-NEXT:    s_sub_i32 s10, 63, s10
161; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
162; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[6:7], s10
163; GCN-IR-NEXT:    s_cbranch_vccz BB0_4
164; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
165; GCN-IR-NEXT:    s_lshr_b64 s[14:15], s[6:7], s14
166; GCN-IR-NEXT:    s_add_u32 s16, s0, -1
167; GCN-IR-NEXT:    s_addc_u32 s17, s1, -1
168; GCN-IR-NEXT:    s_not_b64 s[2:3], s[8:9]
169; GCN-IR-NEXT:    s_mov_b32 s13, s9
170; GCN-IR-NEXT:    s_add_u32 s8, s2, s12
171; GCN-IR-NEXT:    s_addc_u32 s9, s3, s9
172; GCN-IR-NEXT:    s_mov_b64 s[12:13], 0
173; GCN-IR-NEXT:    s_mov_b32 s3, 0
174; GCN-IR-NEXT:  BB0_3: ; %udiv-do-while
175; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
176; GCN-IR-NEXT:    s_lshl_b64 s[14:15], s[14:15], 1
177; GCN-IR-NEXT:    s_lshr_b32 s2, s11, 31
178; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
179; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[2:3]
180; GCN-IR-NEXT:    s_or_b64 s[10:11], s[12:13], s[10:11]
181; GCN-IR-NEXT:    s_sub_u32 s2, s16, s14
182; GCN-IR-NEXT:    s_subb_u32 s2, s17, s15
183; GCN-IR-NEXT:    s_ashr_i32 s12, s2, 31
184; GCN-IR-NEXT:    s_mov_b32 s13, s12
185; GCN-IR-NEXT:    s_and_b32 s2, s12, 1
186; GCN-IR-NEXT:    s_and_b64 s[18:19], s[12:13], s[0:1]
187; GCN-IR-NEXT:    s_sub_u32 s14, s14, s18
188; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
189; GCN-IR-NEXT:    s_subb_u32 s15, s15, s19
190; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
191; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
192; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
193; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
194; GCN-IR-NEXT:    s_mov_b64 s[12:13], s[2:3]
195; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
196; GCN-IR-NEXT:    s_cbranch_vccz BB0_3
197; GCN-IR-NEXT:  BB0_4: ; %Flow6
198; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[10:11], 1
199; GCN-IR-NEXT:    s_or_b64 s[2:3], s[2:3], s[8:9]
200; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
201; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
202; GCN-IR-NEXT:    s_branch BB0_6
203; GCN-IR-NEXT:  BB0_5:
204; GCN-IR-NEXT:    v_mov_b32_e32 v0, s7
205; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[14:15]
206; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
207; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[14:15]
208; GCN-IR-NEXT:  BB0_6: ; %udiv-end
209; GCN-IR-NEXT:    v_mul_lo_u32 v1, s0, v1
210; GCN-IR-NEXT:    v_mul_hi_u32 v2, s0, v0
211; GCN-IR-NEXT:    v_mul_lo_u32 v3, s1, v0
212; GCN-IR-NEXT:    v_mul_lo_u32 v0, s0, v0
213; GCN-IR-NEXT:    s_mov_b32 s11, 0xf000
214; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
215; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
216; GCN-IR-NEXT:    v_mov_b32_e32 v2, s7
217; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
218; GCN-IR-NEXT:    s_mov_b32 s10, -1
219; GCN-IR-NEXT:    s_mov_b32 s8, s4
220; GCN-IR-NEXT:    s_mov_b32 s9, s5
221; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
222; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
223; GCN-IR-NEXT:    s_endpgm
224  %result = urem i64 %x, %y
225  store i64 %result, i64 addrspace(1)* %out
226  ret void
227}
228
229define i64 @v_test_urem_i64(i64 %x, i64 %y) {
230; GCN-LABEL: v_test_urem_i64:
231; GCN:       ; %bb.0:
232; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
233; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
234; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v3
235; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v2
236; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v3, vcc
237; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
238; GCN-NEXT:    v_rcp_f32_e32 v4, v4
239; GCN-NEXT:    v_mov_b32_e32 v14, 0
240; GCN-NEXT:    v_mov_b32_e32 v13, 0
241; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
242; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
243; GCN-NEXT:    v_trunc_f32_e32 v5, v5
244; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
245; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
246; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
247; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
248; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
249; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
250; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
251; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
252; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
253; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
254; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
255; GCN-NEXT:    v_mul_hi_u32 v10, v4, v8
256; GCN-NEXT:    v_mul_hi_u32 v15, v5, v8
257; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
258; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
259; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
260; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
261; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v10, vcc
262; GCN-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
263; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v10, v9, vcc
264; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v15, v13, vcc
265; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
266; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v10, vcc
267; GCN-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v8
268; GCN-NEXT:    v_addc_u32_e64 v8, vcc, v5, v9, s[4:5]
269; GCN-NEXT:    v_mul_lo_u32 v10, v6, v8
270; GCN-NEXT:    v_mul_hi_u32 v11, v6, v4
271; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
272; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
273; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
274; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
275; GCN-NEXT:    v_mul_lo_u32 v12, v4, v7
276; GCN-NEXT:    v_mul_hi_u32 v15, v4, v6
277; GCN-NEXT:    v_mul_hi_u32 v16, v4, v7
278; GCN-NEXT:    v_mul_hi_u32 v11, v8, v6
279; GCN-NEXT:    v_mul_lo_u32 v6, v8, v6
280; GCN-NEXT:    v_mul_hi_u32 v10, v8, v7
281; GCN-NEXT:    v_add_i32_e32 v12, vcc, v15, v12
282; GCN-NEXT:    v_addc_u32_e32 v15, vcc, v14, v16, vcc
283; GCN-NEXT:    v_mul_lo_u32 v7, v8, v7
284; GCN-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
285; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v15, v11, vcc
286; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v13, vcc
287; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
288; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v14, v8, vcc
289; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
290; GCN-NEXT:    v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
291; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
292; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
293; GCN-NEXT:    v_mul_lo_u32 v6, v0, v5
294; GCN-NEXT:    v_mul_hi_u32 v7, v0, v4
295; GCN-NEXT:    v_mul_hi_u32 v8, v0, v5
296; GCN-NEXT:    v_mul_hi_u32 v9, v1, v5
297; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
298; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
299; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v14, v8, vcc
300; GCN-NEXT:    v_mul_lo_u32 v8, v1, v4
301; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
302; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
303; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v4, vcc
304; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v13, vcc
305; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
306; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v14, v6, vcc
307; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
308; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
309; GCN-NEXT:    v_mul_lo_u32 v7, v3, v4
310; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
311; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
312; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
313; GCN-NEXT:    v_sub_i32_e32 v6, vcc, v1, v5
314; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
315; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v6, v3, vcc
316; GCN-NEXT:    v_sub_i32_e64 v6, s[4:5], v0, v2
317; GCN-NEXT:    v_subbrev_u32_e64 v7, s[6:7], 0, v4, s[4:5]
318; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v7, v3
319; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
320; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v2
321; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
322; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[6:7]
323; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v7, v3
324; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v3, s[4:5]
325; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
326; GCN-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[6:7]
327; GCN-NEXT:    v_sub_i32_e64 v9, s[4:5], v6, v2
328; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
329; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
330; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
331; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
332; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
333; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v8
334; GCN-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
335; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v9, s[4:5]
336; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
337; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v4, s[4:5]
338; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
339; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
340; GCN-NEXT:    s_setpc_b64 s[30:31]
341;
342; GCN-IR-LABEL: v_test_urem_i64:
343; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
344; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
345; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[2:3]
346; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
347; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v2
348; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
349; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
350; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v3
351; GCN-IR-NEXT:    v_min_u32_e32 v8, v4, v5
352; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
353; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
354; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
355; GCN-IR-NEXT:    v_min_u32_e32 v10, v4, v5
356; GCN-IR-NEXT:    v_sub_i32_e32 v5, vcc, v8, v10
357; GCN-IR-NEXT:    v_subb_u32_e64 v6, s[6:7], 0, 0, vcc
358; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[5:6]
359; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
360; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
361; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[5:6]
362; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
363; GCN-IR-NEXT:    v_mov_b32_e32 v11, v9
364; GCN-IR-NEXT:    v_cndmask_b32_e64 v7, v1, 0, s[4:5]
365; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v0, 0, s[4:5]
366; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
367; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
368; GCN-IR-NEXT:    s_cbranch_execz BB1_6
369; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
370; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v5
371; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v6, vcc
372; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v5
373; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[12:13], v[5:6]
374; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[0:1], v4
375; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
376; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
377; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
378; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
379; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
380; GCN-IR-NEXT:    s_cbranch_execz BB1_5
381; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
382; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, -1, v2
383; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, -1, v3, vcc
384; GCN-IR-NEXT:    v_not_b32_e32 v6, v8
385; GCN-IR-NEXT:    v_not_b32_e32 v7, v9
386; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, v6, v10
387; GCN-IR-NEXT:    v_lshr_b64 v[12:13], v[0:1], v12
388; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, v7, v11, vcc
389; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
390; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
391; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
392; GCN-IR-NEXT:  BB1_3: ; %udiv-do-while
393; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
394; GCN-IR-NEXT:    v_lshl_b64 v[12:13], v[12:13], 1
395; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
396; GCN-IR-NEXT:    v_or_b32_e32 v12, v12, v6
397; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
398; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v14, v12
399; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v15, v13, vcc
400; GCN-IR-NEXT:    v_or_b32_e32 v4, v10, v4
401; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v6
402; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v10
403; GCN-IR-NEXT:    v_and_b32_e32 v16, v10, v3
404; GCN-IR-NEXT:    v_and_b32_e32 v17, v10, v2
405; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v8
406; GCN-IR-NEXT:    v_or_b32_e32 v5, v11, v5
407; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v9, vcc
408; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[10:11], v[8:9]
409; GCN-IR-NEXT:    v_mov_b32_e32 v8, v10
410; GCN-IR-NEXT:    v_sub_i32_e64 v12, s[4:5], v12, v17
411; GCN-IR-NEXT:    v_mov_b32_e32 v9, v11
412; GCN-IR-NEXT:    v_mov_b32_e32 v11, v7
413; GCN-IR-NEXT:    v_subb_u32_e64 v13, s[4:5], v13, v16, s[4:5]
414; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
415; GCN-IR-NEXT:    v_mov_b32_e32 v10, v6
416; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
417; GCN-IR-NEXT:    s_cbranch_execnz BB1_3
418; GCN-IR-NEXT:  ; %bb.4: ; %Flow
419; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
420; GCN-IR-NEXT:  BB1_5: ; %Flow3
421; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
422; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
423; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v5
424; GCN-IR-NEXT:    v_or_b32_e32 v4, v6, v4
425; GCN-IR-NEXT:  BB1_6: ; %Flow4
426; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
427; GCN-IR-NEXT:    v_mul_lo_u32 v5, v2, v7
428; GCN-IR-NEXT:    v_mul_hi_u32 v6, v2, v4
429; GCN-IR-NEXT:    v_mul_lo_u32 v3, v3, v4
430; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, v4
431; GCN-IR-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
432; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
433; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
434; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
435; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
436  %result = urem i64 %x, %y
437  ret i64 %result
438}
439
440define amdgpu_kernel void @s_test_urem31_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
441; GCN-LABEL: s_test_urem31_i64:
442; GCN:       ; %bb.0:
443; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
444; GCN-NEXT:    s_waitcnt lgkmcnt(0)
445; GCN-NEXT:    s_lshr_b32 s4, s2, 1
446; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
447; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
448; GCN-NEXT:    s_waitcnt lgkmcnt(0)
449; GCN-NEXT:    s_mov_b32 s2, -1
450; GCN-NEXT:    s_lshr_b32 s5, s3, 1
451; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s5
452; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
453; GCN-NEXT:    s_mov_b32 s3, 0xf000
454; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
455; GCN-NEXT:    v_trunc_f32_e32 v2, v2
456; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
457; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
458; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
459; GCN-NEXT:    v_mov_b32_e32 v1, 0
460; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
461; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
462; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
463; GCN-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
464; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
465; GCN-NEXT:    s_endpgm
466;
467; GCN-IR-LABEL: s_test_urem31_i64:
468; GCN-IR:       ; %bb.0:
469; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xe
470; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
471; GCN-IR-NEXT:    s_lshr_b32 s4, s2, 1
472; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
473; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
474; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
475; GCN-IR-NEXT:    s_mov_b32 s2, -1
476; GCN-IR-NEXT:    s_lshr_b32 s5, s3, 1
477; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s5
478; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
479; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
480; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
481; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
482; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
483; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
484; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
485; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
486; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
487; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
488; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
489; GCN-IR-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
490; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
491; GCN-IR-NEXT:    s_endpgm
492  %1 = lshr i64 %x, 33
493  %2 = lshr i64 %y, 33
494  %result = urem i64 %1, %2
495  store i64 %result, i64 addrspace(1)* %out
496  ret void
497}
498
499define amdgpu_kernel void @s_test_urem31_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
500; GCN-LABEL: s_test_urem31_v2i64:
501; GCN:       ; %bb.0:
502; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
503; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
504; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
505; GCN-NEXT:    s_mov_b32 s7, 0xf000
506; GCN-NEXT:    s_mov_b32 s6, -1
507; GCN-NEXT:    s_waitcnt lgkmcnt(0)
508; GCN-NEXT:    s_lshr_b32 s2, s9, 1
509; GCN-NEXT:    s_lshr_b32 s0, s1, 1
510; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
511; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s2
512; GCN-NEXT:    s_lshr_b32 s3, s3, 1
513; GCN-NEXT:    v_cvt_f32_u32_e32 v4, s3
514; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
515; GCN-NEXT:    s_lshr_b32 s1, s11, 1
516; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s1
517; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
518; GCN-NEXT:    v_trunc_f32_e32 v2, v2
519; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
520; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
521; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v4
522; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
523; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
524; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
525; GCN-NEXT:    v_mul_f32_e32 v2, v3, v2
526; GCN-NEXT:    v_trunc_f32_e32 v2, v2
527; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
528; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
529; GCN-NEXT:    v_mad_f32 v2, -v2, v4, v3
530; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
531; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
532; GCN-NEXT:    v_mul_lo_u32 v2, v2, s3
533; GCN-NEXT:    v_mov_b32_e32 v1, 0
534; GCN-NEXT:    s_brev_b32 s0, -2
535; GCN-NEXT:    v_and_b32_e32 v0, s0, v0
536; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
537; GCN-NEXT:    v_and_b32_e32 v2, s0, v2
538; GCN-NEXT:    v_mov_b32_e32 v3, v1
539; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
540; GCN-NEXT:    s_endpgm
541;
542; GCN-IR-LABEL: s_test_urem31_v2i64:
543; GCN-IR:       ; %bb.0:
544; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
545; GCN-IR-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
546; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
547; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
548; GCN-IR-NEXT:    s_mov_b32 s6, -1
549; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
550; GCN-IR-NEXT:    s_lshr_b32 s2, s9, 1
551; GCN-IR-NEXT:    s_lshr_b32 s0, s1, 1
552; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
553; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s2
554; GCN-IR-NEXT:    s_lshr_b32 s3, s3, 1
555; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v4, s3
556; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
557; GCN-IR-NEXT:    s_lshr_b32 s1, s11, 1
558; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v3, s1
559; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
560; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
561; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
562; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
563; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v4
564; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
565; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
566; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
567; GCN-IR-NEXT:    v_mul_f32_e32 v2, v3, v2
568; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
569; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
570; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
571; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v4, v3
572; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
573; GCN-IR-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
574; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, s3
575; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
576; GCN-IR-NEXT:    s_brev_b32 s0, -2
577; GCN-IR-NEXT:    v_and_b32_e32 v0, s0, v0
578; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
579; GCN-IR-NEXT:    v_and_b32_e32 v2, s0, v2
580; GCN-IR-NEXT:    v_mov_b32_e32 v3, v1
581; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
582; GCN-IR-NEXT:    s_endpgm
583  %1 = lshr <2 x i64> %x, <i64 33, i64 33>
584  %2 = lshr <2 x i64> %y, <i64 33, i64 33>
585  %result = urem <2 x i64> %1, %2
586  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
587  ret void
588}
589
590define amdgpu_kernel void @s_test_urem24_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
591; GCN-LABEL: s_test_urem24_i64:
592; GCN:       ; %bb.0:
593; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
594; GCN-NEXT:    s_waitcnt lgkmcnt(0)
595; GCN-NEXT:    s_lshr_b32 s4, s2, 8
596; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
597; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
598; GCN-NEXT:    s_waitcnt lgkmcnt(0)
599; GCN-NEXT:    s_mov_b32 s2, -1
600; GCN-NEXT:    s_lshr_b32 s5, s3, 8
601; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s5
602; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
603; GCN-NEXT:    s_mov_b32 s3, 0xf000
604; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
605; GCN-NEXT:    v_trunc_f32_e32 v2, v2
606; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
607; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
608; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
609; GCN-NEXT:    v_mov_b32_e32 v1, 0
610; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
611; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
612; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
613; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
614; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
615; GCN-NEXT:    s_endpgm
616;
617; GCN-IR-LABEL: s_test_urem24_i64:
618; GCN-IR:       ; %bb.0:
619; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xe
620; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
621; GCN-IR-NEXT:    s_lshr_b32 s4, s2, 8
622; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
623; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
624; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
625; GCN-IR-NEXT:    s_mov_b32 s2, -1
626; GCN-IR-NEXT:    s_lshr_b32 s5, s3, 8
627; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s5
628; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
629; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
630; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
631; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
632; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
633; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
634; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
635; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
636; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
637; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
638; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
639; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
640; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
641; GCN-IR-NEXT:    s_endpgm
642  %1 = lshr i64 %x, 40
643  %2 = lshr i64 %y, 40
644  %result = urem i64 %1, %2
645  store i64 %result, i64 addrspace(1)* %out
646  ret void
647}
648
649define amdgpu_kernel void @s_test_urem23_64_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
650; GCN-LABEL: s_test_urem23_64_v2i64:
651; GCN:       ; %bb.0:
652; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
653; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
654; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
655; GCN-NEXT:    s_mov_b32 s7, 0xf000
656; GCN-NEXT:    s_mov_b32 s6, -1
657; GCN-NEXT:    s_waitcnt lgkmcnt(0)
658; GCN-NEXT:    s_lshr_b32 s2, s9, 1
659; GCN-NEXT:    s_lshr_b32 s0, s1, 1
660; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
661; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s2
662; GCN-NEXT:    s_lshr_b32 s3, s3, 9
663; GCN-NEXT:    v_cvt_f32_u32_e32 v4, s3
664; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
665; GCN-NEXT:    s_lshr_b32 s1, s11, 9
666; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s1
667; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
668; GCN-NEXT:    v_trunc_f32_e32 v2, v2
669; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
670; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
671; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v4
672; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
673; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
674; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
675; GCN-NEXT:    v_mul_f32_e32 v2, v3, v2
676; GCN-NEXT:    v_trunc_f32_e32 v2, v2
677; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
678; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
679; GCN-NEXT:    v_mad_f32 v2, -v2, v4, v3
680; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
681; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
682; GCN-NEXT:    v_mul_lo_u32 v2, v2, s3
683; GCN-NEXT:    v_mov_b32_e32 v1, 0
684; GCN-NEXT:    s_brev_b32 s0, -2
685; GCN-NEXT:    v_and_b32_e32 v0, s0, v0
686; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
687; GCN-NEXT:    v_and_b32_e32 v2, s0, v2
688; GCN-NEXT:    v_mov_b32_e32 v3, v1
689; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
690; GCN-NEXT:    s_endpgm
691;
692; GCN-IR-LABEL: s_test_urem23_64_v2i64:
693; GCN-IR:       ; %bb.0:
694; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
695; GCN-IR-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
696; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
697; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
698; GCN-IR-NEXT:    s_mov_b32 s6, -1
699; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
700; GCN-IR-NEXT:    s_lshr_b32 s2, s9, 1
701; GCN-IR-NEXT:    s_lshr_b32 s0, s1, 1
702; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
703; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s2
704; GCN-IR-NEXT:    s_lshr_b32 s3, s3, 9
705; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v4, s3
706; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
707; GCN-IR-NEXT:    s_lshr_b32 s1, s11, 9
708; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v3, s1
709; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
710; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
711; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
712; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
713; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v4
714; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
715; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
716; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
717; GCN-IR-NEXT:    v_mul_f32_e32 v2, v3, v2
718; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
719; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
720; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
721; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v4, v3
722; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
723; GCN-IR-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
724; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, s3
725; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
726; GCN-IR-NEXT:    s_brev_b32 s0, -2
727; GCN-IR-NEXT:    v_and_b32_e32 v0, s0, v0
728; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
729; GCN-IR-NEXT:    v_and_b32_e32 v2, s0, v2
730; GCN-IR-NEXT:    v_mov_b32_e32 v3, v1
731; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
732; GCN-IR-NEXT:    s_endpgm
733  %1 = lshr <2 x i64> %x, <i64 33, i64 41>
734  %2 = lshr <2 x i64> %y, <i64 33, i64 41>
735  %result = urem <2 x i64> %1, %2
736  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
737  ret void
738}
739
740define amdgpu_kernel void @s_test_urem_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
741; GCN-LABEL: s_test_urem_k_num_i64:
742; GCN:       ; %bb.0:
743; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
744; GCN-NEXT:    v_mov_b32_e32 v2, 0
745; GCN-NEXT:    s_mov_b32 s11, 0xf000
746; GCN-NEXT:    s_mov_b32 s10, -1
747; GCN-NEXT:    s_waitcnt lgkmcnt(0)
748; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s6
749; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s7
750; GCN-NEXT:    s_sub_u32 s2, 0, s6
751; GCN-NEXT:    s_subb_u32 s3, 0, s7
752; GCN-NEXT:    s_mov_b32 s8, s4
753; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
754; GCN-NEXT:    v_rcp_f32_e32 v0, v0
755; GCN-NEXT:    v_mov_b32_e32 v1, 0
756; GCN-NEXT:    s_mov_b32 s9, s5
757; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
758; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
759; GCN-NEXT:    v_trunc_f32_e32 v3, v3
760; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
761; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
762; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
763; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
764; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
765; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
766; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
767; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
768; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
769; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
770; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
771; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
772; GCN-NEXT:    v_mul_hi_u32 v8, v3, v6
773; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
774; GCN-NEXT:    v_mul_hi_u32 v10, v3, v4
775; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
776; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
777; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
778; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
779; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
780; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
781; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
782; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
783; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
784; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
785; GCN-NEXT:    v_mul_lo_u32 v6, s2, v4
786; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
787; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
788; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
789; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
790; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
791; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
792; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
793; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
794; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
795; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
796; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
797; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
798; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
799; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
800; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
801; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
802; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v8, v1, vcc
803; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
804; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
805; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
806; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v3, v1, s[0:1]
807; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
808; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
809; GCN-NEXT:    v_mul_lo_u32 v3, v1, 24
810; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
811; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
812; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
813; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v2, v1, vcc
814; GCN-NEXT:    v_mul_lo_u32 v1, s7, v0
815; GCN-NEXT:    v_mul_hi_u32 v2, s6, v0
816; GCN-NEXT:    v_mul_lo_u32 v0, s6, v0
817; GCN-NEXT:    v_mov_b32_e32 v3, s7
818; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
819; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
820; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
821; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
822; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s6, v0
823; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
824; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s7, v5
825; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
826; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s6, v4
827; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
828; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
829; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s7, v5
830; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s6, v4
831; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
832; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
833; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
834; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
835; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
836; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
837; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
838; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
839; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
840; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s7, v1
841; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
842; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
843; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
844; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
845; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
846; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
847; GCN-NEXT:    s_endpgm
848;
849; GCN-IR-LABEL: s_test_urem_k_num_i64:
850; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
851; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
852; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
853; GCN-IR-NEXT:    s_flbit_i32_b32 s4, s2
854; GCN-IR-NEXT:    s_flbit_i32_b32 s5, s3
855; GCN-IR-NEXT:    s_add_i32 s4, s4, 32
856; GCN-IR-NEXT:    s_min_u32 s6, s4, s5
857; GCN-IR-NEXT:    s_add_u32 s8, s6, 0xffffffc5
858; GCN-IR-NEXT:    s_addc_u32 s9, 0, -1
859; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
860; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[8:9], 63
861; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0
862; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
863; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[8:9], 63
864; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
865; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
866; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
867; GCN-IR-NEXT:    s_cbranch_vccz BB6_5
868; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
869; GCN-IR-NEXT:    s_add_u32 s10, s8, 1
870; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
871; GCN-IR-NEXT:    s_addc_u32 s11, s9, 0
872; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
873; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
874; GCN-IR-NEXT:    s_sub_i32 s7, 63, s8
875; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
876; GCN-IR-NEXT:    s_lshl_b64 s[8:9], 24, s7
877; GCN-IR-NEXT:    s_cbranch_vccz BB6_4
878; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
879; GCN-IR-NEXT:    s_lshr_b64 s[12:13], 24, s10
880; GCN-IR-NEXT:    s_add_u32 s14, s2, -1
881; GCN-IR-NEXT:    s_addc_u32 s15, s3, -1
882; GCN-IR-NEXT:    s_sub_u32 s6, 58, s6
883; GCN-IR-NEXT:    s_subb_u32 s7, 0, 0
884; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
885; GCN-IR-NEXT:    s_mov_b32 s5, 0
886; GCN-IR-NEXT:  BB6_3: ; %udiv-do-while
887; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
888; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
889; GCN-IR-NEXT:    s_lshr_b32 s4, s9, 31
890; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
891; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[4:5]
892; GCN-IR-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
893; GCN-IR-NEXT:    s_sub_u32 s4, s14, s12
894; GCN-IR-NEXT:    s_subb_u32 s4, s15, s13
895; GCN-IR-NEXT:    s_ashr_i32 s10, s4, 31
896; GCN-IR-NEXT:    s_mov_b32 s11, s10
897; GCN-IR-NEXT:    s_and_b32 s4, s10, 1
898; GCN-IR-NEXT:    s_and_b64 s[16:17], s[10:11], s[2:3]
899; GCN-IR-NEXT:    s_sub_u32 s12, s12, s16
900; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
901; GCN-IR-NEXT:    s_subb_u32 s13, s13, s17
902; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
903; GCN-IR-NEXT:    s_add_u32 s6, s6, 1
904; GCN-IR-NEXT:    s_addc_u32 s7, s7, 0
905; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
906; GCN-IR-NEXT:    s_mov_b64 s[10:11], s[4:5]
907; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
908; GCN-IR-NEXT:    s_cbranch_vccz BB6_3
909; GCN-IR-NEXT:  BB6_4: ; %Flow5
910; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[8:9], 1
911; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], s[6:7]
912; GCN-IR-NEXT:    v_mov_b32_e32 v0, s4
913; GCN-IR-NEXT:    v_mov_b32_e32 v1, s5
914; GCN-IR-NEXT:    s_branch BB6_6
915; GCN-IR-NEXT:  BB6_5:
916; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
917; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[10:11]
918; GCN-IR-NEXT:  BB6_6: ; %udiv-end
919; GCN-IR-NEXT:    v_mul_lo_u32 v1, s2, v1
920; GCN-IR-NEXT:    v_mul_hi_u32 v2, s2, v0
921; GCN-IR-NEXT:    v_mul_lo_u32 v3, s3, v0
922; GCN-IR-NEXT:    v_mul_lo_u32 v0, s2, v0
923; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
924; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
925; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
926; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
927; GCN-IR-NEXT:    s_mov_b32 s6, -1
928; GCN-IR-NEXT:    s_mov_b32 s4, s0
929; GCN-IR-NEXT:    s_mov_b32 s5, s1
930; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
931; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
932; GCN-IR-NEXT:    s_endpgm
933  %result = urem i64 24, %x
934  store i64 %result, i64 addrspace(1)* %out
935  ret void
936}
937
938define amdgpu_kernel void @s_test_urem_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
939; GCN-LABEL: s_test_urem_k_den_i64:
940; GCN:       ; %bb.0:
941; GCN-NEXT:    v_mov_b32_e32 v0, 0x4f800000
942; GCN-NEXT:    v_madak_f32 v0, 0, v0, 0x41c00000
943; GCN-NEXT:    v_rcp_f32_e32 v0, v0
944; GCN-NEXT:    s_movk_i32 s2, 0xffe8
945; GCN-NEXT:    v_mov_b32_e32 v8, 0
946; GCN-NEXT:    v_mov_b32_e32 v7, 0
947; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
948; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
949; GCN-NEXT:    v_trunc_f32_e32 v1, v1
950; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
951; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
952; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
953; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
954; GCN-NEXT:    s_mov_b32 s11, 0xf000
955; GCN-NEXT:    v_mul_hi_u32 v2, v0, s2
956; GCN-NEXT:    v_mul_lo_u32 v3, v1, s2
957; GCN-NEXT:    v_mul_lo_u32 v4, v0, s2
958; GCN-NEXT:    s_mov_b32 s10, -1
959; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
960; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
961; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
962; GCN-NEXT:    v_mul_hi_u32 v6, v0, v4
963; GCN-NEXT:    v_mul_hi_u32 v3, v0, v2
964; GCN-NEXT:    v_mul_hi_u32 v9, v1, v2
965; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
966; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
967; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
968; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
969; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v3, vcc
970; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
971; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
972; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
973; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
974; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
975; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
976; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
977; GCN-NEXT:    v_mul_hi_u32 v4, v0, s2
978; GCN-NEXT:    v_mul_lo_u32 v5, v2, s2
979; GCN-NEXT:    v_mul_lo_u32 v6, v0, s2
980; GCN-NEXT:    s_waitcnt lgkmcnt(0)
981; GCN-NEXT:    s_mov_b32 s8, s4
982; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v0, v4
983; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
984; GCN-NEXT:    v_mul_lo_u32 v5, v0, v4
985; GCN-NEXT:    v_mul_hi_u32 v9, v0, v6
986; GCN-NEXT:    v_mul_hi_u32 v10, v0, v4
987; GCN-NEXT:    v_mul_hi_u32 v11, v2, v4
988; GCN-NEXT:    s_mov_b32 s9, s5
989; GCN-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
990; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v8, v10, vcc
991; GCN-NEXT:    v_mul_lo_u32 v10, v2, v6
992; GCN-NEXT:    v_mul_hi_u32 v6, v2, v6
993; GCN-NEXT:    v_mul_lo_u32 v2, v2, v4
994; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v10
995; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v6, vcc
996; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v11, v7, vcc
997; GCN-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
998; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
999; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1000; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
1001; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1002; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1003; GCN-NEXT:    v_mul_lo_u32 v2, s6, v1
1004; GCN-NEXT:    v_mul_hi_u32 v3, s6, v0
1005; GCN-NEXT:    v_mul_hi_u32 v4, s6, v1
1006; GCN-NEXT:    v_mul_hi_u32 v5, s7, v1
1007; GCN-NEXT:    v_mul_lo_u32 v1, s7, v1
1008; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1009; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
1010; GCN-NEXT:    v_mul_lo_u32 v4, s7, v0
1011; GCN-NEXT:    v_mul_hi_u32 v0, s7, v0
1012; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1013; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
1014; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
1015; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1016; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v8, v2, vcc
1017; GCN-NEXT:    v_mul_lo_u32 v1, v1, 24
1018; GCN-NEXT:    v_mul_hi_u32 v2, v0, 24
1019; GCN-NEXT:    v_mul_lo_u32 v0, v0, 24
1020; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1021; GCN-NEXT:    v_mov_b32_e32 v2, s7
1022; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
1023; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1024; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v0
1025; GCN-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v1, vcc
1026; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v2
1027; GCN-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v3, vcc
1028; GCN-NEXT:    v_cmp_lt_u32_e32 vcc, 23, v2
1029; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1030; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
1031; GCN-NEXT:    v_cndmask_b32_e32 v6, -1, v6, vcc
1032; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
1033; GCN-NEXT:    v_cmp_lt_u32_e64 s[0:1], 23, v0
1034; GCN-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
1035; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
1036; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
1037; GCN-NEXT:    v_cndmask_b32_e64 v5, -1, v5, s[0:1]
1038; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v5
1039; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
1040; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
1041; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
1042; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
1043; GCN-NEXT:    s_endpgm
1044;
1045; GCN-IR-LABEL: s_test_urem_k_den_i64:
1046; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1047; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1048; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1049; GCN-IR-NEXT:    s_flbit_i32_b32 s4, s2
1050; GCN-IR-NEXT:    s_flbit_i32_b32 s5, s3
1051; GCN-IR-NEXT:    s_add_i32 s4, s4, 32
1052; GCN-IR-NEXT:    s_min_u32 s6, s4, s5
1053; GCN-IR-NEXT:    s_sub_u32 s8, 59, s6
1054; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
1055; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
1056; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[8:9], 63
1057; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0
1058; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
1059; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[8:9], 63
1060; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
1061; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
1062; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
1063; GCN-IR-NEXT:    s_cbranch_vccz BB7_5
1064; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1065; GCN-IR-NEXT:    s_add_u32 s10, s8, 1
1066; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1067; GCN-IR-NEXT:    s_addc_u32 s11, s9, 0
1068; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
1069; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1070; GCN-IR-NEXT:    s_sub_i32 s7, 63, s8
1071; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1072; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[2:3], s7
1073; GCN-IR-NEXT:    s_cbranch_vccz BB7_4
1074; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1075; GCN-IR-NEXT:    s_lshr_b64 s[12:13], s[2:3], s10
1076; GCN-IR-NEXT:    s_add_u32 s6, s6, 0xffffffc4
1077; GCN-IR-NEXT:    s_addc_u32 s7, 0, -1
1078; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1079; GCN-IR-NEXT:    s_mov_b32 s5, 0
1080; GCN-IR-NEXT:  BB7_3: ; %udiv-do-while
1081; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1082; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
1083; GCN-IR-NEXT:    s_lshr_b32 s4, s9, 31
1084; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
1085; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[4:5]
1086; GCN-IR-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
1087; GCN-IR-NEXT:    s_sub_u32 s4, 23, s12
1088; GCN-IR-NEXT:    s_subb_u32 s4, 0, s13
1089; GCN-IR-NEXT:    s_ashr_i32 s10, s4, 31
1090; GCN-IR-NEXT:    s_and_b32 s4, s10, 1
1091; GCN-IR-NEXT:    s_and_b32 s10, s10, 24
1092; GCN-IR-NEXT:    s_sub_u32 s12, s12, s10
1093; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1094; GCN-IR-NEXT:    s_subb_u32 s13, s13, 0
1095; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1096; GCN-IR-NEXT:    s_add_u32 s6, s6, 1
1097; GCN-IR-NEXT:    s_addc_u32 s7, s7, 0
1098; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
1099; GCN-IR-NEXT:    s_mov_b64 s[10:11], s[4:5]
1100; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1101; GCN-IR-NEXT:    s_cbranch_vccz BB7_3
1102; GCN-IR-NEXT:  BB7_4: ; %Flow5
1103; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[8:9], 1
1104; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], s[6:7]
1105; GCN-IR-NEXT:    v_mov_b32_e32 v0, s4
1106; GCN-IR-NEXT:    v_mov_b32_e32 v1, s5
1107; GCN-IR-NEXT:    s_branch BB7_6
1108; GCN-IR-NEXT:  BB7_5:
1109; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
1110; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[10:11]
1111; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1112; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[10:11]
1113; GCN-IR-NEXT:  BB7_6: ; %udiv-end
1114; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, 24
1115; GCN-IR-NEXT:    v_mul_hi_u32 v2, v0, 24
1116; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, 24
1117; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1118; GCN-IR-NEXT:    s_mov_b32 s6, -1
1119; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1120; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1121; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1122; GCN-IR-NEXT:    s_mov_b32 s4, s0
1123; GCN-IR-NEXT:    s_mov_b32 s5, s1
1124; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1125; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1126; GCN-IR-NEXT:    s_endpgm
1127  %result = urem i64 %x, 24
1128  store i64 %result, i64 addrspace(1)* %out
1129  ret void
1130}
1131
1132; FIXME: Constant bus violation
1133; define i64 @v_test_urem_k_num_i64(i64 %x) {
1134;   %result = urem i64 24, %x
1135;   ret i64 %result
1136; }
1137
1138define i64 @v_test_urem_pow2_k_num_i64(i64 %x) {
1139; GCN-LABEL: v_test_urem_pow2_k_num_i64:
1140; GCN:       ; %bb.0:
1141; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1142; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1143; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1144; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1145; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1146; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1147; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1148; GCN-NEXT:    v_mov_b32_e32 v12, 0
1149; GCN-NEXT:    v_mov_b32_e32 v11, 0
1150; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1151; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1152; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1153; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1154; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1155; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1156; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1157; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1158; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1159; GCN-NEXT:    v_mul_lo_u32 v9, v4, v2
1160; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1161; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1162; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
1163; GCN-NEXT:    v_mul_hi_u32 v10, v2, v9
1164; GCN-NEXT:    v_mul_hi_u32 v7, v2, v6
1165; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
1166; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1167; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
1168; GCN-NEXT:    v_mul_lo_u32 v10, v3, v9
1169; GCN-NEXT:    v_mul_hi_u32 v9, v3, v9
1170; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v7, vcc
1171; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
1172; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
1173; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v11, vcc
1174; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1175; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v8, vcc
1176; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v6
1177; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v3, v7, s[4:5]
1178; GCN-NEXT:    v_mul_lo_u32 v8, v4, v6
1179; GCN-NEXT:    v_mul_hi_u32 v9, v4, v2
1180; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1181; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1182; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1183; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
1184; GCN-NEXT:    v_mul_lo_u32 v10, v2, v5
1185; GCN-NEXT:    v_mul_hi_u32 v13, v2, v4
1186; GCN-NEXT:    v_mul_hi_u32 v14, v2, v5
1187; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
1188; GCN-NEXT:    v_mul_lo_u32 v4, v6, v4
1189; GCN-NEXT:    v_mul_hi_u32 v8, v6, v5
1190; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v10
1191; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v12, v14, vcc
1192; GCN-NEXT:    v_mul_lo_u32 v5, v6, v5
1193; GCN-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
1194; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v13, v9, vcc
1195; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v11, vcc
1196; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1197; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
1198; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
1199; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
1200; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1201; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
1202; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1203; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
1204; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1205; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
1206; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1207; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1208; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0x8000, v2
1209; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1210; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
1211; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1212; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
1213; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1214; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
1215; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1216; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1
1217; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1218; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1219; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v0
1220; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1221; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1222; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1223; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1224; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1225; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1226; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1227; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1228; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
1229; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1230; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1231; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1232; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1233; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1234; GCN-NEXT:    s_setpc_b64 s[30:31]
1235;
1236; GCN-IR-LABEL: v_test_urem_pow2_k_num_i64:
1237; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1238; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1239; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1240; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1241; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1242; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1243; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 0xffffffd0, v6
1244; GCN-IR-NEXT:    v_addc_u32_e64 v3, s[6:7], 0, -1, vcc
1245; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1246; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[2:3]
1247; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0x8000
1248; GCN-IR-NEXT:    v_mov_b32_e32 v4, s8
1249; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1250; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[2:3]
1251; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1252; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v4, 0, s[4:5]
1253; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1254; GCN-IR-NEXT:    v_mov_b32_e32 v5, v7
1255; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1256; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1257; GCN-IR-NEXT:    s_cbranch_execz BB8_6
1258; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1259; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v2
1260; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v3, vcc
1261; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[8:9], v[2:3]
1262; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v2
1263; GCN-IR-NEXT:    v_lshl_b64 v[2:3], s[8:9], v2
1264; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1265; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1266; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1267; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1268; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1269; GCN-IR-NEXT:    s_cbranch_execz BB8_5
1270; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1271; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, -1, v0
1272; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0x8000
1273; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, -1, v1, vcc
1274; GCN-IR-NEXT:    v_lshr_b64 v[8:9], s[4:5], v8
1275; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, 47, v6
1276; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1277; GCN-IR-NEXT:    v_subb_u32_e32 v7, vcc, 0, v7, vcc
1278; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1279; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1280; GCN-IR-NEXT:  BB8_3: ; %udiv-do-while
1281; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1282; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1283; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1284; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1285; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1286; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, v12, v8
1287; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, v13, v9, vcc
1288; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1289; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1290; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1291; GCN-IR-NEXT:    v_and_b32_e32 v14, v10, v1
1292; GCN-IR-NEXT:    v_and_b32_e32 v15, v10, v0
1293; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v6
1294; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1295; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v7, vcc
1296; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7]
1297; GCN-IR-NEXT:    v_mov_b32_e32 v6, v10
1298; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v15
1299; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1300; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1301; GCN-IR-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v14, s[4:5]
1302; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1303; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1304; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1305; GCN-IR-NEXT:    s_cbranch_execnz BB8_3
1306; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1307; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1308; GCN-IR-NEXT:  BB8_5: ; %Flow3
1309; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1310; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1311; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1312; GCN-IR-NEXT:    v_or_b32_e32 v4, v4, v2
1313; GCN-IR-NEXT:  BB8_6: ; %Flow4
1314; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1315; GCN-IR-NEXT:    v_mul_lo_u32 v2, v0, v5
1316; GCN-IR-NEXT:    v_mul_hi_u32 v3, v0, v4
1317; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v4
1318; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v4
1319; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1320; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1321; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1322; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1323; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1324  %result = urem i64 32768, %x
1325  ret i64 %result
1326}
1327
1328define i64 @v_test_urem_pow2_k_den_i64(i64 %x) {
1329; GCN-LABEL: v_test_urem_pow2_k_den_i64:
1330; GCN:       ; %bb.0:
1331; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1332; GCN-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
1333; GCN-NEXT:    v_mov_b32_e32 v1, 0
1334; GCN-NEXT:    s_setpc_b64 s[30:31]
1335;
1336; GCN-IR-LABEL: v_test_urem_pow2_k_den_i64:
1337; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1338; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1339; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1340; GCN-IR-NEXT:    v_add_i32_e64 v2, s[4:5], 32, v2
1341; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1342; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1343; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 48, v6
1344; GCN-IR-NEXT:    v_subb_u32_e64 v3, s[4:5], 0, 0, s[4:5]
1345; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1346; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[2:3]
1347; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1348; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[2:3]
1349; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1350; GCN-IR-NEXT:    v_cndmask_b32_e64 v5, v1, 0, s[4:5]
1351; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v0, 0, s[4:5]
1352; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1353; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1354; GCN-IR-NEXT:    s_cbranch_execz BB9_6
1355; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1356; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 1, v2
1357; GCN-IR-NEXT:    v_addc_u32_e32 v8, vcc, 0, v3, vcc
1358; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[7:8], v[2:3]
1359; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v2
1360; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[0:1], v2
1361; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1362; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1363; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1364; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1365; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1366; GCN-IR-NEXT:    s_cbranch_execz BB9_5
1367; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1368; GCN-IR-NEXT:    v_lshr_b64 v[8:9], v[0:1], v7
1369; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 0xffffffcf, v6
1370; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1371; GCN-IR-NEXT:    v_addc_u32_e64 v7, s[4:5], 0, -1, vcc
1372; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1373; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1374; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1375; GCN-IR-NEXT:  BB9_3: ; %udiv-do-while
1376; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1377; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1378; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1379; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1380; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1381; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, s12, v8
1382; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, 0, v9, vcc
1383; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1384; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1385; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1386; GCN-IR-NEXT:    v_and_b32_e32 v13, 0x8000, v10
1387; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v6
1388; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1389; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v7, vcc
1390; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7]
1391; GCN-IR-NEXT:    v_mov_b32_e32 v6, v10
1392; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1393; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v13
1394; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1395; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1396; GCN-IR-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v12, s[4:5]
1397; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1398; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1399; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1400; GCN-IR-NEXT:    s_cbranch_execnz BB9_3
1401; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1402; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1403; GCN-IR-NEXT:  BB9_5: ; %Flow3
1404; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1405; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1406; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1407; GCN-IR-NEXT:    v_or_b32_e32 v4, v4, v2
1408; GCN-IR-NEXT:  BB9_6: ; %Flow4
1409; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1410; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[4:5], 15
1411; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1412; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1413; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1414  %result = urem i64 %x, 32768
1415  ret i64 %result
1416}
1417
1418define amdgpu_kernel void @s_test_urem24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1419; GCN-LABEL: s_test_urem24_k_num_i64:
1420; GCN:       ; %bb.0:
1421; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1422; GCN-NEXT:    s_mov_b32 s5, 0x41c00000
1423; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1424; GCN-NEXT:    s_mov_b32 s2, -1
1425; GCN-NEXT:    s_lshr_b32 s4, s3, 8
1426; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
1427; GCN-NEXT:    s_mov_b32 s3, 0xf000
1428; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1429; GCN-NEXT:    v_mul_f32_e32 v1, s5, v1
1430; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1431; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1432; GCN-NEXT:    v_mad_f32 v1, -v1, v0, s5
1433; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1434; GCN-NEXT:    v_mov_b32_e32 v1, 0
1435; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1436; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
1437; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1438; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1439; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1440; GCN-NEXT:    s_endpgm
1441;
1442; GCN-IR-LABEL: s_test_urem24_k_num_i64:
1443; GCN-IR:       ; %bb.0:
1444; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1445; GCN-IR-NEXT:    s_mov_b32 s5, 0x41c00000
1446; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1447; GCN-IR-NEXT:    s_mov_b32 s2, -1
1448; GCN-IR-NEXT:    s_lshr_b32 s4, s3, 8
1449; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
1450; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1451; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1452; GCN-IR-NEXT:    v_mul_f32_e32 v1, s5, v1
1453; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1454; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1455; GCN-IR-NEXT:    v_mad_f32 v1, -v1, v0, s5
1456; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1457; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1458; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1459; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
1460; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1461; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1462; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1463; GCN-IR-NEXT:    s_endpgm
1464  %x.shr = lshr i64 %x, 40
1465  %result = urem i64 24, %x.shr
1466  store i64 %result, i64 addrspace(1)* %out
1467  ret void
1468}
1469
1470define amdgpu_kernel void @s_test_urem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1471; GCN-LABEL: s_test_urem24_k_den_i64:
1472; GCN:       ; %bb.0:
1473; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1474; GCN-NEXT:    s_mov_b32 s4, 0x46b6fe00
1475; GCN-NEXT:    s_mov_b32 s7, 0xf000
1476; GCN-NEXT:    s_mov_b32 s6, -1
1477; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1478; GCN-NEXT:    s_lshr_b32 s2, s3, 8
1479; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
1480; GCN-NEXT:    s_movk_i32 s3, 0x5b7f
1481; GCN-NEXT:    s_mov_b32 s5, s1
1482; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1483; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1484; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1485; GCN-NEXT:    v_mad_f32 v0, -v1, s4, v0
1486; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
1487; GCN-NEXT:    s_mov_b32 s4, s0
1488; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1489; GCN-NEXT:    v_mul_lo_u32 v0, v0, s3
1490; GCN-NEXT:    v_mov_b32_e32 v1, 0
1491; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1492; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1493; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1494; GCN-NEXT:    s_endpgm
1495;
1496; GCN-IR-LABEL: s_test_urem24_k_den_i64:
1497; GCN-IR:       ; %bb.0:
1498; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1499; GCN-IR-NEXT:    s_mov_b32 s4, 0x46b6fe00
1500; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1501; GCN-IR-NEXT:    s_mov_b32 s6, -1
1502; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1503; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 8
1504; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
1505; GCN-IR-NEXT:    s_movk_i32 s3, 0x5b7f
1506; GCN-IR-NEXT:    s_mov_b32 s5, s1
1507; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1508; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1509; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1510; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s4, v0
1511; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
1512; GCN-IR-NEXT:    s_mov_b32 s4, s0
1513; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1514; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s3
1515; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1516; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1517; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1518; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1519; GCN-IR-NEXT:    s_endpgm
1520  %x.shr = lshr i64 %x, 40
1521  %result = urem i64 %x.shr, 23423
1522  store i64 %result, i64 addrspace(1)* %out
1523  ret void
1524}
1525
1526define i64 @v_test_urem24_k_num_i64(i64 %x) {
1527; GCN-LABEL: v_test_urem24_k_num_i64:
1528; GCN:       ; %bb.0:
1529; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1530; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1531; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v0
1532; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
1533; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1534; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
1535; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1536; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
1537; GCN-NEXT:    v_mad_f32 v2, -v2, v1, s4
1538; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1539; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1540; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
1541; GCN-NEXT:    v_mov_b32_e32 v1, 0
1542; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1543; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1544; GCN-NEXT:    s_setpc_b64 s[30:31]
1545;
1546; GCN-IR-LABEL: v_test_urem24_k_num_i64:
1547; GCN-IR:       ; %bb.0:
1548; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1549; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1550; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, v0
1551; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
1552; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1553; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
1554; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1555; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
1556; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v1, s4
1557; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1558; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1559; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
1560; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1561; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1562; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1563; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1564  %x.shr = lshr i64 %x, 40
1565  %result = urem i64 24, %x.shr
1566  ret i64 %result
1567}
1568
1569define i64 @v_test_urem24_pow2_k_num_i64(i64 %x) {
1570; GCN-LABEL: v_test_urem24_pow2_k_num_i64:
1571; GCN:       ; %bb.0:
1572; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1573; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1574; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v0
1575; GCN-NEXT:    s_mov_b32 s4, 0x47000000
1576; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1577; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
1578; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1579; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
1580; GCN-NEXT:    v_mad_f32 v2, -v2, v1, s4
1581; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1582; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1583; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
1584; GCN-NEXT:    v_mov_b32_e32 v1, 0
1585; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1586; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1587; GCN-NEXT:    s_setpc_b64 s[30:31]
1588;
1589; GCN-IR-LABEL: v_test_urem24_pow2_k_num_i64:
1590; GCN-IR:       ; %bb.0:
1591; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1592; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1593; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, v0
1594; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
1595; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1596; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
1597; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1598; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
1599; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v1, s4
1600; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1601; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1602; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
1603; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1604; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1605; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1606; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1607  %x.shr = lshr i64 %x, 40
1608  %result = urem i64 32768, %x.shr
1609  ret i64 %result
1610}
1611
1612define i64 @v_test_urem24_pow2_k_den_i64(i64 %x) {
1613; GCN-LABEL: v_test_urem24_pow2_k_den_i64:
1614; GCN:       ; %bb.0:
1615; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1616; GCN-NEXT:    v_bfe_u32 v0, v1, 8, 15
1617; GCN-NEXT:    v_mov_b32_e32 v1, 0
1618; GCN-NEXT:    s_setpc_b64 s[30:31]
1619;
1620; GCN-IR-LABEL: v_test_urem24_pow2_k_den_i64:
1621; GCN-IR:       ; %bb.0:
1622; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1623; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1624; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, v0
1625; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
1626; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38000000, v1
1627; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1628; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
1629; GCN-IR-NEXT:    v_mad_f32 v1, -v2, s4, v1
1630; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
1631; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1632; GCN-IR-NEXT:    v_lshlrev_b32_e32 v1, 15, v1
1633; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
1634; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1635; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1636; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1637  %x.shr = lshr i64 %x, 40
1638  %result = urem i64 %x.shr, 32768
1639  ret i64 %result
1640}
1641