1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3
4define amdgpu_kernel void @s_test_urem_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
5; GCN-LABEL: s_test_urem_i64:
6; GCN:       ; %bb.0:
7; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
8; GCN-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
9; GCN-NEXT:    s_mov_b32 s7, 0xf000
10; GCN-NEXT:    s_mov_b32 s6, -1
11; GCN-NEXT:    v_mov_b32_e32 v0, 0
12; GCN-NEXT:    v_mov_b32_e32 v1, 0
13; GCN-NEXT:    s_waitcnt lgkmcnt(0)
14; GCN-NEXT:    s_mov_b32 s4, s8
15; GCN-NEXT:    s_mov_b32 s5, s9
16; GCN-NEXT:    v_cvt_f32_u32_e32 v2, s2
17; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s3
18; GCN-NEXT:    s_sub_u32 s8, 0, s2
19; GCN-NEXT:    v_mov_b32_e32 v4, s3
20; GCN-NEXT:    v_mov_b32_e32 v5, s11
21; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
22; GCN-NEXT:    s_subb_u32 s9, 0, s3
23; GCN-NEXT:    v_rcp_f32_e32 v2, v2
24; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
25; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
26; GCN-NEXT:    v_trunc_f32_e32 v3, v3
27; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
28; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
29; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
30; GCN-NEXT:    v_mul_lo_u32 v6, s8, v3
31; GCN-NEXT:    v_mul_lo_u32 v7, s9, v2
32; GCN-NEXT:    v_mul_hi_u32 v8, s8, v2
33; GCN-NEXT:    v_mul_lo_u32 v9, s8, v2
34; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
35; GCN-NEXT:    v_mul_hi_u32 v8, v2, v9
36; GCN-NEXT:    v_mul_hi_u32 v10, v3, v9
37; GCN-NEXT:    v_mul_lo_u32 v9, v3, v9
38; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
39; GCN-NEXT:    v_mul_hi_u32 v7, v2, v6
40; GCN-NEXT:    v_mul_lo_u32 v11, v2, v6
41; GCN-NEXT:    v_mul_hi_u32 v12, v3, v6
42; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
43; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
44; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v1, v7, vcc
45; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
46; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v10, vcc
47; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v0, vcc
48; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
49; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v1, v8, vcc
50; GCN-NEXT:    v_add_i32_e64 v2, s[0:1], v2, v6
51; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v3, v7, s[0:1]
52; GCN-NEXT:    v_mul_hi_u32 v8, s8, v2
53; GCN-NEXT:    v_mul_lo_u32 v9, s9, v2
54; GCN-NEXT:    v_mul_lo_u32 v10, s8, v2
55; GCN-NEXT:    v_mul_lo_u32 v11, s8, v6
56; GCN-NEXT:    v_mul_hi_u32 v12, v6, v10
57; GCN-NEXT:    v_mul_lo_u32 v13, v6, v10
58; GCN-NEXT:    v_mul_hi_u32 v10, v2, v10
59; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
60; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
61; GCN-NEXT:    v_mul_hi_u32 v9, v6, v8
62; GCN-NEXT:    v_mul_hi_u32 v11, v2, v8
63; GCN-NEXT:    v_mul_lo_u32 v14, v2, v8
64; GCN-NEXT:    v_mul_lo_u32 v6, v6, v8
65; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v14
66; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v1, v11, vcc
67; GCN-NEXT:    v_add_i32_e32 v8, vcc, v13, v8
68; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v12, vcc
69; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v9, v0, vcc
70; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
71; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
72; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v1, v9, vcc
73; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v7, s[0:1]
74; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
75; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
76; GCN-NEXT:    v_mul_hi_u32 v6, s10, v2
77; GCN-NEXT:    v_mul_hi_u32 v7, s11, v2
78; GCN-NEXT:    v_mul_lo_u32 v2, s11, v2
79; GCN-NEXT:    v_mul_hi_u32 v8, s10, v3
80; GCN-NEXT:    v_mul_lo_u32 v9, s10, v3
81; GCN-NEXT:    v_mul_hi_u32 v10, s11, v3
82; GCN-NEXT:    v_mul_lo_u32 v3, s11, v3
83; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
84; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v1, v8, vcc
85; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
86; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v8, v7, vcc
87; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v10, v0, vcc
88; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
89; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v1, v0, vcc
90; GCN-NEXT:    v_mul_hi_u32 v1, s2, v2
91; GCN-NEXT:    v_mul_lo_u32 v3, s3, v2
92; GCN-NEXT:    v_mul_lo_u32 v2, s2, v2
93; GCN-NEXT:    v_mul_lo_u32 v0, s2, v0
94; GCN-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
95; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
96; GCN-NEXT:    v_sub_i32_e32 v1, vcc, s11, v0
97; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s10, v2
98; GCN-NEXT:    v_subb_u32_e64 v1, s[0:1], v1, v4, vcc
99; GCN-NEXT:    v_subb_u32_e32 v0, vcc, v5, v0, vcc
100; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v2
101; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
102; GCN-NEXT:    v_subrev_i32_e32 v5, vcc, s2, v2
103; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v1, v4, vcc
104; GCN-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
105; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v5
106; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
107; GCN-NEXT:    v_subrev_i32_e32 v7, vcc, s2, v5
108; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v0
109; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[0:1]
110; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v1
111; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[0:1]
112; GCN-NEXT:    v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
113; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v0
114; GCN-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
115; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v1
116; GCN-NEXT:    v_cndmask_b32_e32 v6, v9, v6, vcc
117; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
118; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
119; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v3
120; GCN-NEXT:    v_cndmask_b32_e64 v1, v0, v1, s[0:1]
121; GCN-NEXT:    v_cndmask_b32_e32 v0, v5, v7, vcc
122; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v0, s[0:1]
123; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
124; GCN-NEXT:    s_endpgm
125  %result = urem i64 %x, %y
126  store i64 %result, i64 addrspace(1)* %out
127  ret void
128}
129
130define i64 @v_test_urem_i64(i64 %x, i64 %y) {
131; GCN-LABEL: v_test_urem_i64:
132; GCN:       ; %bb.0:
133; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
134; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
135; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v3
136; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v2
137; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v3, vcc
138; GCN-NEXT:    v_mov_b32_e32 v8, 0
139; GCN-NEXT:    v_mov_b32_e32 v9, 0
140; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
141; GCN-NEXT:    v_rcp_f32_e32 v4, v4
142; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
143; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
144; GCN-NEXT:    v_trunc_f32_e32 v5, v5
145; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
146; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
147; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
148; GCN-NEXT:    v_mul_lo_u32 v10, v6, v5
149; GCN-NEXT:    v_mul_lo_u32 v11, v7, v4
150; GCN-NEXT:    v_mul_hi_u32 v12, v6, v4
151; GCN-NEXT:    v_mul_lo_u32 v13, v6, v4
152; GCN-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
153; GCN-NEXT:    v_mul_hi_u32 v12, v4, v13
154; GCN-NEXT:    v_mul_hi_u32 v14, v5, v13
155; GCN-NEXT:    v_mul_lo_u32 v13, v5, v13
156; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
157; GCN-NEXT:    v_mul_hi_u32 v11, v4, v10
158; GCN-NEXT:    v_mul_lo_u32 v15, v4, v10
159; GCN-NEXT:    v_mul_hi_u32 v16, v5, v10
160; GCN-NEXT:    v_mul_lo_u32 v10, v5, v10
161; GCN-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
162; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v9, v11, vcc
163; GCN-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
164; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v11, v14, vcc
165; GCN-NEXT:    v_addc_u32_e32 v12, vcc, v16, v8, vcc
166; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
167; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v9, v12, vcc
168; GCN-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v10
169; GCN-NEXT:    v_addc_u32_e64 v10, vcc, v5, v11, s[4:5]
170; GCN-NEXT:    v_mul_hi_u32 v12, v6, v4
171; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
172; GCN-NEXT:    v_mul_lo_u32 v13, v6, v4
173; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v11
174; GCN-NEXT:    v_mul_lo_u32 v6, v6, v10
175; GCN-NEXT:    v_mul_hi_u32 v11, v10, v13
176; GCN-NEXT:    v_mul_lo_u32 v14, v10, v13
177; GCN-NEXT:    v_mul_hi_u32 v13, v4, v13
178; GCN-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
179; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
180; GCN-NEXT:    v_mul_hi_u32 v7, v10, v6
181; GCN-NEXT:    v_mul_hi_u32 v12, v4, v6
182; GCN-NEXT:    v_mul_lo_u32 v15, v4, v6
183; GCN-NEXT:    v_mul_lo_u32 v6, v10, v6
184; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v15
185; GCN-NEXT:    v_addc_u32_e32 v12, vcc, v9, v12, vcc
186; GCN-NEXT:    v_add_i32_e32 v10, vcc, v14, v10
187; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v12, v11, vcc
188; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v8, vcc
189; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
190; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v7, vcc
191; GCN-NEXT:    v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
192; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
193; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
194; GCN-NEXT:    v_mul_hi_u32 v6, v0, v4
195; GCN-NEXT:    v_mul_hi_u32 v7, v1, v4
196; GCN-NEXT:    v_mul_lo_u32 v4, v1, v4
197; GCN-NEXT:    v_mul_hi_u32 v10, v0, v5
198; GCN-NEXT:    v_mul_lo_u32 v11, v0, v5
199; GCN-NEXT:    v_mul_hi_u32 v12, v1, v5
200; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
201; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
202; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v9, v10, vcc
203; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
204; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v10, v7, vcc
205; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v12, v8, vcc
206; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
207; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v6, vcc
208; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
209; GCN-NEXT:    v_mul_lo_u32 v7, v3, v4
210; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
211; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
212; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
213; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
214; GCN-NEXT:    v_sub_i32_e32 v6, vcc, v1, v5
215; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
216; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v6, v3, vcc
217; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
218; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
219; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
220; GCN-NEXT:    v_sub_i32_e32 v6, vcc, v0, v2
221; GCN-NEXT:    v_subb_u32_e64 v7, s[4:5], v4, v3, vcc
222; GCN-NEXT:    v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
223; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v6, v2
224; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
225; GCN-NEXT:    v_sub_i32_e32 v2, vcc, v6, v2
226; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v1, v3
227; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
228; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v4, v3
229; GCN-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
230; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v1, v3
231; GCN-NEXT:    v_cndmask_b32_e64 v5, v9, v5, s[4:5]
232; GCN-NEXT:    v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
233; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v4, v3
234; GCN-NEXT:    v_cndmask_b32_e32 v3, v10, v8, vcc
235; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
236; GCN-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
237; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v5
238; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[4:5]
239; GCN-NEXT:    v_cndmask_b32_e32 v2, v4, v7, vcc
240; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v2, s[4:5]
241; GCN-NEXT:    s_setpc_b64 s[30:31]
242  %result = urem i64 %x, %y
243  ret i64 %result
244}
245
246define amdgpu_kernel void @s_test_urem31_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
247; GCN-LABEL: s_test_urem31_i64:
248; GCN:       ; %bb.0:
249; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
250; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
251; GCN-NEXT:    s_mov_b32 s11, 0xf000
252; GCN-NEXT:    s_mov_b32 s10, -1
253; GCN-NEXT:    s_waitcnt lgkmcnt(0)
254; GCN-NEXT:    s_mov_b32 s8, s4
255; GCN-NEXT:    s_mov_b32 s9, s5
256; GCN-NEXT:    s_lshr_b32 s3, s7, 1
257; GCN-NEXT:    s_lshr_b32 s4, s2, 1
258; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
259; GCN-NEXT:    v_rcp_iflag_f32_e32 v0, v0
260; GCN-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0
261; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
262; GCN-NEXT:    v_mul_hi_u32 v1, v0, s4
263; GCN-NEXT:    v_mul_lo_u32 v2, v0, s4
264; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 0, v2
265; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
266; GCN-NEXT:    v_cndmask_b32_e64 v1, v2, v3, s[0:1]
267; GCN-NEXT:    v_mul_hi_u32 v1, v1, v0
268; GCN-NEXT:    v_add_i32_e32 v2, vcc, v1, v0
269; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, v1, v0
270; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
271; GCN-NEXT:    v_mul_hi_u32 v0, v0, s3
272; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
273; GCN-NEXT:    v_sub_i32_e32 v1, vcc, s3, v0
274; GCN-NEXT:    v_add_i32_e32 v2, vcc, s4, v1
275; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], s3, v0
276; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s4, v1
277; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s4, v1
278; GCN-NEXT:    s_and_b64 vcc, s[2:3], s[0:1]
279; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
280; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v0, s[0:1]
281; GCN-NEXT:    v_mov_b32_e32 v1, 0
282; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
283; GCN-NEXT:    s_endpgm
284  %1 = lshr i64 %x, 33
285  %2 = lshr i64 %y, 33
286  %result = urem i64 %1, %2
287  store i64 %result, i64 addrspace(1)* %out
288  ret void
289}
290
291define amdgpu_kernel void @s_test_urem31_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
292; GCN-LABEL: s_test_urem31_v2i64:
293; GCN:       ; %bb.0:
294; GCN-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x9
295; GCN-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0xd
296; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x11
297; GCN-NEXT:    s_mov_b32 s11, 0xf000
298; GCN-NEXT:    s_mov_b32 s10, -1
299; GCN-NEXT:    v_mov_b32_e32 v1, 0
300; GCN-NEXT:    s_waitcnt lgkmcnt(0)
301; GCN-NEXT:    s_lshr_b32 s4, s13, 1
302; GCN-NEXT:    s_lshr_b32 s6, s15, 1
303; GCN-NEXT:    s_lshr_b32 s12, s5, 1
304; GCN-NEXT:    s_lshr_b32 s5, s7, 1
305; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s5
306; GCN-NEXT:    v_cvt_f32_u32_e32 v2, s12
307; GCN-NEXT:    v_rcp_iflag_f32_e32 v0, v0
308; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v2
309; GCN-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0
310; GCN-NEXT:    v_mul_f32_e32 v2, 0x4f800000, v2
311; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
312; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
313; GCN-NEXT:    v_mul_hi_u32 v3, v0, s5
314; GCN-NEXT:    v_mul_lo_u32 v4, v0, s5
315; GCN-NEXT:    v_mul_hi_u32 v5, v2, s12
316; GCN-NEXT:    v_mul_lo_u32 v6, v2, s12
317; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 0, v4
318; GCN-NEXT:    v_sub_i32_e32 v8, vcc, 0, v6
319; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v3
320; GCN-NEXT:    v_cndmask_b32_e64 v3, v4, v7, s[0:1]
321; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], 0, v5
322; GCN-NEXT:    v_cndmask_b32_e64 v4, v6, v8, s[2:3]
323; GCN-NEXT:    v_mul_hi_u32 v3, v3, v0
324; GCN-NEXT:    v_mul_hi_u32 v4, v4, v2
325; GCN-NEXT:    v_add_i32_e32 v5, vcc, v3, v0
326; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, v3, v0
327; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v2
328; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, v4, v2
329; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v5, s[0:1]
330; GCN-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[2:3]
331; GCN-NEXT:    v_mul_hi_u32 v0, v0, s6
332; GCN-NEXT:    v_mul_hi_u32 v2, v2, s4
333; GCN-NEXT:    v_mul_lo_u32 v0, v0, s5
334; GCN-NEXT:    v_mul_lo_u32 v2, v2, s12
335; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s6, v0
336; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s4, v2
337; GCN-NEXT:    v_add_i32_e32 v5, vcc, s5, v3
338; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], s6, v0
339; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s5, v3
340; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s5, v3
341; GCN-NEXT:    v_add_i32_e32 v6, vcc, s12, v4
342; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], s4, v2
343; GCN-NEXT:    v_cmp_le_u32_e64 s[6:7], s12, v4
344; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, s12, v4
345; GCN-NEXT:    s_and_b64 vcc, s[2:3], s[0:1]
346; GCN-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
347; GCN-NEXT:    s_and_b64 vcc, s[6:7], s[4:5]
348; GCN-NEXT:    v_cndmask_b32_e32 v3, v4, v2, vcc
349; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v0, s[0:1]
350; GCN-NEXT:    v_cndmask_b32_e64 v0, v6, v3, s[4:5]
351; GCN-NEXT:    v_mov_b32_e32 v3, v1
352; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
353; GCN-NEXT:    s_endpgm
354  %1 = lshr <2 x i64> %x, <i64 33, i64 33>
355  %2 = lshr <2 x i64> %y, <i64 33, i64 33>
356  %result = urem <2 x i64> %1, %2
357  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
358  ret void
359}
360
361define amdgpu_kernel void @s_test_urem24_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
362; GCN-LABEL: s_test_urem24_i64:
363; GCN:       ; %bb.0:
364; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
365; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
366; GCN-NEXT:    s_mov_b32 s11, 0xf000
367; GCN-NEXT:    s_mov_b32 s10, -1
368; GCN-NEXT:    s_waitcnt lgkmcnt(0)
369; GCN-NEXT:    s_mov_b32 s8, s4
370; GCN-NEXT:    s_mov_b32 s9, s5
371; GCN-NEXT:    s_lshr_b32 s3, s7, 8
372; GCN-NEXT:    s_lshr_b32 s4, s2, 8
373; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
374; GCN-NEXT:    v_rcp_iflag_f32_e32 v0, v0
375; GCN-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0
376; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
377; GCN-NEXT:    v_mul_hi_u32 v1, v0, s4
378; GCN-NEXT:    v_mul_lo_u32 v2, v0, s4
379; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 0, v2
380; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
381; GCN-NEXT:    v_cndmask_b32_e64 v1, v2, v3, s[0:1]
382; GCN-NEXT:    v_mul_hi_u32 v1, v1, v0
383; GCN-NEXT:    v_add_i32_e32 v2, vcc, v1, v0
384; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, v1, v0
385; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
386; GCN-NEXT:    v_mul_hi_u32 v0, v0, s3
387; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
388; GCN-NEXT:    v_sub_i32_e32 v1, vcc, s3, v0
389; GCN-NEXT:    v_add_i32_e32 v2, vcc, s4, v1
390; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], s3, v0
391; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s4, v1
392; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s4, v1
393; GCN-NEXT:    s_and_b64 vcc, s[2:3], s[0:1]
394; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
395; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v0, s[0:1]
396; GCN-NEXT:    v_mov_b32_e32 v1, 0
397; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
398; GCN-NEXT:    s_endpgm
399  %1 = lshr i64 %x, 40
400  %2 = lshr i64 %y, 40
401  %result = urem i64 %1, %2
402  store i64 %result, i64 addrspace(1)* %out
403  ret void
404}
405
406define amdgpu_kernel void @s_test_urem23_64_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
407; GCN-LABEL: s_test_urem23_64_v2i64:
408; GCN:       ; %bb.0:
409; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
410; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
411; GCN-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0x11
412; GCN-NEXT:    s_mov_b32 s7, 0xf000
413; GCN-NEXT:    s_mov_b32 s6, -1
414; GCN-NEXT:    v_mov_b32_e32 v1, 0
415; GCN-NEXT:    s_waitcnt lgkmcnt(0)
416; GCN-NEXT:    s_lshr_b32 s2, s11, 9
417; GCN-NEXT:    s_lshr_b32 s3, s9, 1
418; GCN-NEXT:    s_lshr_b32 s8, s15, 9
419; GCN-NEXT:    s_lshr_b32 s9, s13, 1
420; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s9
421; GCN-NEXT:    v_cvt_f32_u32_e32 v2, s2
422; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s8
423; GCN-NEXT:    v_rcp_iflag_f32_e32 v0, v0
424; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v3
425; GCN-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0
426; GCN-NEXT:    v_mul_f32_e32 v4, v2, v4
427; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
428; GCN-NEXT:    v_trunc_f32_e32 v4, v4
429; GCN-NEXT:    v_mul_hi_u32 v5, v0, s9
430; GCN-NEXT:    v_mul_lo_u32 v6, v0, s9
431; GCN-NEXT:    v_mad_f32 v2, -v4, v3, v2
432; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
433; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 0, v6
434; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v3|
435; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v4, vcc
436; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v5
437; GCN-NEXT:    v_cndmask_b32_e64 v3, v6, v7, s[0:1]
438; GCN-NEXT:    v_mul_lo_u32 v2, v2, s8
439; GCN-NEXT:    v_mul_hi_u32 v3, v3, v0
440; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s2, v2
441; GCN-NEXT:    v_add_i32_e32 v4, vcc, v3, v0
442; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, v3, v0
443; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
444; GCN-NEXT:    v_mul_hi_u32 v0, v0, s3
445; GCN-NEXT:    v_mul_lo_u32 v0, v0, s9
446; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s3, v0
447; GCN-NEXT:    v_add_i32_e32 v4, vcc, s9, v3
448; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], s3, v0
449; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v3
450; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s9, v3
451; GCN-NEXT:    s_and_b64 vcc, s[2:3], s[0:1]
452; GCN-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
453; GCN-NEXT:    v_cndmask_b32_e64 v0, v4, v0, s[0:1]
454; GCN-NEXT:    v_and_b32_e32 v2, 0x7fffff, v2
455; GCN-NEXT:    v_mov_b32_e32 v3, v1
456; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
457; GCN-NEXT:    s_endpgm
458  %1 = lshr <2 x i64> %x, <i64 33, i64 41>
459  %2 = lshr <2 x i64> %y, <i64 33, i64 41>
460  %result = urem <2 x i64> %1, %2
461  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
462  ret void
463}
464
465define amdgpu_kernel void @s_test_urem_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
466; GCN-LABEL: s_test_urem_k_num_i64:
467; GCN:       ; %bb.0:
468; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
469; GCN-NEXT:    s_mov_b32 s7, 0xf000
470; GCN-NEXT:    s_mov_b32 s6, -1
471; GCN-NEXT:    v_mov_b32_e32 v0, 0
472; GCN-NEXT:    v_mov_b32_e32 v1, 0
473; GCN-NEXT:    s_waitcnt lgkmcnt(0)
474; GCN-NEXT:    s_mov_b32 s4, s0
475; GCN-NEXT:    s_mov_b32 s5, s1
476; GCN-NEXT:    v_cvt_f32_u32_e32 v2, s2
477; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s3
478; GCN-NEXT:    s_sub_u32 s8, 0, s2
479; GCN-NEXT:    v_mov_b32_e32 v4, s3
480; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
481; GCN-NEXT:    s_subb_u32 s9, 0, s3
482; GCN-NEXT:    v_rcp_f32_e32 v2, v2
483; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
484; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
485; GCN-NEXT:    v_trunc_f32_e32 v3, v3
486; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
487; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
488; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
489; GCN-NEXT:    v_mul_lo_u32 v5, s8, v3
490; GCN-NEXT:    v_mul_lo_u32 v6, s9, v2
491; GCN-NEXT:    v_mul_hi_u32 v7, s8, v2
492; GCN-NEXT:    v_mul_lo_u32 v8, s8, v2
493; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
494; GCN-NEXT:    v_mul_hi_u32 v7, v2, v8
495; GCN-NEXT:    v_mul_hi_u32 v9, v3, v8
496; GCN-NEXT:    v_mul_lo_u32 v8, v3, v8
497; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
498; GCN-NEXT:    v_mul_hi_u32 v6, v2, v5
499; GCN-NEXT:    v_mul_lo_u32 v10, v2, v5
500; GCN-NEXT:    v_mul_hi_u32 v11, v3, v5
501; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
502; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
503; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v1, v6, vcc
504; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
505; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v9, vcc
506; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v0, vcc
507; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
508; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v1, v7, vcc
509; GCN-NEXT:    v_add_i32_e64 v2, s[0:1], v2, v5
510; GCN-NEXT:    v_addc_u32_e64 v5, vcc, v3, v6, s[0:1]
511; GCN-NEXT:    v_mul_hi_u32 v7, s8, v2
512; GCN-NEXT:    v_mul_lo_u32 v8, s9, v2
513; GCN-NEXT:    v_mul_lo_u32 v9, s8, v2
514; GCN-NEXT:    v_mul_lo_u32 v10, s8, v5
515; GCN-NEXT:    v_mul_hi_u32 v11, v5, v9
516; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
517; GCN-NEXT:    v_mul_hi_u32 v9, v2, v9
518; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
519; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
520; GCN-NEXT:    v_mul_hi_u32 v8, v5, v7
521; GCN-NEXT:    v_mul_hi_u32 v10, v2, v7
522; GCN-NEXT:    v_mul_lo_u32 v13, v2, v7
523; GCN-NEXT:    v_mul_lo_u32 v5, v5, v7
524; GCN-NEXT:    v_add_i32_e32 v7, vcc, v9, v13
525; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v1, v10, vcc
526; GCN-NEXT:    v_add_i32_e32 v7, vcc, v12, v7
527; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v11, vcc
528; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v8, v0, vcc
529; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
530; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
531; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v1, v8, vcc
532; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
533; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
534; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
535; GCN-NEXT:    v_mul_hi_u32 v2, v2, 24
536; GCN-NEXT:    v_mul_hi_u32 v5, v3, 24
537; GCN-NEXT:    v_mul_lo_u32 v3, v3, 24
538; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
539; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v5, vcc
540; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v0, vcc
541; GCN-NEXT:    v_mul_hi_u32 v2, s2, v1
542; GCN-NEXT:    v_mul_lo_u32 v3, s3, v1
543; GCN-NEXT:    v_mul_lo_u32 v1, s2, v1
544; GCN-NEXT:    v_mul_lo_u32 v0, s2, v0
545; GCN-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
546; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
547; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0, v0
548; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 24, v1
549; GCN-NEXT:    v_subb_u32_e64 v1, s[0:1], v2, v4, vcc
550; GCN-NEXT:    v_subb_u32_e32 v0, vcc, 0, v0, vcc
551; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v3
552; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
553; GCN-NEXT:    v_subrev_i32_e32 v5, vcc, s2, v3
554; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v1, v4, vcc
555; GCN-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
556; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v5
557; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
558; GCN-NEXT:    v_subrev_i32_e32 v7, vcc, s2, v5
559; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v0
560; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[0:1]
561; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v1
562; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[0:1]
563; GCN-NEXT:    v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
564; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v0
565; GCN-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc
566; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v1
567; GCN-NEXT:    v_cndmask_b32_e32 v6, v9, v6, vcc
568; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
569; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
570; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v2
571; GCN-NEXT:    v_cndmask_b32_e64 v1, v0, v1, s[0:1]
572; GCN-NEXT:    v_cndmask_b32_e32 v0, v5, v7, vcc
573; GCN-NEXT:    v_cndmask_b32_e64 v0, v3, v0, s[0:1]
574; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
575; GCN-NEXT:    s_endpgm
576  %result = urem i64 24, %x
577  store i64 %result, i64 addrspace(1)* %out
578  ret void
579}
580
581define amdgpu_kernel void @s_test_urem_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
582; GCN-LABEL: s_test_urem_k_den_i64:
583; GCN:       ; %bb.0:
584; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
585; GCN-NEXT:    s_mov_b32 s7, 0xf000
586; GCN-NEXT:    s_mov_b32 s6, -1
587; GCN-NEXT:    v_mov_b32_e32 v0, 0x4f800000
588; GCN-NEXT:    s_movk_i32 s8, 0xffe8
589; GCN-NEXT:    v_mov_b32_e32 v1, 0
590; GCN-NEXT:    v_mov_b32_e32 v2, 0
591; GCN-NEXT:    v_madak_f32 v0, 0, v0, 0x41c00000
592; GCN-NEXT:    v_rcp_f32_e32 v0, v0
593; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
594; GCN-NEXT:    s_waitcnt lgkmcnt(0)
595; GCN-NEXT:    s_mov_b32 s4, s0
596; GCN-NEXT:    s_mov_b32 s5, s1
597; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
598; GCN-NEXT:    v_mov_b32_e32 v4, s3
599; GCN-NEXT:    v_trunc_f32_e32 v3, v3
600; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
601; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
602; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
603; GCN-NEXT:    v_mul_lo_u32 v5, v3, s8
604; GCN-NEXT:    v_mul_hi_u32 v6, v0, s8
605; GCN-NEXT:    v_mul_lo_u32 v7, v0, s8
606; GCN-NEXT:    v_subrev_i32_e32 v6, vcc, v0, v6
607; GCN-NEXT:    v_mul_hi_u32 v8, v0, v7
608; GCN-NEXT:    v_mul_hi_u32 v9, v3, v7
609; GCN-NEXT:    v_mul_lo_u32 v7, v3, v7
610; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
611; GCN-NEXT:    v_mul_hi_u32 v6, v0, v5
612; GCN-NEXT:    v_mul_lo_u32 v10, v0, v5
613; GCN-NEXT:    v_mul_hi_u32 v11, v3, v5
614; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
615; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
616; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
617; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
618; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v9, vcc
619; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v1, vcc
620; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
621; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v7, vcc
622; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v5
623; GCN-NEXT:    v_addc_u32_e64 v5, vcc, v3, v6, s[0:1]
624; GCN-NEXT:    v_mul_hi_u32 v7, v0, s8
625; GCN-NEXT:    v_mul_lo_u32 v8, v0, s8
626; GCN-NEXT:    v_mul_lo_u32 v9, v5, s8
627; GCN-NEXT:    v_subrev_i32_e32 v7, vcc, v0, v7
628; GCN-NEXT:    v_mul_hi_u32 v10, v0, v8
629; GCN-NEXT:    v_mul_hi_u32 v11, v5, v8
630; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
631; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
632; GCN-NEXT:    v_mul_hi_u32 v9, v0, v7
633; GCN-NEXT:    v_mul_lo_u32 v12, v0, v7
634; GCN-NEXT:    v_mul_hi_u32 v13, v5, v7
635; GCN-NEXT:    v_mul_lo_u32 v5, v5, v7
636; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v12
637; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v2, v9, vcc
638; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
639; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v11, vcc
640; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v1, vcc
641; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
642; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
643; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v8, vcc
644; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
645; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v5
646; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
647; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
648; GCN-NEXT:    v_mul_hi_u32 v6, s3, v0
649; GCN-NEXT:    v_mul_lo_u32 v0, s3, v0
650; GCN-NEXT:    v_mul_hi_u32 v7, s2, v3
651; GCN-NEXT:    v_mul_lo_u32 v8, s2, v3
652; GCN-NEXT:    v_mul_hi_u32 v9, s3, v3
653; GCN-NEXT:    v_mul_lo_u32 v3, s3, v3
654; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
655; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v7, vcc
656; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v5
657; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v7, v6, vcc
658; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v9, v1, vcc
659; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
660; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
661; GCN-NEXT:    v_mul_hi_u32 v2, v0, 24
662; GCN-NEXT:    v_mul_lo_u32 v0, v0, 24
663; GCN-NEXT:    v_mul_lo_u32 v1, v1, 24
664; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
665; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
666; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v4, v1, vcc
667; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v0
668; GCN-NEXT:    v_cmp_lt_u32_e64 s[0:1], 23, v0
669; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, s[0:1]
670; GCN-NEXT:    v_subbrev_u32_e32 v4, vcc, 0, v1, vcc
671; GCN-NEXT:    v_subrev_i32_e32 v5, vcc, 24, v2
672; GCN-NEXT:    v_cmp_lt_u32_e64 s[0:1], 23, v2
673; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
674; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
675; GCN-NEXT:    v_cndmask_b32_e64 v3, -1, v3, s[0:1]
676; GCN-NEXT:    v_subbrev_u32_e32 v7, vcc, 0, v4, vcc
677; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v4
678; GCN-NEXT:    v_cndmask_b32_e32 v6, -1, v6, vcc
679; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
680; GCN-NEXT:    v_cndmask_b32_e32 v4, v4, v7, vcc
681; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v3
682; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[0:1]
683; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
684; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
685; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
686; GCN-NEXT:    s_endpgm
687  %result = urem i64 %x, 24
688  store i64 %result, i64 addrspace(1)* %out
689  ret void
690}
691
692; FIXME: Constant bus violation
693; define i64 @v_test_urem_k_num_i64(i64 %x) {
694;   %result = urem i64 24, %x
695;   ret i64 %result
696; }
697
698define i64 @v_test_urem_pow2_k_num_i64(i64 %x) {
699; GCN-LABEL: v_test_urem_pow2_k_num_i64:
700; GCN:       ; %bb.0:
701; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
702; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
703; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
704; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
705; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
706; GCN-NEXT:    v_mov_b32_e32 v6, 0
707; GCN-NEXT:    v_mov_b32_e32 v7, 0
708; GCN-NEXT:    s_mov_b32 s6, 0x8000
709; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
710; GCN-NEXT:    v_rcp_f32_e32 v2, v2
711; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
712; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
713; GCN-NEXT:    v_trunc_f32_e32 v3, v3
714; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
715; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
716; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
717; GCN-NEXT:    v_mul_lo_u32 v8, v4, v3
718; GCN-NEXT:    v_mul_lo_u32 v9, v5, v2
719; GCN-NEXT:    v_mul_hi_u32 v10, v4, v2
720; GCN-NEXT:    v_mul_lo_u32 v11, v4, v2
721; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
722; GCN-NEXT:    v_mul_hi_u32 v10, v2, v11
723; GCN-NEXT:    v_mul_hi_u32 v12, v3, v11
724; GCN-NEXT:    v_mul_lo_u32 v11, v3, v11
725; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
726; GCN-NEXT:    v_mul_hi_u32 v9, v2, v8
727; GCN-NEXT:    v_mul_lo_u32 v13, v2, v8
728; GCN-NEXT:    v_mul_hi_u32 v14, v3, v8
729; GCN-NEXT:    v_mul_lo_u32 v8, v3, v8
730; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
731; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v7, v9, vcc
732; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
733; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v9, v12, vcc
734; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v6, vcc
735; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
736; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v7, v10, vcc
737; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v8
738; GCN-NEXT:    v_addc_u32_e64 v8, vcc, v3, v9, s[4:5]
739; GCN-NEXT:    v_mul_hi_u32 v10, v4, v2
740; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
741; GCN-NEXT:    v_mul_lo_u32 v11, v4, v2
742; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v9
743; GCN-NEXT:    v_mul_lo_u32 v4, v4, v8
744; GCN-NEXT:    v_mul_hi_u32 v9, v8, v11
745; GCN-NEXT:    v_mul_lo_u32 v12, v8, v11
746; GCN-NEXT:    v_mul_hi_u32 v11, v2, v11
747; GCN-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
748; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
749; GCN-NEXT:    v_mul_hi_u32 v5, v8, v4
750; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
751; GCN-NEXT:    v_mul_lo_u32 v13, v2, v4
752; GCN-NEXT:    v_mul_lo_u32 v4, v8, v4
753; GCN-NEXT:    v_add_i32_e32 v8, vcc, v11, v13
754; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v7, v10, vcc
755; GCN-NEXT:    v_add_i32_e32 v8, vcc, v12, v8
756; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v9, vcc
757; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v6, vcc
758; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
759; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v5, vcc
760; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
761; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
762; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
763; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
764; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
765; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
766; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
767; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
768; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s6, v2
769; GCN-NEXT:    v_sub_i32_e64 v4, s[4:5], 0, v3
770; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v0
771; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[4:5]
772; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
773; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
774; GCN-NEXT:    v_sub_i32_e32 v6, vcc, v2, v0
775; GCN-NEXT:    v_subb_u32_e64 v7, s[4:5], v4, v1, vcc
776; GCN-NEXT:    v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
777; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v6, v0
778; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
779; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v6, v0
780; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v3, v1
781; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
782; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v4, v1
783; GCN-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
784; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v3, v1
785; GCN-NEXT:    v_cndmask_b32_e64 v5, v9, v5, s[4:5]
786; GCN-NEXT:    v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
787; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v4, v1
788; GCN-NEXT:    v_cndmask_b32_e32 v1, v10, v8, vcc
789; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
790; GCN-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
791; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v5
792; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v0, s[4:5]
793; GCN-NEXT:    v_cndmask_b32_e32 v1, v4, v7, vcc
794; GCN-NEXT:    v_cndmask_b32_e64 v1, v3, v1, s[4:5]
795; GCN-NEXT:    s_setpc_b64 s[30:31]
796  %result = urem i64 32768, %x
797  ret i64 %result
798}
799
800define i64 @v_test_urem_pow2_k_den_i64(i64 %x) {
801; GCN-LABEL: v_test_urem_pow2_k_den_i64:
802; GCN:       ; %bb.0:
803; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
804; GCN-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
805; GCN-NEXT:    v_mov_b32_e32 v1, 0
806; GCN-NEXT:    s_setpc_b64 s[30:31]
807  %result = urem i64 %x, 32768
808  ret i64 %result
809}
810
811define amdgpu_kernel void @s_test_urem24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
812; GCN-LABEL: s_test_urem24_k_num_i64:
813; GCN:       ; %bb.0:
814; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
815; GCN-NEXT:    s_mov_b32 s7, 0xf000
816; GCN-NEXT:    s_mov_b32 s6, -1
817; GCN-NEXT:    s_waitcnt lgkmcnt(0)
818; GCN-NEXT:    s_mov_b32 s4, s0
819; GCN-NEXT:    s_mov_b32 s5, s1
820; GCN-NEXT:    s_lshr_b32 s8, s3, 8
821; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
822; GCN-NEXT:    v_rcp_iflag_f32_e32 v0, v0
823; GCN-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0
824; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
825; GCN-NEXT:    v_mul_hi_u32 v1, v0, s8
826; GCN-NEXT:    v_mul_lo_u32 v2, v0, s8
827; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 0, v2
828; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
829; GCN-NEXT:    v_cndmask_b32_e64 v1, v2, v3, s[0:1]
830; GCN-NEXT:    v_mul_hi_u32 v1, v1, v0
831; GCN-NEXT:    v_add_i32_e32 v2, vcc, v1, v0
832; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, v1, v0
833; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
834; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
835; GCN-NEXT:    v_mul_lo_u32 v0, v0, s8
836; GCN-NEXT:    v_sub_i32_e32 v1, vcc, 24, v0
837; GCN-NEXT:    v_add_i32_e32 v2, vcc, s8, v1
838; GCN-NEXT:    v_cmp_gt_u32_e64 s[0:1], 25, v0
839; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v1
840; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s8, v1
841; GCN-NEXT:    s_and_b64 vcc, s[2:3], s[0:1]
842; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
843; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v0, s[0:1]
844; GCN-NEXT:    v_mov_b32_e32 v1, 0
845; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
846; GCN-NEXT:    s_endpgm
847  %x.shr = lshr i64 %x, 40
848  %result = urem i64 24, %x.shr
849  store i64 %result, i64 addrspace(1)* %out
850  ret void
851}
852
853define amdgpu_kernel void @s_test_urem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
854; GCN-LABEL: s_test_urem24_k_den_i64:
855; GCN:       ; %bb.0:
856; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
857; GCN-NEXT:    s_mov_b32 s7, 0xf000
858; GCN-NEXT:    s_mov_b32 s6, -1
859; GCN-NEXT:    s_waitcnt lgkmcnt(0)
860; GCN-NEXT:    s_movk_i32 s2, 0x5b7f
861; GCN-NEXT:    s_movk_i32 s8, 0x5b7e
862; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
863; GCN-NEXT:    v_rcp_iflag_f32_e32 v0, v0
864; GCN-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0
865; GCN-NEXT:    s_mov_b32 s4, s0
866; GCN-NEXT:    s_mov_b32 s5, s1
867; GCN-NEXT:    s_lshr_b32 s3, s3, 8
868; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
869; GCN-NEXT:    v_mul_hi_u32 v1, v0, s2
870; GCN-NEXT:    v_mul_lo_u32 v2, v0, s2
871; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 0, v2
872; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
873; GCN-NEXT:    v_cndmask_b32_e64 v1, v2, v3, s[0:1]
874; GCN-NEXT:    v_mul_hi_u32 v1, v1, v0
875; GCN-NEXT:    v_add_i32_e32 v2, vcc, v1, v0
876; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, v1, v0
877; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
878; GCN-NEXT:    v_mul_hi_u32 v0, v0, s3
879; GCN-NEXT:    v_mul_lo_u32 v0, v0, s2
880; GCN-NEXT:    v_sub_i32_e32 v1, vcc, s3, v0
881; GCN-NEXT:    v_add_i32_e32 v2, vcc, s2, v1
882; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], s3, v0
883; GCN-NEXT:    v_cmp_lt_u32_e64 s[2:3], s8, v1
884; GCN-NEXT:    v_add_i32_e32 v0, vcc, 0xffffa481, v1
885; GCN-NEXT:    s_and_b64 vcc, s[2:3], s[0:1]
886; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
887; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v0, s[0:1]
888; GCN-NEXT:    v_mov_b32_e32 v1, 0
889; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
890; GCN-NEXT:    s_endpgm
891  %x.shr = lshr i64 %x, 40
892  %result = urem i64 %x.shr, 23423
893  store i64 %result, i64 addrspace(1)* %out
894  ret void
895}
896
897define i64 @v_test_urem24_k_num_i64(i64 %x) {
898; GCN-LABEL: v_test_urem24_k_num_i64:
899; GCN:       ; %bb.0:
900; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
901; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
902; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v0
903; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v1
904; GCN-NEXT:    v_mul_f32_e32 v1, 0x4f800000, v1
905; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
906; GCN-NEXT:    v_mul_hi_u32 v2, v1, v0
907; GCN-NEXT:    v_mul_lo_u32 v3, v1, v0
908; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
909; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v2
910; GCN-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc
911; GCN-NEXT:    v_mul_hi_u32 v2, v2, v1
912; GCN-NEXT:    v_add_i32_e64 v3, s[4:5], v1, v2
913; GCN-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v2
914; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
915; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
916; GCN-NEXT:    v_mul_lo_u32 v1, v1, v0
917; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 24, v1
918; GCN-NEXT:    v_add_i32_e32 v3, vcc, v2, v0
919; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, 25, v1
920; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v0
921; GCN-NEXT:    v_sub_i32_e64 v0, s[6:7], v2, v0
922; GCN-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
923; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v0, s[4:5]
924; GCN-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
925; GCN-NEXT:    v_mov_b32_e32 v1, 0
926; GCN-NEXT:    s_setpc_b64 s[30:31]
927  %x.shr = lshr i64 %x, 40
928  %result = urem i64 24, %x.shr
929  ret i64 %result
930}
931
932define i64 @v_test_urem24_pow2_k_num_i64(i64 %x) {
933; GCN-LABEL: v_test_urem24_pow2_k_num_i64:
934; GCN:       ; %bb.0:
935; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
936; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
937; GCN-NEXT:    s_mov_b32 s6, 0x8001
938; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v0
939; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v1
940; GCN-NEXT:    v_mul_f32_e32 v1, 0x4f800000, v1
941; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
942; GCN-NEXT:    v_mul_hi_u32 v2, v1, v0
943; GCN-NEXT:    v_mul_lo_u32 v3, v1, v0
944; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
945; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v2
946; GCN-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc
947; GCN-NEXT:    v_mul_hi_u32 v2, v2, v1
948; GCN-NEXT:    v_add_i32_e64 v3, s[4:5], v1, v2
949; GCN-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v2
950; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
951; GCN-NEXT:    v_lshrrev_b32_e32 v1, 17, v1
952; GCN-NEXT:    v_mul_u32_u24_e32 v1, v1, v0
953; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0x8000, v1
954; GCN-NEXT:    v_add_i32_e32 v3, vcc, v2, v0
955; GCN-NEXT:    v_cmp_gt_u32_e32 vcc, s6, v1
956; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v0
957; GCN-NEXT:    v_sub_i32_e64 v0, s[6:7], v2, v0
958; GCN-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
959; GCN-NEXT:    v_cndmask_b32_e64 v0, v2, v0, s[4:5]
960; GCN-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
961; GCN-NEXT:    v_mov_b32_e32 v1, 0
962; GCN-NEXT:    s_setpc_b64 s[30:31]
963  %x.shr = lshr i64 %x, 40
964  %result = urem i64 32768, %x.shr
965  ret i64 %result
966}
967
968define i64 @v_test_urem24_pow2_k_den_i64(i64 %x) {
969; GCN-LABEL: v_test_urem24_pow2_k_den_i64:
970; GCN:       ; %bb.0:
971; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
972; GCN-NEXT:    v_bfe_u32 v0, v1, 8, 15
973; GCN-NEXT:    v_mov_b32_e32 v1, 0
974; GCN-NEXT:    s_setpc_b64 s[30:31]
975  %x.shr = lshr i64 %x, 40
976  %result = urem i64 %x.shr, 32768
977  ret i64 %result
978}
979