1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_urem_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_urem_i64:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
9; GCN-NEXT:    v_mov_b32_e32 v2, 0
10; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
11; GCN-NEXT:    s_mov_b32 s7, 0xf000
12; GCN-NEXT:    s_mov_b32 s6, -1
13; GCN-NEXT:    s_waitcnt lgkmcnt(0)
14; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
15; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
16; GCN-NEXT:    s_sub_u32 s2, 0, s12
17; GCN-NEXT:    s_subb_u32 s3, 0, s13
18; GCN-NEXT:    s_mov_b32 s4, s8
19; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
20; GCN-NEXT:    v_rcp_f32_e32 v0, v0
21; GCN-NEXT:    v_mov_b32_e32 v1, 0
22; GCN-NEXT:    s_mov_b32 s5, s9
23; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
24; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
25; GCN-NEXT:    v_trunc_f32_e32 v3, v3
26; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
27; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
28; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
29; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
30; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
31; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
32; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
33; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
34; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
35; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
36; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
37; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
38; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
39; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
40; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
41; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
42; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
43; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
44; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
45; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
46; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v1, vcc
47; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
48; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
49; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
50; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
51; GCN-NEXT:    v_mul_lo_u32 v6, s2, v4
52; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
53; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
54; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
55; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
56; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
57; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
58; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
59; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
60; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
61; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
62; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
63; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
64; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
65; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
66; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
67; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
68; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
69; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
70; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
71; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
72; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
73; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
74; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
75; GCN-NEXT:    v_mul_lo_u32 v4, s10, v3
76; GCN-NEXT:    v_mul_hi_u32 v5, s10, v0
77; GCN-NEXT:    v_mul_hi_u32 v6, s10, v3
78; GCN-NEXT:    v_mul_hi_u32 v7, s11, v3
79; GCN-NEXT:    v_mul_lo_u32 v3, s11, v3
80; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
81; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
82; GCN-NEXT:    v_mul_lo_u32 v6, s11, v0
83; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
84; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
85; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
86; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
87; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
88; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
89; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
90; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
91; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
92; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
93; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
94; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
95; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
96; GCN-NEXT:    v_mov_b32_e32 v3, s13
97; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s10, v0
98; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
99; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
100; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
101; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
102; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
103; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
104; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
105; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
106; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
107; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
108; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
109; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
110; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
111; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
112; GCN-NEXT:    v_mov_b32_e32 v5, s11
113; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
114; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
115; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
116; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
117; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
118; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
119; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
120; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
121; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
122; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
123; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
124; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
125; GCN-NEXT:    s_endpgm
126;
127; GCN-IR-LABEL: s_test_urem_i64:
128; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
129; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
130; GCN-IR-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
131; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
132; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[6:7], 0
133; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s2
134; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
135; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s3
136; GCN-IR-NEXT:    v_mov_b32_e32 v1, s10
137; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s6
138; GCN-IR-NEXT:    v_mov_b32_e32 v0, s11
139; GCN-IR-NEXT:    v_cmp_eq_u32_e64 vcc, s3, 0
140; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
141; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s7
142; GCN-IR-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
143; GCN-IR-NEXT:    v_mov_b32_e32 v0, s11
144; GCN-IR-NEXT:    v_mov_b32_e32 v1, s10
145; GCN-IR-NEXT:    v_cmp_eq_u32_e64 vcc, s7, 0
146; GCN-IR-NEXT:    v_cndmask_b32_e32 v3, v0, v1, vcc
147; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v2, v3
148; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[2:3], 0
149; GCN-IR-NEXT:    v_subb_u32_e64 v1, s[10:11], 0, 0, vcc
150; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[0:1]
151; GCN-IR-NEXT:    s_or_b64 s[0:1], s[0:1], s[8:9]
152; GCN-IR-NEXT:    s_or_b64 s[0:1], s[0:1], vcc
153; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[0:1]
154; GCN-IR-NEXT:    s_xor_b64 s[8:9], s[0:1], -1
155; GCN-IR-NEXT:    s_and_b64 s[8:9], s[8:9], vcc
156; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[8:9]
157; GCN-IR-NEXT:    s_cbranch_vccz BB0_4
158; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
159; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
160; GCN-IR-NEXT:    v_addc_u32_e32 v5, vcc, 0, v1, vcc
161; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1]
162; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 63, v0
163; GCN-IR-NEXT:    v_lshl_b64 v[0:1], s[6:7], v0
164; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[0:1]
165; GCN-IR-NEXT:    s_cbranch_vccz BB0_5
166; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
167; GCN-IR-NEXT:    v_not_b32_e32 v2, v2
168; GCN-IR-NEXT:    s_add_u32 s8, s2, -1
169; GCN-IR-NEXT:    v_lshr_b64 v[6:7], s[6:7], v4
170; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, v2, v3
171; GCN-IR-NEXT:    v_mov_b32_e32 v8, 0
172; GCN-IR-NEXT:    s_addc_u32 s9, s3, -1
173; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[0:1], -1, 0, vcc
174; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
175; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
176; GCN-IR-NEXT:  BB0_3: ; %udiv-do-while
177; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
178; GCN-IR-NEXT:    v_lshl_b64 v[6:7], v[6:7], 1
179; GCN-IR-NEXT:    v_lshrrev_b32_e32 v2, 31, v1
180; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
181; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v2
182; GCN-IR-NEXT:    v_or_b32_e32 v0, v8, v0
183; GCN-IR-NEXT:    v_mov_b32_e32 v2, s9
184; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, s8, v6
185; GCN-IR-NEXT:    v_subb_u32_e32 v2, vcc, v2, v7, vcc
186; GCN-IR-NEXT:    v_ashrrev_i32_e32 v8, 31, v2
187; GCN-IR-NEXT:    v_and_b32_e32 v10, s2, v8
188; GCN-IR-NEXT:    v_and_b32_e32 v2, 1, v8
189; GCN-IR-NEXT:    v_and_b32_e32 v11, s3, v8
190; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
191; GCN-IR-NEXT:    v_or_b32_e32 v1, v9, v1
192; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
193; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
194; GCN-IR-NEXT:    v_mov_b32_e32 v4, v8
195; GCN-IR-NEXT:    v_sub_i32_e64 v6, s[0:1], v6, v10
196; GCN-IR-NEXT:    v_mov_b32_e32 v5, v9
197; GCN-IR-NEXT:    v_mov_b32_e32 v9, v3
198; GCN-IR-NEXT:    v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1]
199; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
200; GCN-IR-NEXT:    v_mov_b32_e32 v8, v2
201; GCN-IR-NEXT:    s_cbranch_vccz BB0_3
202; GCN-IR-NEXT:    s_branch BB0_6
203; GCN-IR-NEXT:  BB0_4:
204; GCN-IR-NEXT:    v_mov_b32_e32 v0, s7
205; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[0:1]
206; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
207; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[0:1]
208; GCN-IR-NEXT:    s_branch BB0_7
209; GCN-IR-NEXT:  BB0_5:
210; GCN-IR-NEXT:    v_mov_b32_e32 v2, 0
211; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
212; GCN-IR-NEXT:  BB0_6: ; %Flow6
213; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
214; GCN-IR-NEXT:    v_or_b32_e32 v0, v2, v0
215; GCN-IR-NEXT:    v_or_b32_e32 v1, v3, v1
216; GCN-IR-NEXT:  BB0_7: ; %udiv-end
217; GCN-IR-NEXT:    v_mul_lo_u32 v1, s2, v1
218; GCN-IR-NEXT:    v_mul_hi_u32 v2, s2, v0
219; GCN-IR-NEXT:    v_mul_lo_u32 v3, s3, v0
220; GCN-IR-NEXT:    v_mul_lo_u32 v0, s2, v0
221; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
222; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
223; GCN-IR-NEXT:    v_mov_b32_e32 v2, s7
224; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
225; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
226; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
227; GCN-IR-NEXT:    s_mov_b32 s6, -1
228; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
229; GCN-IR-NEXT:    s_endpgm
230  %result = urem i64 %x, %y
231  store i64 %result, i64 addrspace(1)* %out
232  ret void
233}
234
235define i64 @v_test_urem_i64(i64 %x, i64 %y) {
236; GCN-LABEL: v_test_urem_i64:
237; GCN:       ; %bb.0:
238; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
239; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
240; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v3
241; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v2
242; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v3, vcc
243; GCN-NEXT:    v_mov_b32_e32 v14, 0
244; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
245; GCN-NEXT:    v_rcp_f32_e32 v4, v4
246; GCN-NEXT:    v_mov_b32_e32 v13, 0
247; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
248; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
249; GCN-NEXT:    v_trunc_f32_e32 v5, v5
250; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
251; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
252; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
253; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
254; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
255; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
256; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
257; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
258; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
259; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
260; GCN-NEXT:    v_mul_hi_u32 v10, v4, v8
261; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
262; GCN-NEXT:    v_mul_hi_u32 v15, v5, v8
263; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
264; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
265; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
266; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
267; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v10, vcc
268; GCN-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
269; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v10, v9, vcc
270; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v15, v13, vcc
271; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
272; GCN-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v8
273; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v10, vcc
274; GCN-NEXT:    v_addc_u32_e64 v8, vcc, v5, v9, s[4:5]
275; GCN-NEXT:    v_mul_lo_u32 v10, v6, v8
276; GCN-NEXT:    v_mul_hi_u32 v11, v6, v4
277; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
278; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
279; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
280; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
281; GCN-NEXT:    v_mul_lo_u32 v12, v4, v7
282; GCN-NEXT:    v_mul_hi_u32 v15, v4, v6
283; GCN-NEXT:    v_mul_hi_u32 v16, v4, v7
284; GCN-NEXT:    v_mul_hi_u32 v11, v8, v6
285; GCN-NEXT:    v_mul_lo_u32 v6, v8, v6
286; GCN-NEXT:    v_add_i32_e32 v12, vcc, v15, v12
287; GCN-NEXT:    v_mul_hi_u32 v10, v8, v7
288; GCN-NEXT:    v_addc_u32_e32 v15, vcc, v14, v16, vcc
289; GCN-NEXT:    v_mul_lo_u32 v7, v8, v7
290; GCN-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
291; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v15, v11, vcc
292; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v13, vcc
293; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
294; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v14, v8, vcc
295; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
296; GCN-NEXT:    v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
297; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
298; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
299; GCN-NEXT:    v_mul_lo_u32 v6, v0, v5
300; GCN-NEXT:    v_mul_hi_u32 v7, v0, v4
301; GCN-NEXT:    v_mul_hi_u32 v8, v0, v5
302; GCN-NEXT:    v_mul_hi_u32 v9, v1, v5
303; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
304; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
305; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v14, v8, vcc
306; GCN-NEXT:    v_mul_lo_u32 v8, v1, v4
307; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
308; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
309; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v4, vcc
310; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v13, vcc
311; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
312; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v14, v6, vcc
313; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
314; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
315; GCN-NEXT:    v_mul_lo_u32 v7, v3, v4
316; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
317; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
318; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
319; GCN-NEXT:    v_sub_i32_e32 v6, vcc, v1, v5
320; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
321; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v6, v3, vcc
322; GCN-NEXT:    v_sub_i32_e64 v6, s[4:5], v0, v2
323; GCN-NEXT:    v_subbrev_u32_e64 v7, s[6:7], 0, v4, s[4:5]
324; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v7, v3
325; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
326; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
327; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v2
328; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[6:7]
329; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v7, v3
330; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
331; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v3, s[4:5]
332; GCN-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[6:7]
333; GCN-NEXT:    v_sub_i32_e64 v9, s[4:5], v6, v2
334; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
335; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
336; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
337; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
338; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
339; GCN-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
340; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v8
341; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
342; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v9, s[4:5]
343; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v4, s[4:5]
344; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
345; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
346; GCN-NEXT:    s_setpc_b64 s[30:31]
347;
348; GCN-IR-LABEL: v_test_urem_i64:
349; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
350; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
351; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[2:3]
352; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
353; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v2
354; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
355; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
356; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v3
357; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
358; GCN-IR-NEXT:    v_cndmask_b32_e32 v10, v5, v4, vcc
359; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
360; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
361; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
362; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
363; GCN-IR-NEXT:    v_cndmask_b32_e32 v12, v5, v4, vcc
364; GCN-IR-NEXT:    v_sub_i32_e32 v5, vcc, v10, v12
365; GCN-IR-NEXT:    v_subb_u32_e64 v6, s[6:7], 0, 0, vcc
366; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[5:6]
367; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
368; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
369; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[5:6]
370; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
371; GCN-IR-NEXT:    v_mov_b32_e32 v13, v11
372; GCN-IR-NEXT:    v_cndmask_b32_e64 v7, v1, 0, s[4:5]
373; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v0, 0, s[4:5]
374; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
375; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
376; GCN-IR-NEXT:    s_cbranch_execz BB1_6
377; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
378; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 1, v5
379; GCN-IR-NEXT:    v_addc_u32_e32 v8, vcc, 0, v6, vcc
380; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v5
381; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[7:8], v[5:6]
382; GCN-IR-NEXT:    v_mov_b32_e32 v8, 0
383; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[0:1], v4
384; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
385; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
386; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
387; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
388; GCN-IR-NEXT:    s_cbranch_execz BB1_5
389; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
390; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, -1, v2
391; GCN-IR-NEXT:    v_lshr_b64 v[14:15], v[0:1], v7
392; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, -1, v3, vcc
393; GCN-IR-NEXT:    v_not_b32_e32 v8, v10
394; GCN-IR-NEXT:    v_not_b32_e32 v9, v11
395; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, v8, v12
396; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, v9, v13, vcc
397; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
398; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
399; GCN-IR-NEXT:  BB1_3: ; %udiv-do-while
400; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
401; GCN-IR-NEXT:    v_lshl_b64 v[14:15], v[14:15], 1
402; GCN-IR-NEXT:    v_lshrrev_b32_e32 v8, 31, v5
403; GCN-IR-NEXT:    v_or_b32_e32 v14, v14, v8
404; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
405; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, v6, v14
406; GCN-IR-NEXT:    v_subb_u32_e32 v8, vcc, v7, v15, vcc
407; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
408; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v8
409; GCN-IR-NEXT:    v_and_b32_e32 v17, v12, v2
410; GCN-IR-NEXT:    v_and_b32_e32 v8, 1, v12
411; GCN-IR-NEXT:    v_and_b32_e32 v16, v12, v3
412; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v10
413; GCN-IR-NEXT:    v_or_b32_e32 v5, v13, v5
414; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v11, vcc
415; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[10:11]
416; GCN-IR-NEXT:    v_mov_b32_e32 v10, v12
417; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
418; GCN-IR-NEXT:    v_sub_i32_e64 v14, s[4:5], v14, v17
419; GCN-IR-NEXT:    v_mov_b32_e32 v11, v13
420; GCN-IR-NEXT:    v_mov_b32_e32 v13, v9
421; GCN-IR-NEXT:    v_subb_u32_e64 v15, s[4:5], v15, v16, s[4:5]
422; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
423; GCN-IR-NEXT:    v_mov_b32_e32 v12, v8
424; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
425; GCN-IR-NEXT:    s_cbranch_execnz BB1_3
426; GCN-IR-NEXT:  ; %bb.4: ; %Flow
427; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
428; GCN-IR-NEXT:  BB1_5: ; %Flow3
429; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
430; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
431; GCN-IR-NEXT:    v_or_b32_e32 v7, v9, v5
432; GCN-IR-NEXT:    v_or_b32_e32 v4, v8, v4
433; GCN-IR-NEXT:  BB1_6: ; %Flow4
434; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
435; GCN-IR-NEXT:    v_mul_lo_u32 v5, v2, v7
436; GCN-IR-NEXT:    v_mul_hi_u32 v6, v2, v4
437; GCN-IR-NEXT:    v_mul_lo_u32 v3, v3, v4
438; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, v4
439; GCN-IR-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
440; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
441; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
442; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
443; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
444  %result = urem i64 %x, %y
445  ret i64 %result
446}
447
448define amdgpu_kernel void @s_test_urem31_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
449; GCN-LABEL: s_test_urem31_i64:
450; GCN:       ; %bb.0:
451; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
452; GCN-NEXT:    s_waitcnt lgkmcnt(0)
453; GCN-NEXT:    s_lshr_b32 s4, s2, 1
454; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
455; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
456; GCN-NEXT:    s_waitcnt lgkmcnt(0)
457; GCN-NEXT:    s_mov_b32 s2, -1
458; GCN-NEXT:    s_lshr_b32 s5, s3, 1
459; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s5
460; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
461; GCN-NEXT:    s_mov_b32 s3, 0xf000
462; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
463; GCN-NEXT:    v_trunc_f32_e32 v2, v2
464; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
465; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
466; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
467; GCN-NEXT:    v_mov_b32_e32 v1, 0
468; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
469; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
470; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
471; GCN-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
472; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
473; GCN-NEXT:    s_endpgm
474;
475; GCN-IR-LABEL: s_test_urem31_i64:
476; GCN-IR:       ; %bb.0:
477; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xe
478; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
479; GCN-IR-NEXT:    s_lshr_b32 s4, s2, 1
480; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
481; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
482; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
483; GCN-IR-NEXT:    s_mov_b32 s2, -1
484; GCN-IR-NEXT:    s_lshr_b32 s5, s3, 1
485; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s5
486; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
487; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
488; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
489; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
490; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
491; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
492; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
493; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
494; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
495; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
496; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
497; GCN-IR-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
498; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
499; GCN-IR-NEXT:    s_endpgm
500  %1 = lshr i64 %x, 33
501  %2 = lshr i64 %y, 33
502  %result = urem i64 %1, %2
503  store i64 %result, i64 addrspace(1)* %out
504  ret void
505}
506
507define amdgpu_kernel void @s_test_urem31_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
508; GCN-LABEL: s_test_urem31_v2i64:
509; GCN:       ; %bb.0:
510; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
511; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
512; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
513; GCN-NEXT:    s_mov_b32 s7, 0xf000
514; GCN-NEXT:    s_mov_b32 s6, -1
515; GCN-NEXT:    s_waitcnt lgkmcnt(0)
516; GCN-NEXT:    s_lshr_b32 s2, s9, 1
517; GCN-NEXT:    s_lshr_b32 s0, s1, 1
518; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
519; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s2
520; GCN-NEXT:    s_lshr_b32 s3, s3, 1
521; GCN-NEXT:    v_cvt_f32_u32_e32 v4, s3
522; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
523; GCN-NEXT:    s_lshr_b32 s1, s11, 1
524; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s1
525; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
526; GCN-NEXT:    v_trunc_f32_e32 v2, v2
527; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
528; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
529; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v4
530; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
531; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
532; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
533; GCN-NEXT:    v_mul_f32_e32 v2, v3, v2
534; GCN-NEXT:    v_trunc_f32_e32 v2, v2
535; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
536; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
537; GCN-NEXT:    v_mad_f32 v2, -v2, v4, v3
538; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
539; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
540; GCN-NEXT:    v_mul_lo_u32 v2, v2, s3
541; GCN-NEXT:    v_mov_b32_e32 v1, 0
542; GCN-NEXT:    s_brev_b32 s0, -2
543; GCN-NEXT:    v_and_b32_e32 v0, s0, v0
544; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
545; GCN-NEXT:    v_and_b32_e32 v2, s0, v2
546; GCN-NEXT:    v_mov_b32_e32 v3, v1
547; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
548; GCN-NEXT:    s_endpgm
549;
550; GCN-IR-LABEL: s_test_urem31_v2i64:
551; GCN-IR:       ; %bb.0:
552; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
553; GCN-IR-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
554; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
555; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
556; GCN-IR-NEXT:    s_mov_b32 s6, -1
557; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
558; GCN-IR-NEXT:    s_lshr_b32 s2, s9, 1
559; GCN-IR-NEXT:    s_lshr_b32 s0, s1, 1
560; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
561; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s2
562; GCN-IR-NEXT:    s_lshr_b32 s3, s3, 1
563; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v4, s3
564; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
565; GCN-IR-NEXT:    s_lshr_b32 s1, s11, 1
566; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v3, s1
567; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
568; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
569; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
570; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
571; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v4
572; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
573; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
574; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
575; GCN-IR-NEXT:    v_mul_f32_e32 v2, v3, v2
576; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
577; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
578; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
579; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v4, v3
580; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
581; GCN-IR-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
582; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, s3
583; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
584; GCN-IR-NEXT:    s_brev_b32 s0, -2
585; GCN-IR-NEXT:    v_and_b32_e32 v0, s0, v0
586; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
587; GCN-IR-NEXT:    v_and_b32_e32 v2, s0, v2
588; GCN-IR-NEXT:    v_mov_b32_e32 v3, v1
589; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
590; GCN-IR-NEXT:    s_endpgm
591  %1 = lshr <2 x i64> %x, <i64 33, i64 33>
592  %2 = lshr <2 x i64> %y, <i64 33, i64 33>
593  %result = urem <2 x i64> %1, %2
594  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
595  ret void
596}
597
598define amdgpu_kernel void @s_test_urem24_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
599; GCN-LABEL: s_test_urem24_i64:
600; GCN:       ; %bb.0:
601; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
602; GCN-NEXT:    s_waitcnt lgkmcnt(0)
603; GCN-NEXT:    s_lshr_b32 s4, s2, 8
604; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
605; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
606; GCN-NEXT:    s_waitcnt lgkmcnt(0)
607; GCN-NEXT:    s_mov_b32 s2, -1
608; GCN-NEXT:    s_lshr_b32 s5, s3, 8
609; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s5
610; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
611; GCN-NEXT:    s_mov_b32 s3, 0xf000
612; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
613; GCN-NEXT:    v_trunc_f32_e32 v2, v2
614; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
615; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
616; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
617; GCN-NEXT:    v_mov_b32_e32 v1, 0
618; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
619; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
620; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
621; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
622; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
623; GCN-NEXT:    s_endpgm
624;
625; GCN-IR-LABEL: s_test_urem24_i64:
626; GCN-IR:       ; %bb.0:
627; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xe
628; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
629; GCN-IR-NEXT:    s_lshr_b32 s4, s2, 8
630; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
631; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
632; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
633; GCN-IR-NEXT:    s_mov_b32 s2, -1
634; GCN-IR-NEXT:    s_lshr_b32 s5, s3, 8
635; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s5
636; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
637; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
638; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
639; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
640; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
641; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
642; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
643; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
644; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
645; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
646; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
647; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
648; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
649; GCN-IR-NEXT:    s_endpgm
650  %1 = lshr i64 %x, 40
651  %2 = lshr i64 %y, 40
652  %result = urem i64 %1, %2
653  store i64 %result, i64 addrspace(1)* %out
654  ret void
655}
656
657define amdgpu_kernel void @s_test_urem23_64_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
658; GCN-LABEL: s_test_urem23_64_v2i64:
659; GCN:       ; %bb.0:
660; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
661; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
662; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
663; GCN-NEXT:    s_mov_b32 s7, 0xf000
664; GCN-NEXT:    s_mov_b32 s6, -1
665; GCN-NEXT:    s_waitcnt lgkmcnt(0)
666; GCN-NEXT:    s_lshr_b32 s2, s9, 1
667; GCN-NEXT:    s_lshr_b32 s0, s1, 1
668; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
669; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s2
670; GCN-NEXT:    s_lshr_b32 s3, s3, 9
671; GCN-NEXT:    v_cvt_f32_u32_e32 v4, s3
672; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
673; GCN-NEXT:    s_lshr_b32 s1, s11, 9
674; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s1
675; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
676; GCN-NEXT:    v_trunc_f32_e32 v2, v2
677; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
678; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
679; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v4
680; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
681; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
682; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
683; GCN-NEXT:    v_mul_f32_e32 v2, v3, v2
684; GCN-NEXT:    v_trunc_f32_e32 v2, v2
685; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
686; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
687; GCN-NEXT:    v_mad_f32 v2, -v2, v4, v3
688; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
689; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
690; GCN-NEXT:    v_mul_lo_u32 v2, v2, s3
691; GCN-NEXT:    v_mov_b32_e32 v1, 0
692; GCN-NEXT:    s_brev_b32 s0, -2
693; GCN-NEXT:    v_and_b32_e32 v0, s0, v0
694; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
695; GCN-NEXT:    v_and_b32_e32 v2, s0, v2
696; GCN-NEXT:    v_mov_b32_e32 v3, v1
697; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
698; GCN-NEXT:    s_endpgm
699;
700; GCN-IR-LABEL: s_test_urem23_64_v2i64:
701; GCN-IR:       ; %bb.0:
702; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
703; GCN-IR-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
704; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
705; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
706; GCN-IR-NEXT:    s_mov_b32 s6, -1
707; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
708; GCN-IR-NEXT:    s_lshr_b32 s2, s9, 1
709; GCN-IR-NEXT:    s_lshr_b32 s0, s1, 1
710; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
711; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s2
712; GCN-IR-NEXT:    s_lshr_b32 s3, s3, 9
713; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v4, s3
714; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
715; GCN-IR-NEXT:    s_lshr_b32 s1, s11, 9
716; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v3, s1
717; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
718; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
719; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
720; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
721; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v4
722; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
723; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
724; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
725; GCN-IR-NEXT:    v_mul_f32_e32 v2, v3, v2
726; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
727; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
728; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
729; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v4, v3
730; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
731; GCN-IR-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
732; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, s3
733; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
734; GCN-IR-NEXT:    s_brev_b32 s0, -2
735; GCN-IR-NEXT:    v_and_b32_e32 v0, s0, v0
736; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
737; GCN-IR-NEXT:    v_and_b32_e32 v2, s0, v2
738; GCN-IR-NEXT:    v_mov_b32_e32 v3, v1
739; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
740; GCN-IR-NEXT:    s_endpgm
741  %1 = lshr <2 x i64> %x, <i64 33, i64 41>
742  %2 = lshr <2 x i64> %y, <i64 33, i64 41>
743  %result = urem <2 x i64> %1, %2
744  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
745  ret void
746}
747
748define amdgpu_kernel void @s_test_urem_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
749; GCN-LABEL: s_test_urem_k_num_i64:
750; GCN:       ; %bb.0:
751; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
752; GCN-NEXT:    v_mov_b32_e32 v2, 0
753; GCN-NEXT:    s_mov_b32 s11, 0xf000
754; GCN-NEXT:    s_mov_b32 s10, -1
755; GCN-NEXT:    s_waitcnt lgkmcnt(0)
756; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s6
757; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s7
758; GCN-NEXT:    s_sub_u32 s2, 0, s6
759; GCN-NEXT:    s_subb_u32 s3, 0, s7
760; GCN-NEXT:    s_mov_b32 s8, s4
761; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
762; GCN-NEXT:    v_rcp_f32_e32 v0, v0
763; GCN-NEXT:    v_mov_b32_e32 v1, 0
764; GCN-NEXT:    s_mov_b32 s9, s5
765; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
766; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
767; GCN-NEXT:    v_trunc_f32_e32 v3, v3
768; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
769; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
770; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
771; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
772; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
773; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
774; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
775; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
776; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
777; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
778; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
779; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
780; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
781; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
782; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
783; GCN-NEXT:    v_mul_hi_u32 v10, v3, v4
784; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
785; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
786; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
787; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
788; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
789; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
790; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
791; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
792; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
793; GCN-NEXT:    v_mul_lo_u32 v6, s2, v4
794; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
795; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
796; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
797; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
798; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
799; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
800; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
801; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
802; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
803; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
804; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
805; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
806; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
807; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
808; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
809; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
810; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
811; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
812; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
813; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
814; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
815; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
816; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
817; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
818; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
819; GCN-NEXT:    v_mul_hi_u32 v3, v3, 24
820; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
821; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v2, v3, vcc
822; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
823; GCN-NEXT:    v_mul_lo_u32 v1, s6, v1
824; GCN-NEXT:    v_mul_hi_u32 v2, s6, v0
825; GCN-NEXT:    v_mul_lo_u32 v3, s7, v0
826; GCN-NEXT:    v_mul_lo_u32 v0, s6, v0
827; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
828; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
829; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
830; GCN-NEXT:    v_mov_b32_e32 v3, s7
831; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
832; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
833; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s6, v0
834; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
835; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s7, v5
836; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
837; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
838; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s6, v4
839; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s6, v4
840; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
841; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s7, v5
842; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
843; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
844; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
845; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
846; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
847; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
848; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
849; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
850; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
851; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s7, v1
852; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
853; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
854; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
855; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
856; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
857; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
858; GCN-NEXT:    s_endpgm
859;
860; GCN-IR-LABEL: s_test_urem_k_num_i64:
861; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
862; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
863; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
864; GCN-IR-NEXT:    s_flbit_i32_b32 s2, s6
865; GCN-IR-NEXT:    s_flbit_i32_b32 s3, s7
866; GCN-IR-NEXT:    s_add_i32 s2, s2, 32
867; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
868; GCN-IR-NEXT:    v_mov_b32_e32 v1, s2
869; GCN-IR-NEXT:    v_cmp_eq_u32_e64 vcc, s7, 0
870; GCN-IR-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
871; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, 0xffffffc5, v2
872; GCN-IR-NEXT:    v_addc_u32_e64 v1, s[2:3], 0, -1, vcc
873; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[6:7], 0
874; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[0:1]
875; GCN-IR-NEXT:    s_or_b64 s[0:1], s[0:1], vcc
876; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[0:1]
877; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[0:1], -1
878; GCN-IR-NEXT:    s_and_b64 s[2:3], s[2:3], vcc
879; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[2:3]
880; GCN-IR-NEXT:    s_cbranch_vccz BB6_4
881; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
882; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
883; GCN-IR-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
884; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[0:1], v[3:4], v[0:1]
885; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 63, v0
886; GCN-IR-NEXT:    v_lshl_b64 v[0:1], 24, v0
887; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[0:1]
888; GCN-IR-NEXT:    s_cbranch_vccz BB6_5
889; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
890; GCN-IR-NEXT:    s_add_u32 s2, s6, -1
891; GCN-IR-NEXT:    v_lshr_b64 v[6:7], 24, v3
892; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, 58, v2
893; GCN-IR-NEXT:    v_mov_b32_e32 v8, 0
894; GCN-IR-NEXT:    s_addc_u32 s3, s7, -1
895; GCN-IR-NEXT:    v_subb_u32_e64 v5, s[0:1], 0, 0, vcc
896; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
897; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
898; GCN-IR-NEXT:  BB6_3: ; %udiv-do-while
899; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
900; GCN-IR-NEXT:    v_lshl_b64 v[6:7], v[6:7], 1
901; GCN-IR-NEXT:    v_lshrrev_b32_e32 v2, 31, v1
902; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
903; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v2
904; GCN-IR-NEXT:    v_or_b32_e32 v0, v8, v0
905; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
906; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, s2, v6
907; GCN-IR-NEXT:    v_subb_u32_e32 v2, vcc, v2, v7, vcc
908; GCN-IR-NEXT:    v_ashrrev_i32_e32 v8, 31, v2
909; GCN-IR-NEXT:    v_and_b32_e32 v10, s6, v8
910; GCN-IR-NEXT:    v_and_b32_e32 v2, 1, v8
911; GCN-IR-NEXT:    v_and_b32_e32 v11, s7, v8
912; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
913; GCN-IR-NEXT:    v_or_b32_e32 v1, v9, v1
914; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
915; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
916; GCN-IR-NEXT:    v_mov_b32_e32 v4, v8
917; GCN-IR-NEXT:    v_sub_i32_e64 v6, s[0:1], v6, v10
918; GCN-IR-NEXT:    v_mov_b32_e32 v5, v9
919; GCN-IR-NEXT:    v_mov_b32_e32 v9, v3
920; GCN-IR-NEXT:    v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1]
921; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
922; GCN-IR-NEXT:    v_mov_b32_e32 v8, v2
923; GCN-IR-NEXT:    s_cbranch_vccz BB6_3
924; GCN-IR-NEXT:    s_branch BB6_6
925; GCN-IR-NEXT:  BB6_4:
926; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
927; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[0:1]
928; GCN-IR-NEXT:    s_branch BB6_7
929; GCN-IR-NEXT:  BB6_5:
930; GCN-IR-NEXT:    v_mov_b32_e32 v2, 0
931; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
932; GCN-IR-NEXT:  BB6_6: ; %Flow5
933; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
934; GCN-IR-NEXT:    v_or_b32_e32 v0, v2, v0
935; GCN-IR-NEXT:    v_or_b32_e32 v1, v3, v1
936; GCN-IR-NEXT:  BB6_7: ; %udiv-end
937; GCN-IR-NEXT:    v_mul_lo_u32 v1, s6, v1
938; GCN-IR-NEXT:    v_mul_hi_u32 v2, s6, v0
939; GCN-IR-NEXT:    v_mul_lo_u32 v3, s7, v0
940; GCN-IR-NEXT:    v_mul_lo_u32 v0, s6, v0
941; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
942; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
943; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
944; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
945; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
946; GCN-IR-NEXT:    s_mov_b32 s6, -1
947; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
948; GCN-IR-NEXT:    s_endpgm
949  %result = urem i64 24, %x
950  store i64 %result, i64 addrspace(1)* %out
951  ret void
952}
953
954define amdgpu_kernel void @s_test_urem_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
955; GCN-LABEL: s_test_urem_k_den_i64:
956; GCN:       ; %bb.0:
957; GCN-NEXT:    v_mov_b32_e32 v0, 0x4f800000
958; GCN-NEXT:    v_madak_f32 v0, 0, v0, 0x41c00000
959; GCN-NEXT:    v_rcp_f32_e32 v0, v0
960; GCN-NEXT:    s_movk_i32 s2, 0xffe8
961; GCN-NEXT:    v_mov_b32_e32 v8, 0
962; GCN-NEXT:    v_mov_b32_e32 v7, 0
963; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
964; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
965; GCN-NEXT:    v_trunc_f32_e32 v1, v1
966; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
967; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
968; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
969; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
970; GCN-NEXT:    s_mov_b32 s11, 0xf000
971; GCN-NEXT:    v_mul_hi_u32 v2, v0, s2
972; GCN-NEXT:    v_mul_lo_u32 v3, v1, s2
973; GCN-NEXT:    v_mul_lo_u32 v4, v0, s2
974; GCN-NEXT:    s_mov_b32 s10, -1
975; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
976; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
977; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
978; GCN-NEXT:    v_mul_hi_u32 v6, v0, v4
979; GCN-NEXT:    v_mul_hi_u32 v3, v0, v2
980; GCN-NEXT:    v_mul_hi_u32 v9, v1, v2
981; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
982; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
983; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
984; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
985; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v3, vcc
986; GCN-NEXT:    s_waitcnt lgkmcnt(0)
987; GCN-NEXT:    s_mov_b32 s8, s4
988; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
989; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
990; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
991; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
992; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
993; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
994; GCN-NEXT:    v_mul_hi_u32 v4, v0, s2
995; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
996; GCN-NEXT:    v_mul_lo_u32 v5, v2, s2
997; GCN-NEXT:    v_mul_lo_u32 v6, v0, s2
998; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v0, v4
999; GCN-NEXT:    s_mov_b32 s9, s5
1000; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1001; GCN-NEXT:    v_mul_lo_u32 v5, v0, v4
1002; GCN-NEXT:    v_mul_hi_u32 v9, v0, v6
1003; GCN-NEXT:    v_mul_hi_u32 v10, v0, v4
1004; GCN-NEXT:    v_mul_hi_u32 v11, v2, v4
1005; GCN-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
1006; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v8, v10, vcc
1007; GCN-NEXT:    v_mul_lo_u32 v10, v2, v6
1008; GCN-NEXT:    v_mul_hi_u32 v6, v2, v6
1009; GCN-NEXT:    v_mul_lo_u32 v2, v2, v4
1010; GCN-NEXT:    v_add_i32_e32 v5, vcc, v10, v5
1011; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v6, vcc
1012; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v11, v7, vcc
1013; GCN-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
1014; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
1015; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1016; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
1017; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1018; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1019; GCN-NEXT:    v_mul_lo_u32 v2, s6, v1
1020; GCN-NEXT:    v_mul_hi_u32 v3, s6, v0
1021; GCN-NEXT:    v_mul_hi_u32 v4, s6, v1
1022; GCN-NEXT:    v_mul_hi_u32 v5, s7, v1
1023; GCN-NEXT:    v_mul_lo_u32 v1, s7, v1
1024; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1025; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
1026; GCN-NEXT:    v_mul_lo_u32 v4, s7, v0
1027; GCN-NEXT:    v_mul_hi_u32 v0, s7, v0
1028; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
1029; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
1030; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
1031; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1032; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v8, v2, vcc
1033; GCN-NEXT:    v_mul_hi_u32 v2, v0, 24
1034; GCN-NEXT:    v_mul_lo_u32 v1, v1, 24
1035; GCN-NEXT:    v_mul_lo_u32 v0, v0, 24
1036; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1037; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
1038; GCN-NEXT:    v_mov_b32_e32 v2, s7
1039; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1040; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v0
1041; GCN-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v1, vcc
1042; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v2
1043; GCN-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v3, vcc
1044; GCN-NEXT:    v_cmp_lt_u32_e32 vcc, 23, v2
1045; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1046; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
1047; GCN-NEXT:    v_cndmask_b32_e32 v6, -1, v6, vcc
1048; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
1049; GCN-NEXT:    v_cmp_lt_u32_e64 s[0:1], 23, v0
1050; GCN-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
1051; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
1052; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
1053; GCN-NEXT:    v_cndmask_b32_e64 v5, -1, v5, s[0:1]
1054; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v5
1055; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
1056; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
1057; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
1058; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
1059; GCN-NEXT:    s_endpgm
1060;
1061; GCN-IR-LABEL: s_test_urem_k_den_i64:
1062; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1063; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1064; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1065; GCN-IR-NEXT:    s_flbit_i32_b32 s2, s6
1066; GCN-IR-NEXT:    s_flbit_i32_b32 s3, s7
1067; GCN-IR-NEXT:    s_add_i32 s2, s2, 32
1068; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
1069; GCN-IR-NEXT:    v_mov_b32_e32 v1, s2
1070; GCN-IR-NEXT:    v_cmp_eq_u32_e64 vcc, s7, 0
1071; GCN-IR-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
1072; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 59, v2
1073; GCN-IR-NEXT:    v_subb_u32_e64 v1, s[2:3], 0, 0, vcc
1074; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[0:1], s[6:7], 0
1075; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[0:1]
1076; GCN-IR-NEXT:    s_or_b64 s[0:1], s[0:1], vcc
1077; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[0:1]
1078; GCN-IR-NEXT:    s_xor_b64 s[2:3], s[0:1], -1
1079; GCN-IR-NEXT:    s_and_b64 s[2:3], s[2:3], vcc
1080; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[2:3]
1081; GCN-IR-NEXT:    s_cbranch_vccz BB7_4
1082; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1083; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
1084; GCN-IR-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
1085; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[0:1], v[3:4], v[0:1]
1086; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 63, v0
1087; GCN-IR-NEXT:    v_lshl_b64 v[0:1], s[6:7], v0
1088; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[0:1]
1089; GCN-IR-NEXT:    s_cbranch_vccz BB7_5
1090; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1091; GCN-IR-NEXT:    v_lshr_b64 v[6:7], s[6:7], v3
1092; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 0xffffffc4, v2
1093; GCN-IR-NEXT:    v_mov_b32_e32 v8, 0
1094; GCN-IR-NEXT:    v_addc_u32_e64 v5, s[0:1], 0, -1, vcc
1095; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1096; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
1097; GCN-IR-NEXT:  BB7_3: ; %udiv-do-while
1098; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1099; GCN-IR-NEXT:    v_lshl_b64 v[6:7], v[6:7], 1
1100; GCN-IR-NEXT:    v_lshrrev_b32_e32 v2, 31, v1
1101; GCN-IR-NEXT:    v_or_b32_e32 v6, v6, v2
1102; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
1103; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, 23, v6
1104; GCN-IR-NEXT:    v_subb_u32_e32 v2, vcc, 0, v7, vcc
1105; GCN-IR-NEXT:    v_or_b32_e32 v0, v8, v0
1106; GCN-IR-NEXT:    v_ashrrev_i32_e32 v8, 31, v2
1107; GCN-IR-NEXT:    v_and_b32_e32 v10, 24, v8
1108; GCN-IR-NEXT:    v_and_b32_e32 v2, 1, v8
1109; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
1110; GCN-IR-NEXT:    v_or_b32_e32 v1, v9, v1
1111; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
1112; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
1113; GCN-IR-NEXT:    v_mov_b32_e32 v4, v8
1114; GCN-IR-NEXT:    v_sub_i32_e64 v6, s[0:1], v6, v10
1115; GCN-IR-NEXT:    v_mov_b32_e32 v5, v9
1116; GCN-IR-NEXT:    v_mov_b32_e32 v9, v3
1117; GCN-IR-NEXT:    v_subbrev_u32_e64 v7, s[0:1], 0, v7, s[0:1]
1118; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1119; GCN-IR-NEXT:    v_mov_b32_e32 v8, v2
1120; GCN-IR-NEXT:    s_cbranch_vccz BB7_3
1121; GCN-IR-NEXT:    s_branch BB7_6
1122; GCN-IR-NEXT:  BB7_4:
1123; GCN-IR-NEXT:    v_mov_b32_e32 v0, s7
1124; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[0:1]
1125; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1126; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[0:1]
1127; GCN-IR-NEXT:    s_branch BB7_7
1128; GCN-IR-NEXT:  BB7_5:
1129; GCN-IR-NEXT:    v_mov_b32_e32 v2, 0
1130; GCN-IR-NEXT:    v_mov_b32_e32 v3, 0
1131; GCN-IR-NEXT:  BB7_6: ; %Flow5
1132; GCN-IR-NEXT:    v_lshl_b64 v[0:1], v[0:1], 1
1133; GCN-IR-NEXT:    v_or_b32_e32 v0, v2, v0
1134; GCN-IR-NEXT:    v_or_b32_e32 v1, v3, v1
1135; GCN-IR-NEXT:  BB7_7: ; %udiv-end
1136; GCN-IR-NEXT:    v_mul_hi_u32 v2, v0, 24
1137; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, 24
1138; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, 24
1139; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1140; GCN-IR-NEXT:    v_mov_b32_e32 v2, s7
1141; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
1142; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1143; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1144; GCN-IR-NEXT:    s_mov_b32 s6, -1
1145; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1146; GCN-IR-NEXT:    s_endpgm
1147  %result = urem i64 %x, 24
1148  store i64 %result, i64 addrspace(1)* %out
1149  ret void
1150}
1151
1152; FIXME: Constant bus violation
1153; define i64 @v_test_urem_k_num_i64(i64 %x) {
1154;   %result = urem i64 24, %x
1155;   ret i64 %result
1156; }
1157
1158define i64 @v_test_urem_pow2_k_num_i64(i64 %x) {
1159; GCN-LABEL: v_test_urem_pow2_k_num_i64:
1160; GCN:       ; %bb.0:
1161; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1162; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1163; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1164; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1165; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1166; GCN-NEXT:    v_mov_b32_e32 v12, 0
1167; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1168; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1169; GCN-NEXT:    v_mov_b32_e32 v11, 0
1170; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1171; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1172; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1173; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1174; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1175; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1176; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1177; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1178; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1179; GCN-NEXT:    v_mul_lo_u32 v9, v4, v2
1180; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1181; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1182; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
1183; GCN-NEXT:    v_mul_hi_u32 v10, v2, v9
1184; GCN-NEXT:    v_mul_hi_u32 v7, v2, v6
1185; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
1186; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1187; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
1188; GCN-NEXT:    v_mul_lo_u32 v10, v3, v9
1189; GCN-NEXT:    v_mul_hi_u32 v9, v3, v9
1190; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v7, vcc
1191; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
1192; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
1193; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v11, vcc
1194; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1195; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v6
1196; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v8, vcc
1197; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v3, v7, s[4:5]
1198; GCN-NEXT:    v_mul_lo_u32 v8, v4, v6
1199; GCN-NEXT:    v_mul_hi_u32 v9, v4, v2
1200; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1201; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1202; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1203; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
1204; GCN-NEXT:    v_mul_lo_u32 v10, v2, v5
1205; GCN-NEXT:    v_mul_hi_u32 v13, v2, v4
1206; GCN-NEXT:    v_mul_hi_u32 v14, v2, v5
1207; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
1208; GCN-NEXT:    v_mul_lo_u32 v4, v6, v4
1209; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v10
1210; GCN-NEXT:    v_mul_hi_u32 v8, v6, v5
1211; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v12, v14, vcc
1212; GCN-NEXT:    v_mul_lo_u32 v5, v6, v5
1213; GCN-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
1214; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v13, v9, vcc
1215; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v11, vcc
1216; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1217; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
1218; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
1219; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
1220; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1221; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
1222; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1223; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
1224; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1225; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
1226; GCN-NEXT:    s_mov_b32 s4, 0x8000
1227; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1228; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1229; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s4, v2
1230; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1231; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
1232; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1233; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
1234; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1235; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
1236; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1237; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1
1238; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1239; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1240; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1241; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v0
1242; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1243; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1244; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1245; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1246; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1247; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1248; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1249; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
1250; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1251; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1252; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1253; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1254; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1255; GCN-NEXT:    s_setpc_b64 s[30:31]
1256;
1257; GCN-IR-LABEL: v_test_urem_pow2_k_num_i64:
1258; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1259; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1260; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1261; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1262; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1263; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
1264; GCN-IR-NEXT:    v_cndmask_b32_e32 v8, v3, v2, vcc
1265; GCN-IR-NEXT:    s_movk_i32 s6, 0xffd0
1266; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, s6, v8
1267; GCN-IR-NEXT:    v_addc_u32_e64 v3, s[6:7], 0, -1, vcc
1268; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1269; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[2:3]
1270; GCN-IR-NEXT:    s_mov_b32 s8, 0x8000
1271; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1272; GCN-IR-NEXT:    v_mov_b32_e32 v4, s8
1273; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[2:3]
1274; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1275; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v4, 0, s[4:5]
1276; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1277; GCN-IR-NEXT:    s_mov_b32 s9, 0
1278; GCN-IR-NEXT:    v_mov_b32_e32 v5, v9
1279; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1280; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1281; GCN-IR-NEXT:    s_cbranch_execz BB8_6
1282; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1283; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 1, v2
1284; GCN-IR-NEXT:    v_addc_u32_e32 v5, vcc, 0, v3, vcc
1285; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[4:5], v[2:3]
1286; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v2
1287; GCN-IR-NEXT:    v_lshl_b64 v[2:3], s[8:9], v2
1288; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
1289; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1290; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1291; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1292; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
1293; GCN-IR-NEXT:    s_cbranch_execz BB8_5
1294; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1295; GCN-IR-NEXT:    s_mov_b32 s5, 0
1296; GCN-IR-NEXT:    s_mov_b32 s4, 0x8000
1297; GCN-IR-NEXT:    v_lshr_b64 v[10:11], s[4:5], v4
1298; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, -1, v0
1299; GCN-IR-NEXT:    v_addc_u32_e32 v5, vcc, -1, v1, vcc
1300; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, 47, v8
1301; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1302; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, 0, v9, vcc
1303; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1304; GCN-IR-NEXT:  BB8_3: ; %udiv-do-while
1305; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1306; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
1307; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v3
1308; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v6
1309; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1310; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v4, v10
1311; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v5, v11, vcc
1312; GCN-IR-NEXT:    v_or_b32_e32 v2, v12, v2
1313; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v6
1314; GCN-IR-NEXT:    v_and_b32_e32 v15, v12, v0
1315; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v12
1316; GCN-IR-NEXT:    v_and_b32_e32 v14, v12, v1
1317; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
1318; GCN-IR-NEXT:    v_or_b32_e32 v3, v13, v3
1319; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
1320; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
1321; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1322; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1323; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v15
1324; GCN-IR-NEXT:    v_mov_b32_e32 v9, v13
1325; GCN-IR-NEXT:    v_mov_b32_e32 v13, v7
1326; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v14, s[4:5]
1327; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
1328; GCN-IR-NEXT:    v_mov_b32_e32 v12, v6
1329; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
1330; GCN-IR-NEXT:    s_cbranch_execnz BB8_3
1331; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1332; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1333; GCN-IR-NEXT:  BB8_5: ; %Flow3
1334; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1335; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1336; GCN-IR-NEXT:    v_or_b32_e32 v5, v7, v3
1337; GCN-IR-NEXT:    v_or_b32_e32 v4, v6, v2
1338; GCN-IR-NEXT:  BB8_6: ; %Flow4
1339; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1340; GCN-IR-NEXT:    v_mul_lo_u32 v2, v0, v5
1341; GCN-IR-NEXT:    v_mul_hi_u32 v3, v0, v4
1342; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v4
1343; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v4
1344; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1345; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1346; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1347; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1348; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1349  %result = urem i64 32768, %x
1350  ret i64 %result
1351}
1352
1353define i64 @v_test_urem_pow2_k_den_i64(i64 %x) {
1354; GCN-LABEL: v_test_urem_pow2_k_den_i64:
1355; GCN:       ; %bb.0:
1356; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1357; GCN-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
1358; GCN-NEXT:    v_mov_b32_e32 v1, 0
1359; GCN-NEXT:    s_setpc_b64 s[30:31]
1360;
1361; GCN-IR-LABEL: v_test_urem_pow2_k_den_i64:
1362; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1363; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1364; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1365; GCN-IR-NEXT:    v_add_i32_e64 v2, s[4:5], 32, v2
1366; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1367; GCN-IR-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v1
1368; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v3, v2, s[4:5]
1369; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 48, v6
1370; GCN-IR-NEXT:    v_subb_u32_e64 v3, s[4:5], 0, 0, s[4:5]
1371; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1372; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[2:3]
1373; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1374; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[2:3]
1375; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1376; GCN-IR-NEXT:    v_cndmask_b32_e64 v5, v1, 0, s[4:5]
1377; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v0, 0, s[4:5]
1378; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1379; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1380; GCN-IR-NEXT:    s_cbranch_execz BB9_6
1381; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1382; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 1, v2
1383; GCN-IR-NEXT:    v_addc_u32_e32 v8, vcc, 0, v3, vcc
1384; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[7:8], v[2:3]
1385; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v2
1386; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1387; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[0:1], v2
1388; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1389; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1390; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1391; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
1392; GCN-IR-NEXT:    s_cbranch_execz BB9_5
1393; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1394; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1395; GCN-IR-NEXT:    v_lshr_b64 v[8:9], v[0:1], v7
1396; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 0xffffffcf, v6
1397; GCN-IR-NEXT:    v_addc_u32_e64 v7, s[4:5], 0, -1, vcc
1398; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1399; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1400; GCN-IR-NEXT:  BB9_3: ; %udiv-do-while
1401; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1402; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1403; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1404; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1405; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1406; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, s12, v8
1407; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, 0, v9, vcc
1408; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1409; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1410; GCN-IR-NEXT:    v_and_b32_e32 v12, 0x8000, v10
1411; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1412; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v6
1413; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1414; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v7, vcc
1415; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7]
1416; GCN-IR-NEXT:    v_mov_b32_e32 v6, v10
1417; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1418; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1419; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1420; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1421; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v12
1422; GCN-IR-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v13, s[4:5]
1423; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
1424; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1425; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
1426; GCN-IR-NEXT:    s_cbranch_execnz BB9_3
1427; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1428; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1429; GCN-IR-NEXT:  BB9_5: ; %Flow3
1430; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1431; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1432; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1433; GCN-IR-NEXT:    v_or_b32_e32 v4, v4, v2
1434; GCN-IR-NEXT:  BB9_6: ; %Flow4
1435; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1436; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[4:5], 15
1437; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1438; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1439; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1440  %result = urem i64 %x, 32768
1441  ret i64 %result
1442}
1443
1444define amdgpu_kernel void @s_test_urem24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1445; GCN-LABEL: s_test_urem24_k_num_i64:
1446; GCN:       ; %bb.0:
1447; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1448; GCN-NEXT:    s_mov_b32 s5, 0x41c00000
1449; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1450; GCN-NEXT:    s_mov_b32 s2, -1
1451; GCN-NEXT:    s_lshr_b32 s4, s3, 8
1452; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
1453; GCN-NEXT:    s_mov_b32 s3, 0xf000
1454; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1455; GCN-NEXT:    v_mul_f32_e32 v1, s5, v1
1456; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1457; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1458; GCN-NEXT:    v_mad_f32 v1, -v1, v0, s5
1459; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1460; GCN-NEXT:    v_mov_b32_e32 v1, 0
1461; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1462; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
1463; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1464; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1465; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1466; GCN-NEXT:    s_endpgm
1467;
1468; GCN-IR-LABEL: s_test_urem24_k_num_i64:
1469; GCN-IR:       ; %bb.0:
1470; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1471; GCN-IR-NEXT:    s_mov_b32 s5, 0x41c00000
1472; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1473; GCN-IR-NEXT:    s_mov_b32 s2, -1
1474; GCN-IR-NEXT:    s_lshr_b32 s4, s3, 8
1475; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
1476; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1477; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1478; GCN-IR-NEXT:    v_mul_f32_e32 v1, s5, v1
1479; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1480; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1481; GCN-IR-NEXT:    v_mad_f32 v1, -v1, v0, s5
1482; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1483; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1484; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1485; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
1486; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1487; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1488; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1489; GCN-IR-NEXT:    s_endpgm
1490  %x.shr = lshr i64 %x, 40
1491  %result = urem i64 24, %x.shr
1492  store i64 %result, i64 addrspace(1)* %out
1493  ret void
1494}
1495
1496define amdgpu_kernel void @s_test_urem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1497; GCN-LABEL: s_test_urem24_k_den_i64:
1498; GCN:       ; %bb.0:
1499; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1500; GCN-NEXT:    s_mov_b32 s1, 0x46b6fe00
1501; GCN-NEXT:    s_movk_i32 s0, 0x5b7f
1502; GCN-NEXT:    s_mov_b32 s3, 0xf000
1503; GCN-NEXT:    s_mov_b32 s2, -1
1504; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1505; GCN-NEXT:    s_lshr_b32 s6, s7, 8
1506; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s6
1507; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1508; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1509; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1510; GCN-NEXT:    v_mad_f32 v0, -v1, s1, v0
1511; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s1
1512; GCN-NEXT:    s_mov_b32 s1, s5
1513; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1514; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
1515; GCN-NEXT:    s_mov_b32 s0, s4
1516; GCN-NEXT:    v_mov_b32_e32 v1, 0
1517; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
1518; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1519; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1520; GCN-NEXT:    s_endpgm
1521;
1522; GCN-IR-LABEL: s_test_urem24_k_den_i64:
1523; GCN-IR:       ; %bb.0:
1524; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1525; GCN-IR-NEXT:    s_mov_b32 s1, 0x46b6fe00
1526; GCN-IR-NEXT:    s_movk_i32 s0, 0x5b7f
1527; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1528; GCN-IR-NEXT:    s_mov_b32 s2, -1
1529; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1530; GCN-IR-NEXT:    s_lshr_b32 s6, s7, 8
1531; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s6
1532; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1533; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1534; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1535; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s1, v0
1536; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s1
1537; GCN-IR-NEXT:    s_mov_b32 s1, s5
1538; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1539; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
1540; GCN-IR-NEXT:    s_mov_b32 s0, s4
1541; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1542; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
1543; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1544; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1545; GCN-IR-NEXT:    s_endpgm
1546  %x.shr = lshr i64 %x, 40
1547  %result = urem i64 %x.shr, 23423
1548  store i64 %result, i64 addrspace(1)* %out
1549  ret void
1550}
1551
1552define i64 @v_test_urem24_k_num_i64(i64 %x) {
1553; GCN-LABEL: v_test_urem24_k_num_i64:
1554; GCN:       ; %bb.0:
1555; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1556; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1557; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v0
1558; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
1559; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1560; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
1561; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1562; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
1563; GCN-NEXT:    v_mad_f32 v2, -v2, v1, s4
1564; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1565; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1566; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
1567; GCN-NEXT:    v_mov_b32_e32 v1, 0
1568; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1569; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1570; GCN-NEXT:    s_setpc_b64 s[30:31]
1571;
1572; GCN-IR-LABEL: v_test_urem24_k_num_i64:
1573; GCN-IR:       ; %bb.0:
1574; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1575; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1576; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, v0
1577; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
1578; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1579; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
1580; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1581; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
1582; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v1, s4
1583; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1584; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1585; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
1586; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1587; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1588; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1589; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1590  %x.shr = lshr i64 %x, 40
1591  %result = urem i64 24, %x.shr
1592  ret i64 %result
1593}
1594
1595define i64 @v_test_urem24_pow2_k_num_i64(i64 %x) {
1596; GCN-LABEL: v_test_urem24_pow2_k_num_i64:
1597; GCN:       ; %bb.0:
1598; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1599; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1600; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v0
1601; GCN-NEXT:    s_mov_b32 s4, 0x47000000
1602; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1603; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
1604; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1605; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
1606; GCN-NEXT:    v_mad_f32 v2, -v2, v1, s4
1607; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1608; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1609; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
1610; GCN-NEXT:    v_mov_b32_e32 v1, 0
1611; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1612; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1613; GCN-NEXT:    s_setpc_b64 s[30:31]
1614;
1615; GCN-IR-LABEL: v_test_urem24_pow2_k_num_i64:
1616; GCN-IR:       ; %bb.0:
1617; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1618; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1619; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, v0
1620; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
1621; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1622; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
1623; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1624; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
1625; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v1, s4
1626; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1627; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1628; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
1629; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1630; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1631; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1632; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1633  %x.shr = lshr i64 %x, 40
1634  %result = urem i64 32768, %x.shr
1635  ret i64 %result
1636}
1637
1638define i64 @v_test_urem24_pow2_k_den_i64(i64 %x) {
1639; GCN-LABEL: v_test_urem24_pow2_k_den_i64:
1640; GCN:       ; %bb.0:
1641; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1642; GCN-NEXT:    v_bfe_u32 v0, v1, 8, 15
1643; GCN-NEXT:    v_mov_b32_e32 v1, 0
1644; GCN-NEXT:    s_setpc_b64 s[30:31]
1645;
1646; GCN-IR-LABEL: v_test_urem24_pow2_k_den_i64:
1647; GCN-IR:       ; %bb.0:
1648; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1649; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1650; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, v0
1651; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
1652; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38000000, v1
1653; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1654; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
1655; GCN-IR-NEXT:    v_mad_f32 v1, -v2, s4, v1
1656; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
1657; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1658; GCN-IR-NEXT:    v_lshlrev_b32_e32 v1, 15, v1
1659; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
1660; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1661; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1662; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1663  %x.shr = lshr i64 %x, 40
1664  %result = urem i64 %x.shr, 32768
1665  ret i64 %result
1666}
1667