1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_urem_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_urem_i64:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
9; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
10; GCN-NEXT:    s_mov_b32 s7, 0xf000
11; GCN-NEXT:    s_mov_b32 s6, -1
12; GCN-NEXT:    s_waitcnt lgkmcnt(0)
13; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
14; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
15; GCN-NEXT:    s_sub_u32 s0, 0, s12
16; GCN-NEXT:    s_subb_u32 s1, 0, s13
17; GCN-NEXT:    s_mov_b32 s4, s8
18; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
19; GCN-NEXT:    v_rcp_f32_e32 v0, v0
20; GCN-NEXT:    v_mov_b32_e32 v1, 0
21; GCN-NEXT:    s_mov_b32 s5, s9
22; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
23; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
24; GCN-NEXT:    v_trunc_f32_e32 v2, v2
25; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
26; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
27; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
28; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
29; GCN-NEXT:    v_mul_hi_u32 v4, s0, v0
30; GCN-NEXT:    v_mul_lo_u32 v6, s1, v0
31; GCN-NEXT:    v_mul_lo_u32 v5, s0, v0
32; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
33; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
34; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
35; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
36; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
37; GCN-NEXT:    v_mul_lo_u32 v7, v2, v5
38; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
39; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
40; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
41; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
42; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
43; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
44; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
45; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
46; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
47; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
48; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
49; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
50; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
51; GCN-NEXT:    v_mul_hi_u32 v4, s0, v0
52; GCN-NEXT:    v_mul_lo_u32 v5, s1, v0
53; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
54; GCN-NEXT:    v_mul_lo_u32 v4, s0, v0
55; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
56; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
57; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
58; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
59; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
60; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
61; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
62; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
63; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
64; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
65; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
66; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
67; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v1, vcc
68; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
69; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
70; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
71; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
72; GCN-NEXT:    v_mul_lo_u32 v3, s10, v2
73; GCN-NEXT:    v_mul_hi_u32 v4, s10, v0
74; GCN-NEXT:    v_mul_hi_u32 v5, s10, v2
75; GCN-NEXT:    v_mul_hi_u32 v6, s11, v2
76; GCN-NEXT:    v_mul_lo_u32 v2, s11, v2
77; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
78; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
79; GCN-NEXT:    v_mul_lo_u32 v5, s11, v0
80; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
81; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
82; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
83; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
84; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
85; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
86; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
87; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
88; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
89; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
90; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
91; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
92; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
93; GCN-NEXT:    v_mov_b32_e32 v3, s13
94; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s10, v0
95; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
96; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
97; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
98; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
99; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
100; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
101; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
102; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
103; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
104; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
105; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
106; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
107; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
108; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
109; GCN-NEXT:    v_mov_b32_e32 v5, s11
110; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
111; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
112; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
113; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
114; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
115; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
116; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
117; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
118; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
119; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
120; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
121; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
122; GCN-NEXT:    s_endpgm
123;
124; GCN-IR-LABEL: s_test_urem_i64:
125; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
126; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
127; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
128; GCN-IR-NEXT:    s_mov_b64 s[6:7], 0
129; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
130; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[4:5], 0
131; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
132; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s4
133; GCN-IR-NEXT:    s_or_b64 s[14:15], s[8:9], s[10:11]
134; GCN-IR-NEXT:    s_flbit_i32_b32 s10, s2
135; GCN-IR-NEXT:    s_add_i32 s12, s12, 32
136; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s5
137; GCN-IR-NEXT:    s_add_i32 s10, s10, 32
138; GCN-IR-NEXT:    s_flbit_i32_b32 s11, s3
139; GCN-IR-NEXT:    s_min_u32 s8, s12, s8
140; GCN-IR-NEXT:    s_min_u32 s12, s10, s11
141; GCN-IR-NEXT:    s_sub_u32 s10, s8, s12
142; GCN-IR-NEXT:    s_subb_u32 s11, 0, 0
143; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[16:17], s[10:11], 63
144; GCN-IR-NEXT:    s_mov_b32 s9, 0
145; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[16:17]
146; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[16:17], s[10:11], 63
147; GCN-IR-NEXT:    s_xor_b64 s[18:19], s[14:15], -1
148; GCN-IR-NEXT:    s_and_b64 s[16:17], s[18:19], s[16:17]
149; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
150; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_5
151; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
152; GCN-IR-NEXT:    s_add_u32 s14, s10, 1
153; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
154; GCN-IR-NEXT:    s_addc_u32 s15, s11, 0
155; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
156; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1]
157; GCN-IR-NEXT:    s_sub_i32 s10, 63, s10
158; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
159; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[2:3], s10
160; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_4
161; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
162; GCN-IR-NEXT:    s_lshr_b64 s[14:15], s[2:3], s14
163; GCN-IR-NEXT:    s_add_u32 s16, s4, -1
164; GCN-IR-NEXT:    s_addc_u32 s17, s5, -1
165; GCN-IR-NEXT:    s_not_b64 s[6:7], s[8:9]
166; GCN-IR-NEXT:    s_mov_b32 s13, s9
167; GCN-IR-NEXT:    s_add_u32 s8, s6, s12
168; GCN-IR-NEXT:    s_addc_u32 s9, s7, s9
169; GCN-IR-NEXT:    s_mov_b64 s[12:13], 0
170; GCN-IR-NEXT:    s_mov_b32 s7, 0
171; GCN-IR-NEXT:  .LBB0_3: ; %udiv-do-while
172; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
173; GCN-IR-NEXT:    s_lshl_b64 s[14:15], s[14:15], 1
174; GCN-IR-NEXT:    s_lshr_b32 s6, s11, 31
175; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
176; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[6:7]
177; GCN-IR-NEXT:    s_or_b64 s[10:11], s[12:13], s[10:11]
178; GCN-IR-NEXT:    s_sub_u32 s6, s16, s14
179; GCN-IR-NEXT:    s_subb_u32 s6, s17, s15
180; GCN-IR-NEXT:    s_ashr_i32 s12, s6, 31
181; GCN-IR-NEXT:    s_mov_b32 s13, s12
182; GCN-IR-NEXT:    s_and_b32 s6, s12, 1
183; GCN-IR-NEXT:    s_and_b64 s[18:19], s[12:13], s[4:5]
184; GCN-IR-NEXT:    s_sub_u32 s14, s14, s18
185; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
186; GCN-IR-NEXT:    s_subb_u32 s15, s15, s19
187; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
188; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
189; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
190; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
191; GCN-IR-NEXT:    s_mov_b64 s[12:13], s[6:7]
192; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
193; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_3
194; GCN-IR-NEXT:  .LBB0_4: ; %Flow6
195; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[10:11], 1
196; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
197; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
198; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
199; GCN-IR-NEXT:    s_branch .LBB0_6
200; GCN-IR-NEXT:  .LBB0_5:
201; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
202; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[14:15]
203; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
204; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[14:15]
205; GCN-IR-NEXT:  .LBB0_6: ; %udiv-end
206; GCN-IR-NEXT:    v_mul_lo_u32 v1, s4, v1
207; GCN-IR-NEXT:    v_mul_hi_u32 v2, s4, v0
208; GCN-IR-NEXT:    v_mul_lo_u32 v3, s5, v0
209; GCN-IR-NEXT:    v_mul_lo_u32 v0, s4, v0
210; GCN-IR-NEXT:    s_mov_b32 s11, 0xf000
211; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
212; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
213; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
214; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
215; GCN-IR-NEXT:    s_mov_b32 s10, -1
216; GCN-IR-NEXT:    s_mov_b32 s8, s0
217; GCN-IR-NEXT:    s_mov_b32 s9, s1
218; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
219; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
220; GCN-IR-NEXT:    s_endpgm
221  %result = urem i64 %x, %y
222  store i64 %result, i64 addrspace(1)* %out
223  ret void
224}
225
226define i64 @v_test_urem_i64(i64 %x, i64 %y) {
227; GCN-LABEL: v_test_urem_i64:
228; GCN:       ; %bb.0:
229; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
230; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
231; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v3
232; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v2
233; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v3, vcc
234; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
235; GCN-NEXT:    v_rcp_f32_e32 v4, v4
236; GCN-NEXT:    v_mov_b32_e32 v13, 0
237; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
238; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
239; GCN-NEXT:    v_trunc_f32_e32 v5, v5
240; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
241; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
242; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
243; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
244; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
245; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
246; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
247; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
248; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
249; GCN-NEXT:    v_mul_lo_u32 v10, v4, v8
250; GCN-NEXT:    v_mul_hi_u32 v11, v4, v9
251; GCN-NEXT:    v_mul_hi_u32 v12, v4, v8
252; GCN-NEXT:    v_mul_hi_u32 v14, v5, v8
253; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
254; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
255; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
256; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
257; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
258; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
259; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v9, vcc
260; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v13, vcc
261; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
262; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
263; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
264; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v9, vcc
265; GCN-NEXT:    v_mul_lo_u32 v8, v6, v5
266; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
267; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
268; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
269; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
270; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
271; GCN-NEXT:    v_mul_lo_u32 v10, v4, v7
272; GCN-NEXT:    v_mul_hi_u32 v11, v4, v6
273; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
274; GCN-NEXT:    v_mul_hi_u32 v9, v5, v6
275; GCN-NEXT:    v_mul_lo_u32 v6, v5, v6
276; GCN-NEXT:    v_mul_hi_u32 v8, v5, v7
277; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
278; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
279; GCN-NEXT:    v_mul_lo_u32 v7, v5, v7
280; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
281; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
282; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v8, v13, vcc
283; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
284; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
285; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
286; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
287; GCN-NEXT:    v_mul_lo_u32 v6, v0, v5
288; GCN-NEXT:    v_mul_hi_u32 v7, v0, v4
289; GCN-NEXT:    v_mul_hi_u32 v8, v0, v5
290; GCN-NEXT:    v_mul_hi_u32 v9, v1, v5
291; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
292; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
293; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
294; GCN-NEXT:    v_mul_lo_u32 v8, v1, v4
295; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
296; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
297; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v4, vcc
298; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v13, vcc
299; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
300; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
301; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
302; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
303; GCN-NEXT:    v_mul_lo_u32 v7, v3, v4
304; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
305; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
306; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
307; GCN-NEXT:    v_sub_i32_e32 v6, vcc, v1, v5
308; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
309; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v6, v3, vcc
310; GCN-NEXT:    v_sub_i32_e64 v6, s[4:5], v0, v2
311; GCN-NEXT:    v_subbrev_u32_e64 v7, s[6:7], 0, v4, s[4:5]
312; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v7, v3
313; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
314; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v2
315; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
316; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[6:7]
317; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v7, v3
318; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v3, s[4:5]
319; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
320; GCN-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[6:7]
321; GCN-NEXT:    v_sub_i32_e64 v9, s[4:5], v6, v2
322; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
323; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
324; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
325; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
326; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
327; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v8
328; GCN-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
329; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v9, s[4:5]
330; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
331; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v4, s[4:5]
332; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
333; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
334; GCN-NEXT:    s_setpc_b64 s[30:31]
335;
336; GCN-IR-LABEL: v_test_urem_i64:
337; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
338; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
339; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[2:3]
340; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
341; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v2
342; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
343; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
344; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v3
345; GCN-IR-NEXT:    v_min_u32_e32 v8, v4, v5
346; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
347; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
348; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
349; GCN-IR-NEXT:    v_min_u32_e32 v10, v4, v5
350; GCN-IR-NEXT:    v_sub_i32_e32 v5, vcc, v8, v10
351; GCN-IR-NEXT:    v_subb_u32_e64 v6, s[6:7], 0, 0, vcc
352; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[5:6]
353; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
354; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
355; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[5:6]
356; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
357; GCN-IR-NEXT:    v_mov_b32_e32 v11, v9
358; GCN-IR-NEXT:    v_cndmask_b32_e64 v7, v1, 0, s[4:5]
359; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v0, 0, s[4:5]
360; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
361; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
362; GCN-IR-NEXT:    s_cbranch_execz .LBB1_6
363; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
364; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v5
365; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v6, vcc
366; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v5
367; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[12:13], v[5:6]
368; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[0:1], v4
369; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
370; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
371; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
372; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
373; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
374; GCN-IR-NEXT:    s_cbranch_execz .LBB1_5
375; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
376; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, -1, v2
377; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, -1, v3, vcc
378; GCN-IR-NEXT:    v_not_b32_e32 v7, v8
379; GCN-IR-NEXT:    v_not_b32_e32 v6, v9
380; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, v7, v10
381; GCN-IR-NEXT:    v_lshr_b64 v[12:13], v[0:1], v12
382; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, v6, v11, vcc
383; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
384; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
385; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
386; GCN-IR-NEXT:  .LBB1_3: ; %udiv-do-while
387; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
388; GCN-IR-NEXT:    v_lshl_b64 v[12:13], v[12:13], 1
389; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
390; GCN-IR-NEXT:    v_or_b32_e32 v12, v12, v6
391; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
392; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v14, v12
393; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v15, v13, vcc
394; GCN-IR-NEXT:    v_or_b32_e32 v4, v10, v4
395; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v6
396; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v10
397; GCN-IR-NEXT:    v_and_b32_e32 v16, v10, v3
398; GCN-IR-NEXT:    v_and_b32_e32 v17, v10, v2
399; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v8
400; GCN-IR-NEXT:    v_or_b32_e32 v5, v11, v5
401; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v9, vcc
402; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[10:11], v[8:9]
403; GCN-IR-NEXT:    v_mov_b32_e32 v8, v10
404; GCN-IR-NEXT:    v_sub_i32_e64 v12, s[4:5], v12, v17
405; GCN-IR-NEXT:    v_mov_b32_e32 v9, v11
406; GCN-IR-NEXT:    v_mov_b32_e32 v11, v7
407; GCN-IR-NEXT:    v_subb_u32_e64 v13, s[4:5], v13, v16, s[4:5]
408; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
409; GCN-IR-NEXT:    v_mov_b32_e32 v10, v6
410; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
411; GCN-IR-NEXT:    s_cbranch_execnz .LBB1_3
412; GCN-IR-NEXT:  ; %bb.4: ; %Flow
413; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
414; GCN-IR-NEXT:  .LBB1_5: ; %Flow3
415; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
416; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
417; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v5
418; GCN-IR-NEXT:    v_or_b32_e32 v4, v6, v4
419; GCN-IR-NEXT:  .LBB1_6: ; %Flow4
420; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
421; GCN-IR-NEXT:    v_mul_lo_u32 v5, v2, v7
422; GCN-IR-NEXT:    v_mul_hi_u32 v6, v2, v4
423; GCN-IR-NEXT:    v_mul_lo_u32 v3, v3, v4
424; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, v4
425; GCN-IR-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
426; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
427; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
428; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
429; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
430  %result = urem i64 %x, %y
431  ret i64 %result
432}
433
434define amdgpu_kernel void @s_test_urem31_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
435; GCN-LABEL: s_test_urem31_i64:
436; GCN:       ; %bb.0:
437; GCN-NEXT:    s_load_dword s4, s[0:1], 0xe
438; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
439; GCN-NEXT:    s_waitcnt lgkmcnt(0)
440; GCN-NEXT:    s_mov_b32 s2, -1
441; GCN-NEXT:    s_lshr_b32 s4, s4, 1
442; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
443; GCN-NEXT:    s_lshr_b32 s5, s3, 1
444; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s5
445; GCN-NEXT:    s_mov_b32 s3, 0xf000
446; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
447; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
448; GCN-NEXT:    v_trunc_f32_e32 v2, v2
449; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
450; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
451; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
452; GCN-NEXT:    v_mov_b32_e32 v1, 0
453; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
454; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
455; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
456; GCN-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
457; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
458; GCN-NEXT:    s_endpgm
459;
460; GCN-IR-LABEL: s_test_urem31_i64:
461; GCN-IR:       ; %bb.0:
462; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xe
463; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
464; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
465; GCN-IR-NEXT:    s_mov_b32 s2, -1
466; GCN-IR-NEXT:    s_lshr_b32 s4, s4, 1
467; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
468; GCN-IR-NEXT:    s_lshr_b32 s5, s3, 1
469; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s5
470; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
471; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
472; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
473; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
474; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
475; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
476; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
477; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
478; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
479; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
480; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
481; GCN-IR-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
482; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
483; GCN-IR-NEXT:    s_endpgm
484  %1 = lshr i64 %x, 33
485  %2 = lshr i64 %y, 33
486  %result = urem i64 %1, %2
487  store i64 %result, i64 addrspace(1)* %out
488  ret void
489}
490
491define amdgpu_kernel void @s_test_urem31_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
492; GCN-LABEL: s_test_urem31_v2i64:
493; GCN:       ; %bb.0:
494; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x11
495; GCN-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x9
496; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
497; GCN-NEXT:    s_mov_b32 s11, 0xf000
498; GCN-NEXT:    s_mov_b32 s10, -1
499; GCN-NEXT:    s_waitcnt lgkmcnt(0)
500; GCN-NEXT:    s_lshr_b32 s0, s5, 1
501; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
502; GCN-NEXT:    s_lshr_b32 s1, s1, 1
503; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s1
504; GCN-NEXT:    s_lshr_b32 s2, s3, 1
505; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
506; GCN-NEXT:    s_lshr_b32 s3, s7, 1
507; GCN-NEXT:    v_cvt_f32_u32_e32 v4, s3
508; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s2
509; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
510; GCN-NEXT:    v_trunc_f32_e32 v2, v2
511; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
512; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
513; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v4
514; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
515; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
516; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
517; GCN-NEXT:    v_mul_f32_e32 v2, v3, v2
518; GCN-NEXT:    v_trunc_f32_e32 v2, v2
519; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
520; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s1, v0
521; GCN-NEXT:    v_mad_f32 v2, -v2, v4, v3
522; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
523; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
524; GCN-NEXT:    v_mul_lo_u32 v2, v2, s3
525; GCN-NEXT:    v_mov_b32_e32 v1, 0
526; GCN-NEXT:    s_brev_b32 s0, -2
527; GCN-NEXT:    v_and_b32_e32 v0, s0, v0
528; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s2, v2
529; GCN-NEXT:    v_and_b32_e32 v2, s0, v2
530; GCN-NEXT:    v_mov_b32_e32 v3, v1
531; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
532; GCN-NEXT:    s_endpgm
533;
534; GCN-IR-LABEL: s_test_urem31_v2i64:
535; GCN-IR:       ; %bb.0:
536; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x11
537; GCN-IR-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x9
538; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
539; GCN-IR-NEXT:    s_mov_b32 s11, 0xf000
540; GCN-IR-NEXT:    s_mov_b32 s10, -1
541; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
542; GCN-IR-NEXT:    s_lshr_b32 s0, s5, 1
543; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
544; GCN-IR-NEXT:    s_lshr_b32 s1, s1, 1
545; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s1
546; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 1
547; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
548; GCN-IR-NEXT:    s_lshr_b32 s3, s7, 1
549; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v4, s3
550; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v3, s2
551; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
552; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
553; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
554; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
555; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v4
556; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
557; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
558; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
559; GCN-IR-NEXT:    v_mul_f32_e32 v2, v3, v2
560; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
561; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
562; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s1, v0
563; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v4, v3
564; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
565; GCN-IR-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
566; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, s3
567; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
568; GCN-IR-NEXT:    s_brev_b32 s0, -2
569; GCN-IR-NEXT:    v_and_b32_e32 v0, s0, v0
570; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, s2, v2
571; GCN-IR-NEXT:    v_and_b32_e32 v2, s0, v2
572; GCN-IR-NEXT:    v_mov_b32_e32 v3, v1
573; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
574; GCN-IR-NEXT:    s_endpgm
575  %1 = lshr <2 x i64> %x, <i64 33, i64 33>
576  %2 = lshr <2 x i64> %y, <i64 33, i64 33>
577  %result = urem <2 x i64> %1, %2
578  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
579  ret void
580}
581
582define amdgpu_kernel void @s_test_urem24_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
583; GCN-LABEL: s_test_urem24_i64:
584; GCN:       ; %bb.0:
585; GCN-NEXT:    s_load_dword s4, s[0:1], 0xe
586; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
587; GCN-NEXT:    s_waitcnt lgkmcnt(0)
588; GCN-NEXT:    s_mov_b32 s2, -1
589; GCN-NEXT:    s_lshr_b32 s4, s4, 8
590; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
591; GCN-NEXT:    s_lshr_b32 s5, s3, 8
592; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s5
593; GCN-NEXT:    s_mov_b32 s3, 0xf000
594; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
595; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
596; GCN-NEXT:    v_trunc_f32_e32 v2, v2
597; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
598; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
599; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
600; GCN-NEXT:    v_mov_b32_e32 v1, 0
601; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
602; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
603; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
604; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
605; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
606; GCN-NEXT:    s_endpgm
607;
608; GCN-IR-LABEL: s_test_urem24_i64:
609; GCN-IR:       ; %bb.0:
610; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xe
611; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
612; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
613; GCN-IR-NEXT:    s_mov_b32 s2, -1
614; GCN-IR-NEXT:    s_lshr_b32 s4, s4, 8
615; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
616; GCN-IR-NEXT:    s_lshr_b32 s5, s3, 8
617; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s5
618; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
619; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
620; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
621; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
622; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
623; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
624; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
625; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
626; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
627; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
628; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
629; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
630; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
631; GCN-IR-NEXT:    s_endpgm
632  %1 = lshr i64 %x, 40
633  %2 = lshr i64 %y, 40
634  %result = urem i64 %1, %2
635  store i64 %result, i64 addrspace(1)* %out
636  ret void
637}
638
639define amdgpu_kernel void @s_test_urem23_64_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
640; GCN-LABEL: s_test_urem23_64_v2i64:
641; GCN:       ; %bb.0:
642; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x11
643; GCN-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x9
644; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
645; GCN-NEXT:    s_mov_b32 s11, 0xf000
646; GCN-NEXT:    s_mov_b32 s10, -1
647; GCN-NEXT:    s_waitcnt lgkmcnt(0)
648; GCN-NEXT:    s_lshr_b32 s0, s5, 1
649; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
650; GCN-NEXT:    s_lshr_b32 s1, s1, 1
651; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s1
652; GCN-NEXT:    s_lshr_b32 s2, s3, 9
653; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
654; GCN-NEXT:    s_lshr_b32 s3, s7, 9
655; GCN-NEXT:    v_cvt_f32_u32_e32 v4, s3
656; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s2
657; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
658; GCN-NEXT:    v_trunc_f32_e32 v2, v2
659; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
660; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
661; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v4
662; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
663; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
664; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
665; GCN-NEXT:    v_mul_f32_e32 v2, v3, v2
666; GCN-NEXT:    v_trunc_f32_e32 v2, v2
667; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
668; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s1, v0
669; GCN-NEXT:    v_mad_f32 v2, -v2, v4, v3
670; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
671; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
672; GCN-NEXT:    v_mul_lo_u32 v2, v2, s3
673; GCN-NEXT:    v_mov_b32_e32 v1, 0
674; GCN-NEXT:    s_brev_b32 s0, -2
675; GCN-NEXT:    v_and_b32_e32 v0, s0, v0
676; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s2, v2
677; GCN-NEXT:    v_and_b32_e32 v2, s0, v2
678; GCN-NEXT:    v_mov_b32_e32 v3, v1
679; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
680; GCN-NEXT:    s_endpgm
681;
682; GCN-IR-LABEL: s_test_urem23_64_v2i64:
683; GCN-IR:       ; %bb.0:
684; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x11
685; GCN-IR-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x9
686; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
687; GCN-IR-NEXT:    s_mov_b32 s11, 0xf000
688; GCN-IR-NEXT:    s_mov_b32 s10, -1
689; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
690; GCN-IR-NEXT:    s_lshr_b32 s0, s5, 1
691; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
692; GCN-IR-NEXT:    s_lshr_b32 s1, s1, 1
693; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s1
694; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 9
695; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
696; GCN-IR-NEXT:    s_lshr_b32 s3, s7, 9
697; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v4, s3
698; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v3, s2
699; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
700; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
701; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
702; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
703; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v4
704; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
705; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
706; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
707; GCN-IR-NEXT:    v_mul_f32_e32 v2, v3, v2
708; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
709; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
710; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s1, v0
711; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v4, v3
712; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
713; GCN-IR-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
714; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, s3
715; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
716; GCN-IR-NEXT:    s_brev_b32 s0, -2
717; GCN-IR-NEXT:    v_and_b32_e32 v0, s0, v0
718; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, s2, v2
719; GCN-IR-NEXT:    v_and_b32_e32 v2, s0, v2
720; GCN-IR-NEXT:    v_mov_b32_e32 v3, v1
721; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
722; GCN-IR-NEXT:    s_endpgm
723  %1 = lshr <2 x i64> %x, <i64 33, i64 41>
724  %2 = lshr <2 x i64> %y, <i64 33, i64 41>
725  %result = urem <2 x i64> %1, %2
726  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
727  ret void
728}
729
730define amdgpu_kernel void @s_test_urem_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
731; GCN-LABEL: s_test_urem_k_num_i64:
732; GCN:       ; %bb.0:
733; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
734; GCN-NEXT:    s_mov_b32 s11, 0xf000
735; GCN-NEXT:    s_mov_b32 s10, -1
736; GCN-NEXT:    s_waitcnt lgkmcnt(0)
737; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s6
738; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s7
739; GCN-NEXT:    s_sub_u32 s0, 0, s6
740; GCN-NEXT:    s_subb_u32 s1, 0, s7
741; GCN-NEXT:    s_mov_b32 s8, s4
742; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
743; GCN-NEXT:    v_rcp_f32_e32 v0, v0
744; GCN-NEXT:    v_mov_b32_e32 v1, 0
745; GCN-NEXT:    s_mov_b32 s9, s5
746; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
747; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
748; GCN-NEXT:    v_trunc_f32_e32 v2, v2
749; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
750; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
751; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
752; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
753; GCN-NEXT:    v_mul_hi_u32 v4, s0, v0
754; GCN-NEXT:    v_mul_lo_u32 v6, s1, v0
755; GCN-NEXT:    v_mul_lo_u32 v5, s0, v0
756; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
757; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
758; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
759; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
760; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
761; GCN-NEXT:    v_mul_hi_u32 v7, v2, v5
762; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
763; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
764; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
765; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
766; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
767; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
768; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v7, vcc
769; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
770; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
771; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
772; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
773; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
774; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
775; GCN-NEXT:    v_mul_hi_u32 v4, s0, v0
776; GCN-NEXT:    v_mul_lo_u32 v5, s1, v0
777; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
778; GCN-NEXT:    v_mul_lo_u32 v4, s0, v0
779; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
780; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
781; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
782; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
783; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
784; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
785; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
786; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
787; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
788; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
789; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
790; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
791; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v5, v1, vcc
792; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
793; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
794; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
795; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
796; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
797; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
798; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
799; GCN-NEXT:    v_mov_b32_e32 v3, s7
800; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
801; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v1, vcc
802; GCN-NEXT:    v_mul_lo_u32 v1, s7, v0
803; GCN-NEXT:    v_mul_hi_u32 v2, s6, v0
804; GCN-NEXT:    v_mul_lo_u32 v0, s6, v0
805; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
806; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
807; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
808; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
809; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s6, v0
810; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
811; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s7, v5
812; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
813; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s6, v4
814; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
815; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
816; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s7, v5
817; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s6, v4
818; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
819; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
820; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
821; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
822; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
823; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
824; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
825; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
826; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
827; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s7, v1
828; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
829; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
830; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
831; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
832; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
833; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
834; GCN-NEXT:    s_endpgm
835;
836; GCN-IR-LABEL: s_test_urem_k_num_i64:
837; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
838; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
839; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
840; GCN-IR-NEXT:    s_flbit_i32_b32 s4, s2
841; GCN-IR-NEXT:    s_flbit_i32_b32 s5, s3
842; GCN-IR-NEXT:    s_add_i32 s4, s4, 32
843; GCN-IR-NEXT:    s_min_u32 s6, s4, s5
844; GCN-IR-NEXT:    s_add_u32 s8, s6, 0xffffffc5
845; GCN-IR-NEXT:    s_addc_u32 s9, 0, -1
846; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
847; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[8:9], 63
848; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0
849; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
850; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[8:9], 63
851; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
852; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
853; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
854; GCN-IR-NEXT:    s_cbranch_vccz .LBB6_5
855; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
856; GCN-IR-NEXT:    s_add_u32 s10, s8, 1
857; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
858; GCN-IR-NEXT:    s_addc_u32 s11, s9, 0
859; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
860; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
861; GCN-IR-NEXT:    s_sub_i32 s7, 63, s8
862; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
863; GCN-IR-NEXT:    s_lshl_b64 s[8:9], 24, s7
864; GCN-IR-NEXT:    s_cbranch_vccz .LBB6_4
865; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
866; GCN-IR-NEXT:    s_lshr_b64 s[12:13], 24, s10
867; GCN-IR-NEXT:    s_add_u32 s14, s2, -1
868; GCN-IR-NEXT:    s_addc_u32 s15, s3, -1
869; GCN-IR-NEXT:    s_sub_u32 s6, 58, s6
870; GCN-IR-NEXT:    s_subb_u32 s7, 0, 0
871; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
872; GCN-IR-NEXT:    s_mov_b32 s5, 0
873; GCN-IR-NEXT:  .LBB6_3: ; %udiv-do-while
874; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
875; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
876; GCN-IR-NEXT:    s_lshr_b32 s4, s9, 31
877; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
878; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[4:5]
879; GCN-IR-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
880; GCN-IR-NEXT:    s_sub_u32 s4, s14, s12
881; GCN-IR-NEXT:    s_subb_u32 s4, s15, s13
882; GCN-IR-NEXT:    s_ashr_i32 s10, s4, 31
883; GCN-IR-NEXT:    s_mov_b32 s11, s10
884; GCN-IR-NEXT:    s_and_b32 s4, s10, 1
885; GCN-IR-NEXT:    s_and_b64 s[16:17], s[10:11], s[2:3]
886; GCN-IR-NEXT:    s_sub_u32 s12, s12, s16
887; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
888; GCN-IR-NEXT:    s_subb_u32 s13, s13, s17
889; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
890; GCN-IR-NEXT:    s_add_u32 s6, s6, 1
891; GCN-IR-NEXT:    s_addc_u32 s7, s7, 0
892; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
893; GCN-IR-NEXT:    s_mov_b64 s[10:11], s[4:5]
894; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
895; GCN-IR-NEXT:    s_cbranch_vccz .LBB6_3
896; GCN-IR-NEXT:  .LBB6_4: ; %Flow5
897; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[8:9], 1
898; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], s[6:7]
899; GCN-IR-NEXT:    v_mov_b32_e32 v0, s4
900; GCN-IR-NEXT:    v_mov_b32_e32 v1, s5
901; GCN-IR-NEXT:    s_branch .LBB6_6
902; GCN-IR-NEXT:  .LBB6_5:
903; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
904; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[10:11]
905; GCN-IR-NEXT:  .LBB6_6: ; %udiv-end
906; GCN-IR-NEXT:    v_mul_lo_u32 v1, s2, v1
907; GCN-IR-NEXT:    v_mul_hi_u32 v2, s2, v0
908; GCN-IR-NEXT:    v_mul_lo_u32 v3, s3, v0
909; GCN-IR-NEXT:    v_mul_lo_u32 v0, s2, v0
910; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
911; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
912; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
913; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
914; GCN-IR-NEXT:    s_mov_b32 s6, -1
915; GCN-IR-NEXT:    s_mov_b32 s4, s0
916; GCN-IR-NEXT:    s_mov_b32 s5, s1
917; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
918; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
919; GCN-IR-NEXT:    s_endpgm
920  %result = urem i64 24, %x
921  store i64 %result, i64 addrspace(1)* %out
922  ret void
923}
924
925define amdgpu_kernel void @s_test_urem_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
926; GCN-LABEL: s_test_urem_k_den_i64:
927; GCN:       ; %bb.0:
928; GCN-NEXT:    v_mov_b32_e32 v0, 0x4f800000
929; GCN-NEXT:    v_madak_f32 v0, 0, v0, 0x41c00000
930; GCN-NEXT:    v_rcp_f32_e32 v0, v0
931; GCN-NEXT:    s_movk_i32 s4, 0xffe8
932; GCN-NEXT:    v_mov_b32_e32 v2, 0
933; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
934; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
935; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
936; GCN-NEXT:    v_trunc_f32_e32 v1, v1
937; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
938; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
939; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
940; GCN-NEXT:    s_waitcnt lgkmcnt(0)
941; GCN-NEXT:    s_mov_b32 s5, s1
942; GCN-NEXT:    s_mov_b32 s7, 0xf000
943; GCN-NEXT:    v_mul_hi_u32 v3, v0, s4
944; GCN-NEXT:    v_mul_lo_u32 v5, v1, s4
945; GCN-NEXT:    v_mul_lo_u32 v4, v0, s4
946; GCN-NEXT:    s_mov_b32 s6, -1
947; GCN-NEXT:    v_subrev_i32_e32 v3, vcc, v0, v3
948; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
949; GCN-NEXT:    v_mul_hi_u32 v6, v0, v4
950; GCN-NEXT:    v_mul_lo_u32 v5, v0, v3
951; GCN-NEXT:    v_mul_hi_u32 v7, v0, v3
952; GCN-NEXT:    v_mul_hi_u32 v8, v1, v3
953; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
954; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
955; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
956; GCN-NEXT:    v_mul_lo_u32 v7, v1, v4
957; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
958; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
959; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v4, vcc
960; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v2, vcc
961; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
962; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
963; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
964; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc
965; GCN-NEXT:    v_mul_hi_u32 v3, v0, s4
966; GCN-NEXT:    v_mul_lo_u32 v4, v1, s4
967; GCN-NEXT:    v_mul_lo_u32 v5, v0, s4
968; GCN-NEXT:    s_mov_b32 s4, s0
969; GCN-NEXT:    v_subrev_i32_e32 v3, vcc, v0, v3
970; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
971; GCN-NEXT:    v_mul_lo_u32 v4, v0, v3
972; GCN-NEXT:    v_mul_hi_u32 v6, v0, v5
973; GCN-NEXT:    v_mul_hi_u32 v7, v0, v3
974; GCN-NEXT:    v_mul_hi_u32 v8, v1, v3
975; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
976; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
977; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
978; GCN-NEXT:    v_mul_lo_u32 v7, v1, v5
979; GCN-NEXT:    v_mul_hi_u32 v5, v1, v5
980; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
981; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
982; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v2, vcc
983; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
984; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
985; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
986; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc
987; GCN-NEXT:    v_mul_lo_u32 v3, s2, v1
988; GCN-NEXT:    v_mul_hi_u32 v4, s2, v0
989; GCN-NEXT:    v_mul_hi_u32 v5, s2, v1
990; GCN-NEXT:    v_mul_hi_u32 v6, s3, v1
991; GCN-NEXT:    v_mul_lo_u32 v1, s3, v1
992; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
993; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
994; GCN-NEXT:    v_mul_lo_u32 v5, s3, v0
995; GCN-NEXT:    v_mul_hi_u32 v0, s3, v0
996; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
997; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
998; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v6, v2, vcc
999; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1000; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
1001; GCN-NEXT:    v_mul_lo_u32 v1, v1, 24
1002; GCN-NEXT:    v_mul_hi_u32 v2, v0, 24
1003; GCN-NEXT:    v_mul_lo_u32 v0, v0, 24
1004; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1005; GCN-NEXT:    v_mov_b32_e32 v2, s3
1006; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1007; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1008; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v0
1009; GCN-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v1, vcc
1010; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v2
1011; GCN-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v3, vcc
1012; GCN-NEXT:    v_cmp_lt_u32_e32 vcc, 23, v2
1013; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1014; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
1015; GCN-NEXT:    v_cndmask_b32_e32 v6, -1, v6, vcc
1016; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
1017; GCN-NEXT:    v_cmp_lt_u32_e64 s[0:1], 23, v0
1018; GCN-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
1019; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
1020; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
1021; GCN-NEXT:    v_cndmask_b32_e64 v5, -1, v5, s[0:1]
1022; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v5
1023; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
1024; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
1025; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
1026; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1027; GCN-NEXT:    s_endpgm
1028;
1029; GCN-IR-LABEL: s_test_urem_k_den_i64:
1030; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1031; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1032; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1033; GCN-IR-NEXT:    s_flbit_i32_b32 s4, s2
1034; GCN-IR-NEXT:    s_flbit_i32_b32 s5, s3
1035; GCN-IR-NEXT:    s_add_i32 s4, s4, 32
1036; GCN-IR-NEXT:    s_min_u32 s6, s4, s5
1037; GCN-IR-NEXT:    s_sub_u32 s8, 59, s6
1038; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
1039; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
1040; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[8:9], 63
1041; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0
1042; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
1043; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[8:9], 63
1044; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
1045; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
1046; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
1047; GCN-IR-NEXT:    s_cbranch_vccz .LBB7_5
1048; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1049; GCN-IR-NEXT:    s_add_u32 s10, s8, 1
1050; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1051; GCN-IR-NEXT:    s_addc_u32 s11, s9, 0
1052; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
1053; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1054; GCN-IR-NEXT:    s_sub_i32 s7, 63, s8
1055; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1056; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[2:3], s7
1057; GCN-IR-NEXT:    s_cbranch_vccz .LBB7_4
1058; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1059; GCN-IR-NEXT:    s_lshr_b64 s[12:13], s[2:3], s10
1060; GCN-IR-NEXT:    s_add_u32 s6, s6, 0xffffffc4
1061; GCN-IR-NEXT:    s_addc_u32 s7, 0, -1
1062; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1063; GCN-IR-NEXT:    s_mov_b32 s5, 0
1064; GCN-IR-NEXT:  .LBB7_3: ; %udiv-do-while
1065; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1066; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
1067; GCN-IR-NEXT:    s_lshr_b32 s4, s9, 31
1068; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
1069; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[4:5]
1070; GCN-IR-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
1071; GCN-IR-NEXT:    s_sub_u32 s4, 23, s12
1072; GCN-IR-NEXT:    s_subb_u32 s4, 0, s13
1073; GCN-IR-NEXT:    s_ashr_i32 s10, s4, 31
1074; GCN-IR-NEXT:    s_and_b32 s4, s10, 1
1075; GCN-IR-NEXT:    s_and_b32 s10, s10, 24
1076; GCN-IR-NEXT:    s_sub_u32 s12, s12, s10
1077; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1078; GCN-IR-NEXT:    s_subb_u32 s13, s13, 0
1079; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1080; GCN-IR-NEXT:    s_add_u32 s6, s6, 1
1081; GCN-IR-NEXT:    s_addc_u32 s7, s7, 0
1082; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
1083; GCN-IR-NEXT:    s_mov_b64 s[10:11], s[4:5]
1084; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1085; GCN-IR-NEXT:    s_cbranch_vccz .LBB7_3
1086; GCN-IR-NEXT:  .LBB7_4: ; %Flow5
1087; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[8:9], 1
1088; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], s[6:7]
1089; GCN-IR-NEXT:    v_mov_b32_e32 v0, s4
1090; GCN-IR-NEXT:    v_mov_b32_e32 v1, s5
1091; GCN-IR-NEXT:    s_branch .LBB7_6
1092; GCN-IR-NEXT:  .LBB7_5:
1093; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
1094; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[10:11]
1095; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1096; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[10:11]
1097; GCN-IR-NEXT:  .LBB7_6: ; %udiv-end
1098; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, 24
1099; GCN-IR-NEXT:    v_mul_hi_u32 v2, v0, 24
1100; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, 24
1101; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1102; GCN-IR-NEXT:    s_mov_b32 s6, -1
1103; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1104; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1105; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1106; GCN-IR-NEXT:    s_mov_b32 s4, s0
1107; GCN-IR-NEXT:    s_mov_b32 s5, s1
1108; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1109; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1110; GCN-IR-NEXT:    s_endpgm
1111  %result = urem i64 %x, 24
1112  store i64 %result, i64 addrspace(1)* %out
1113  ret void
1114}
1115
1116; FIXME: Constant bus violation
1117; define i64 @v_test_urem_k_num_i64(i64 %x) {
1118;   %result = urem i64 24, %x
1119;   ret i64 %result
1120; }
1121
1122define i64 @v_test_urem_pow2_k_num_i64(i64 %x) {
1123; GCN-LABEL: v_test_urem_pow2_k_num_i64:
1124; GCN:       ; %bb.0:
1125; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1126; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1127; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1128; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1129; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1130; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1131; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1132; GCN-NEXT:    v_mov_b32_e32 v11, 0
1133; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1134; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1135; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1136; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1137; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1138; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1139; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1140; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1141; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1142; GCN-NEXT:    v_mul_lo_u32 v9, v4, v2
1143; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1144; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1145; GCN-NEXT:    v_mul_lo_u32 v7, v2, v6
1146; GCN-NEXT:    v_mul_hi_u32 v8, v2, v9
1147; GCN-NEXT:    v_mul_hi_u32 v10, v2, v6
1148; GCN-NEXT:    v_mul_hi_u32 v12, v3, v6
1149; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1150; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1151; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v10, vcc
1152; GCN-NEXT:    v_mul_lo_u32 v10, v3, v9
1153; GCN-NEXT:    v_mul_hi_u32 v9, v3, v9
1154; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
1155; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v9, vcc
1156; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v11, vcc
1157; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1158; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
1159; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
1160; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v7, vcc
1161; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1162; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1163; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1164; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1165; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1166; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1167; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
1168; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
1169; GCN-NEXT:    v_mul_hi_u32 v10, v2, v5
1170; GCN-NEXT:    v_mul_hi_u32 v7, v3, v4
1171; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1172; GCN-NEXT:    v_mul_hi_u32 v6, v3, v5
1173; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1174; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
1175; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
1176; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
1177; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
1178; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v11, vcc
1179; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1180; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1181; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1182; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v3, v5, vcc
1183; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1184; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
1185; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1186; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
1187; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1188; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1189; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0x8000, v2
1190; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1191; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
1192; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1193; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
1194; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1195; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
1196; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1197; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1
1198; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1199; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1200; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v0
1201; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1202; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1203; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1204; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1205; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1206; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1207; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1208; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1209; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
1210; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1211; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1212; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1213; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1214; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1215; GCN-NEXT:    s_setpc_b64 s[30:31]
1216;
1217; GCN-IR-LABEL: v_test_urem_pow2_k_num_i64:
1218; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1219; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1220; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1221; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1222; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1223; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1224; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 0xffffffd0, v6
1225; GCN-IR-NEXT:    v_addc_u32_e64 v3, s[6:7], 0, -1, vcc
1226; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1227; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[2:3]
1228; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0x8000
1229; GCN-IR-NEXT:    v_mov_b32_e32 v4, s8
1230; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1231; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[2:3]
1232; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1233; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v4, 0, s[4:5]
1234; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1235; GCN-IR-NEXT:    v_mov_b32_e32 v5, v7
1236; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1237; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1238; GCN-IR-NEXT:    s_cbranch_execz .LBB8_6
1239; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1240; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v2
1241; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v3, vcc
1242; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[8:9], v[2:3]
1243; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v2
1244; GCN-IR-NEXT:    v_lshl_b64 v[2:3], s[8:9], v2
1245; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1246; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1247; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1248; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1249; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1250; GCN-IR-NEXT:    s_cbranch_execz .LBB8_5
1251; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1252; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, -1, v0
1253; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0x8000
1254; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, -1, v1, vcc
1255; GCN-IR-NEXT:    v_lshr_b64 v[8:9], s[4:5], v8
1256; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, 47, v6
1257; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1258; GCN-IR-NEXT:    v_subb_u32_e32 v7, vcc, 0, v7, vcc
1259; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1260; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1261; GCN-IR-NEXT:  .LBB8_3: ; %udiv-do-while
1262; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1263; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1264; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1265; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1266; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1267; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, v12, v8
1268; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, v13, v9, vcc
1269; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1270; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1271; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1272; GCN-IR-NEXT:    v_and_b32_e32 v14, v10, v1
1273; GCN-IR-NEXT:    v_and_b32_e32 v15, v10, v0
1274; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v6
1275; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1276; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v7, vcc
1277; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7]
1278; GCN-IR-NEXT:    v_mov_b32_e32 v6, v10
1279; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v15
1280; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1281; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1282; GCN-IR-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v14, s[4:5]
1283; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1284; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1285; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1286; GCN-IR-NEXT:    s_cbranch_execnz .LBB8_3
1287; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1288; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1289; GCN-IR-NEXT:  .LBB8_5: ; %Flow3
1290; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1291; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1292; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1293; GCN-IR-NEXT:    v_or_b32_e32 v4, v4, v2
1294; GCN-IR-NEXT:  .LBB8_6: ; %Flow4
1295; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1296; GCN-IR-NEXT:    v_mul_lo_u32 v2, v0, v5
1297; GCN-IR-NEXT:    v_mul_hi_u32 v3, v0, v4
1298; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v4
1299; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v4
1300; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1301; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1302; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1303; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1304; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1305  %result = urem i64 32768, %x
1306  ret i64 %result
1307}
1308
1309define i64 @v_test_urem_pow2_k_den_i64(i64 %x) {
1310; GCN-LABEL: v_test_urem_pow2_k_den_i64:
1311; GCN:       ; %bb.0:
1312; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1313; GCN-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
1314; GCN-NEXT:    v_mov_b32_e32 v1, 0
1315; GCN-NEXT:    s_setpc_b64 s[30:31]
1316;
1317; GCN-IR-LABEL: v_test_urem_pow2_k_den_i64:
1318; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1319; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1320; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1321; GCN-IR-NEXT:    v_add_i32_e64 v2, s[4:5], 32, v2
1322; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1323; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1324; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 48, v6
1325; GCN-IR-NEXT:    v_subb_u32_e64 v3, s[4:5], 0, 0, s[4:5]
1326; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1327; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[2:3]
1328; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1329; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[2:3]
1330; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1331; GCN-IR-NEXT:    v_cndmask_b32_e64 v5, v1, 0, s[4:5]
1332; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v0, 0, s[4:5]
1333; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1334; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1335; GCN-IR-NEXT:    s_cbranch_execz .LBB9_6
1336; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1337; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 1, v2
1338; GCN-IR-NEXT:    v_addc_u32_e32 v8, vcc, 0, v3, vcc
1339; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[7:8], v[2:3]
1340; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v2
1341; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[0:1], v2
1342; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1343; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1344; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1345; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1346; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1347; GCN-IR-NEXT:    s_cbranch_execz .LBB9_5
1348; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1349; GCN-IR-NEXT:    v_lshr_b64 v[8:9], v[0:1], v7
1350; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 0xffffffcf, v6
1351; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1352; GCN-IR-NEXT:    v_addc_u32_e64 v7, s[4:5], 0, -1, vcc
1353; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1354; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1355; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1356; GCN-IR-NEXT:  .LBB9_3: ; %udiv-do-while
1357; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1358; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1359; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1360; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1361; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1362; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, s12, v8
1363; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, 0, v9, vcc
1364; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1365; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1366; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1367; GCN-IR-NEXT:    v_and_b32_e32 v12, 0x8000, v10
1368; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v6
1369; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1370; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v7, vcc
1371; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7]
1372; GCN-IR-NEXT:    v_mov_b32_e32 v6, v10
1373; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v12
1374; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1375; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1376; GCN-IR-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5]
1377; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1378; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1379; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1380; GCN-IR-NEXT:    s_cbranch_execnz .LBB9_3
1381; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1382; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1383; GCN-IR-NEXT:  .LBB9_5: ; %Flow3
1384; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1385; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1386; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1387; GCN-IR-NEXT:    v_or_b32_e32 v4, v4, v2
1388; GCN-IR-NEXT:  .LBB9_6: ; %Flow4
1389; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1390; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[4:5], 15
1391; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1392; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1393; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1394  %result = urem i64 %x, 32768
1395  ret i64 %result
1396}
1397
1398define amdgpu_kernel void @s_test_urem24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1399; GCN-LABEL: s_test_urem24_k_num_i64:
1400; GCN:       ; %bb.0:
1401; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1402; GCN-NEXT:    s_mov_b32 s5, 0x41c00000
1403; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1404; GCN-NEXT:    s_mov_b32 s2, -1
1405; GCN-NEXT:    s_lshr_b32 s4, s3, 8
1406; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
1407; GCN-NEXT:    s_mov_b32 s3, 0xf000
1408; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1409; GCN-NEXT:    v_mul_f32_e32 v1, s5, v1
1410; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1411; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1412; GCN-NEXT:    v_mad_f32 v1, -v1, v0, s5
1413; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1414; GCN-NEXT:    v_mov_b32_e32 v1, 0
1415; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1416; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
1417; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1418; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1419; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1420; GCN-NEXT:    s_endpgm
1421;
1422; GCN-IR-LABEL: s_test_urem24_k_num_i64:
1423; GCN-IR:       ; %bb.0:
1424; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1425; GCN-IR-NEXT:    s_mov_b32 s5, 0x41c00000
1426; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1427; GCN-IR-NEXT:    s_mov_b32 s2, -1
1428; GCN-IR-NEXT:    s_lshr_b32 s4, s3, 8
1429; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
1430; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1431; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1432; GCN-IR-NEXT:    v_mul_f32_e32 v1, s5, v1
1433; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1434; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1435; GCN-IR-NEXT:    v_mad_f32 v1, -v1, v0, s5
1436; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1437; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1438; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1439; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
1440; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1441; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1442; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1443; GCN-IR-NEXT:    s_endpgm
1444  %x.shr = lshr i64 %x, 40
1445  %result = urem i64 24, %x.shr
1446  store i64 %result, i64 addrspace(1)* %out
1447  ret void
1448}
1449
1450define amdgpu_kernel void @s_test_urem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1451; GCN-LABEL: s_test_urem24_k_den_i64:
1452; GCN:       ; %bb.0:
1453; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1454; GCN-NEXT:    s_mov_b32 s4, 0x46b6fe00
1455; GCN-NEXT:    s_mov_b32 s7, 0xf000
1456; GCN-NEXT:    s_mov_b32 s6, -1
1457; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1458; GCN-NEXT:    s_lshr_b32 s2, s3, 8
1459; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
1460; GCN-NEXT:    s_movk_i32 s3, 0x5b7f
1461; GCN-NEXT:    s_mov_b32 s5, s1
1462; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1463; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1464; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1465; GCN-NEXT:    v_mad_f32 v0, -v1, s4, v0
1466; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
1467; GCN-NEXT:    s_mov_b32 s4, s0
1468; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1469; GCN-NEXT:    v_mul_lo_u32 v0, v0, s3
1470; GCN-NEXT:    v_mov_b32_e32 v1, 0
1471; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1472; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1473; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1474; GCN-NEXT:    s_endpgm
1475;
1476; GCN-IR-LABEL: s_test_urem24_k_den_i64:
1477; GCN-IR:       ; %bb.0:
1478; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1479; GCN-IR-NEXT:    s_mov_b32 s4, 0x46b6fe00
1480; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1481; GCN-IR-NEXT:    s_mov_b32 s6, -1
1482; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1483; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 8
1484; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
1485; GCN-IR-NEXT:    s_movk_i32 s3, 0x5b7f
1486; GCN-IR-NEXT:    s_mov_b32 s5, s1
1487; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1488; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1489; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1490; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s4, v0
1491; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
1492; GCN-IR-NEXT:    s_mov_b32 s4, s0
1493; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1494; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s3
1495; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1496; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1497; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1498; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1499; GCN-IR-NEXT:    s_endpgm
1500  %x.shr = lshr i64 %x, 40
1501  %result = urem i64 %x.shr, 23423
1502  store i64 %result, i64 addrspace(1)* %out
1503  ret void
1504}
1505
1506define i64 @v_test_urem24_k_num_i64(i64 %x) {
1507; GCN-LABEL: v_test_urem24_k_num_i64:
1508; GCN:       ; %bb.0:
1509; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1510; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1511; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v0
1512; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
1513; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1514; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
1515; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1516; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
1517; GCN-NEXT:    v_mad_f32 v2, -v2, v1, s4
1518; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1519; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1520; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
1521; GCN-NEXT:    v_mov_b32_e32 v1, 0
1522; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1523; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1524; GCN-NEXT:    s_setpc_b64 s[30:31]
1525;
1526; GCN-IR-LABEL: v_test_urem24_k_num_i64:
1527; GCN-IR:       ; %bb.0:
1528; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1529; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1530; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, v0
1531; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
1532; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1533; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
1534; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1535; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
1536; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v1, s4
1537; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1538; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1539; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
1540; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1541; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1542; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1543; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1544  %x.shr = lshr i64 %x, 40
1545  %result = urem i64 24, %x.shr
1546  ret i64 %result
1547}
1548
1549define i64 @v_test_urem24_pow2_k_num_i64(i64 %x) {
1550; GCN-LABEL: v_test_urem24_pow2_k_num_i64:
1551; GCN:       ; %bb.0:
1552; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1553; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1554; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v0
1555; GCN-NEXT:    s_mov_b32 s4, 0x47000000
1556; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1557; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
1558; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1559; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
1560; GCN-NEXT:    v_mad_f32 v2, -v2, v1, s4
1561; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1562; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1563; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
1564; GCN-NEXT:    v_mov_b32_e32 v1, 0
1565; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1566; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1567; GCN-NEXT:    s_setpc_b64 s[30:31]
1568;
1569; GCN-IR-LABEL: v_test_urem24_pow2_k_num_i64:
1570; GCN-IR:       ; %bb.0:
1571; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1572; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1573; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, v0
1574; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
1575; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1576; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
1577; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1578; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
1579; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v1, s4
1580; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1581; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1582; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
1583; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1584; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1585; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1586; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1587  %x.shr = lshr i64 %x, 40
1588  %result = urem i64 32768, %x.shr
1589  ret i64 %result
1590}
1591
1592define i64 @v_test_urem24_pow2_k_den_i64(i64 %x) {
1593; GCN-LABEL: v_test_urem24_pow2_k_den_i64:
1594; GCN:       ; %bb.0:
1595; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1596; GCN-NEXT:    v_bfe_u32 v0, v1, 8, 15
1597; GCN-NEXT:    v_mov_b32_e32 v1, 0
1598; GCN-NEXT:    s_setpc_b64 s[30:31]
1599;
1600; GCN-IR-LABEL: v_test_urem24_pow2_k_den_i64:
1601; GCN-IR:       ; %bb.0:
1602; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1603; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1604; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, v0
1605; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
1606; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38000000, v1
1607; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1608; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
1609; GCN-IR-NEXT:    v_mad_f32 v1, -v2, s4, v1
1610; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
1611; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1612; GCN-IR-NEXT:    v_lshlrev_b32_e32 v1, 15, v1
1613; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
1614; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1615; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1616; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1617  %x.shr = lshr i64 %x, 40
1618  %result = urem i64 %x.shr, 32768
1619  ret i64 %result
1620}
1621