1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_urem_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_urem_i64:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
9; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
10; GCN-NEXT:    s_mov_b32 s7, 0xf000
11; GCN-NEXT:    s_mov_b32 s6, -1
12; GCN-NEXT:    s_waitcnt lgkmcnt(0)
13; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
14; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
15; GCN-NEXT:    s_sub_u32 s2, 0, s12
16; GCN-NEXT:    s_subb_u32 s3, 0, s13
17; GCN-NEXT:    s_mov_b32 s4, s8
18; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
19; GCN-NEXT:    v_rcp_f32_e32 v0, v0
20; GCN-NEXT:    s_mov_b32 s5, s9
21; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
22; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
23; GCN-NEXT:    v_trunc_f32_e32 v1, v1
24; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
25; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
26; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
27; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
28; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
29; GCN-NEXT:    v_mul_lo_u32 v5, s3, v0
30; GCN-NEXT:    v_mul_lo_u32 v4, s2, v0
31; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
32; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
33; GCN-NEXT:    v_mul_hi_u32 v3, v0, v4
34; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
35; GCN-NEXT:    v_mul_hi_u32 v7, v0, v2
36; GCN-NEXT:    v_mul_hi_u32 v6, v1, v4
37; GCN-NEXT:    v_mul_lo_u32 v4, v1, v4
38; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
39; GCN-NEXT:    v_mul_hi_u32 v8, v1, v2
40; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v7, vcc
41; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
42; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
43; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v5, v6, vcc
44; GCN-NEXT:    v_mov_b32_e32 v4, 0
45; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v4, vcc
46; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
47; GCN-NEXT:    v_mov_b32_e32 v6, 0
48; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
49; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v6, v5, vcc
50; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
51; GCN-NEXT:    v_mul_lo_u32 v5, s2, v2
52; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
53; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
54; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
55; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
56; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
57; GCN-NEXT:    v_mul_lo_u32 v10, v0, v5
58; GCN-NEXT:    v_mul_hi_u32 v12, v0, v5
59; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
60; GCN-NEXT:    v_mul_hi_u32 v9, v2, v7
61; GCN-NEXT:    v_mul_lo_u32 v7, v2, v7
62; GCN-NEXT:    v_mul_hi_u32 v8, v2, v5
63; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
64; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
65; GCN-NEXT:    v_mul_lo_u32 v2, v2, v5
66; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
67; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
68; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v4, vcc
69; GCN-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
70; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v6, v5, vcc
71; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
72; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
73; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
74; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
75; GCN-NEXT:    v_mul_lo_u32 v2, s10, v1
76; GCN-NEXT:    v_mul_hi_u32 v3, s10, v0
77; GCN-NEXT:    v_mul_hi_u32 v5, s10, v1
78; GCN-NEXT:    v_mul_hi_u32 v7, s11, v1
79; GCN-NEXT:    v_mul_lo_u32 v1, s11, v1
80; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
81; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
82; GCN-NEXT:    v_mul_lo_u32 v5, s11, v0
83; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
84; GCN-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
85; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
86; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v7, v4, vcc
87; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
88; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
89; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
90; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
91; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
92; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
93; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
94; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
95; GCN-NEXT:    v_sub_i32_e64 v0, s[0:1], s10, v0
96; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
97; GCN-NEXT:    v_mov_b32_e32 v3, s13
98; GCN-NEXT:    v_subb_u32_e64 v2, vcc, v2, v3, s[0:1]
99; GCN-NEXT:    v_subrev_i32_e64 v4, s[2:3], s12, v0
100; GCN-NEXT:    v_subbrev_u32_e64 v5, vcc, 0, v2, s[2:3]
101; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v5
102; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
103; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v4
104; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
105; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v5
106; GCN-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc
107; GCN-NEXT:    v_subb_u32_e64 v2, vcc, v2, v3, s[2:3]
108; GCN-NEXT:    v_subrev_i32_e32 v3, vcc, s12, v4
109; GCN-NEXT:    v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
110; GCN-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v6
111; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[2:3]
112; GCN-NEXT:    v_mov_b32_e32 v5, s11
113; GCN-NEXT:    v_subb_u32_e64 v1, vcc, v5, v1, s[0:1]
114; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
115; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
116; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
117; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
118; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
119; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
120; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
121; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
122; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[2:3]
123; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
124; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
125; GCN-NEXT:    s_endpgm
126;
127; GCN-IR-LABEL: s_test_urem_i64:
128; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
129; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
130; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
131; GCN-IR-NEXT:    s_mov_b64 s[2:3], 0
132; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
133; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
134; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[0:1], 0
135; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s0
136; GCN-IR-NEXT:    s_add_i32 s14, s12, 32
137; GCN-IR-NEXT:    s_or_b64 s[12:13], s[8:9], s[10:11]
138; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s1
139; GCN-IR-NEXT:    s_cmp_eq_u32 s1, 0
140; GCN-IR-NEXT:    s_cselect_b32 s10, s14, s8
141; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s6
142; GCN-IR-NEXT:    s_add_i32 s8, s8, 32
143; GCN-IR-NEXT:    s_flbit_i32_b32 s9, s7
144; GCN-IR-NEXT:    s_cmp_eq_u32 s7, 0
145; GCN-IR-NEXT:    s_cselect_b32 s14, s8, s9
146; GCN-IR-NEXT:    s_sub_u32 s8, s10, s14
147; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
148; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[16:17], s[8:9], 63
149; GCN-IR-NEXT:    s_mov_b32 s11, 0
150; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[16:17]
151; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[16:17], s[8:9], 63
152; GCN-IR-NEXT:    s_xor_b64 s[18:19], s[12:13], -1
153; GCN-IR-NEXT:    s_and_b64 s[16:17], s[18:19], s[16:17]
154; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
155; GCN-IR-NEXT:    s_cbranch_vccz BB0_5
156; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
157; GCN-IR-NEXT:    s_add_u32 s16, s8, 1
158; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
159; GCN-IR-NEXT:    s_addc_u32 s17, s9, 0
160; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
161; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1]
162; GCN-IR-NEXT:    s_sub_i32 s8, 63, s8
163; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
164; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[6:7], s8
165; GCN-IR-NEXT:    s_cbranch_vccz BB0_4
166; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
167; GCN-IR-NEXT:    s_lshr_b64 s[16:17], s[6:7], s16
168; GCN-IR-NEXT:    s_add_u32 s8, s0, -1
169; GCN-IR-NEXT:    s_addc_u32 s9, s1, -1
170; GCN-IR-NEXT:    s_not_b64 s[2:3], s[10:11]
171; GCN-IR-NEXT:    s_mov_b32 s15, s11
172; GCN-IR-NEXT:    s_add_u32 s10, s2, s14
173; GCN-IR-NEXT:    s_addc_u32 s11, s3, s11
174; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
175; GCN-IR-NEXT:    s_mov_b32 s3, 0
176; GCN-IR-NEXT:  BB0_3: ; %udiv-do-while
177; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
178; GCN-IR-NEXT:    s_lshr_b32 s2, s13, 31
179; GCN-IR-NEXT:    s_lshl_b64 s[16:17], s[16:17], 1
180; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
181; GCN-IR-NEXT:    s_or_b64 s[16:17], s[16:17], s[2:3]
182; GCN-IR-NEXT:    s_or_b64 s[12:13], s[14:15], s[12:13]
183; GCN-IR-NEXT:    s_sub_u32 s2, s8, s16
184; GCN-IR-NEXT:    s_subb_u32 s2, s9, s17
185; GCN-IR-NEXT:    s_ashr_i32 s14, s2, 31
186; GCN-IR-NEXT:    s_mov_b32 s15, s14
187; GCN-IR-NEXT:    s_and_b32 s2, s14, 1
188; GCN-IR-NEXT:    s_and_b64 s[18:19], s[14:15], s[0:1]
189; GCN-IR-NEXT:    s_sub_u32 s16, s16, s18
190; GCN-IR-NEXT:    v_mov_b32_e32 v0, s10
191; GCN-IR-NEXT:    s_subb_u32 s17, s17, s19
192; GCN-IR-NEXT:    v_mov_b32_e32 v1, s11
193; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
194; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
195; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
196; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[2:3]
197; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
198; GCN-IR-NEXT:    s_cbranch_vccz BB0_3
199; GCN-IR-NEXT:  BB0_4: ; %Flow6
200; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[12:13], 1
201; GCN-IR-NEXT:    s_or_b64 s[2:3], s[2:3], s[8:9]
202; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
203; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
204; GCN-IR-NEXT:    s_branch BB0_6
205; GCN-IR-NEXT:  BB0_5:
206; GCN-IR-NEXT:    v_mov_b32_e32 v0, s7
207; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[12:13]
208; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
209; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[12:13]
210; GCN-IR-NEXT:  BB0_6: ; %udiv-end
211; GCN-IR-NEXT:    v_mul_lo_u32 v1, s0, v1
212; GCN-IR-NEXT:    v_mul_hi_u32 v2, s0, v0
213; GCN-IR-NEXT:    v_mul_lo_u32 v3, s1, v0
214; GCN-IR-NEXT:    v_mul_lo_u32 v0, s0, v0
215; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
216; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
217; GCN-IR-NEXT:    v_mov_b32_e32 v2, s7
218; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
219; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
220; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
221; GCN-IR-NEXT:    s_mov_b32 s6, -1
222; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
223; GCN-IR-NEXT:    s_endpgm
224  %result = urem i64 %x, %y
225  store i64 %result, i64 addrspace(1)* %out
226  ret void
227}
228
229define i64 @v_test_urem_i64(i64 %x, i64 %y) {
230; GCN-LABEL: v_test_urem_i64:
231; GCN:       ; %bb.0:
232; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
233; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
234; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v3
235; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v2
236; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v3, vcc
237; GCN-NEXT:    v_mov_b32_e32 v14, 0
238; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
239; GCN-NEXT:    v_rcp_f32_e32 v4, v4
240; GCN-NEXT:    v_mov_b32_e32 v13, 0
241; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
242; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
243; GCN-NEXT:    v_trunc_f32_e32 v5, v5
244; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
245; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
246; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
247; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
248; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
249; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
250; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
251; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
252; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
253; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
254; GCN-NEXT:    v_mul_hi_u32 v10, v4, v8
255; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
256; GCN-NEXT:    v_mul_hi_u32 v15, v5, v8
257; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
258; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
259; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
260; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
261; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v10, vcc
262; GCN-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
263; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v10, v9, vcc
264; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v15, v13, vcc
265; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
266; GCN-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v8
267; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v10, vcc
268; GCN-NEXT:    v_addc_u32_e64 v8, vcc, v5, v9, s[4:5]
269; GCN-NEXT:    v_mul_lo_u32 v10, v6, v8
270; GCN-NEXT:    v_mul_hi_u32 v11, v6, v4
271; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
272; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
273; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
274; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
275; GCN-NEXT:    v_mul_lo_u32 v12, v4, v7
276; GCN-NEXT:    v_mul_hi_u32 v15, v4, v6
277; GCN-NEXT:    v_mul_hi_u32 v16, v4, v7
278; GCN-NEXT:    v_mul_hi_u32 v11, v8, v6
279; GCN-NEXT:    v_mul_lo_u32 v6, v8, v6
280; GCN-NEXT:    v_add_i32_e32 v12, vcc, v15, v12
281; GCN-NEXT:    v_mul_hi_u32 v10, v8, v7
282; GCN-NEXT:    v_addc_u32_e32 v15, vcc, v14, v16, vcc
283; GCN-NEXT:    v_mul_lo_u32 v7, v8, v7
284; GCN-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
285; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v15, v11, vcc
286; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v13, vcc
287; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
288; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v14, v8, vcc
289; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
290; GCN-NEXT:    v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
291; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
292; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
293; GCN-NEXT:    v_mul_lo_u32 v6, v0, v5
294; GCN-NEXT:    v_mul_hi_u32 v7, v0, v4
295; GCN-NEXT:    v_mul_hi_u32 v8, v0, v5
296; GCN-NEXT:    v_mul_hi_u32 v9, v1, v5
297; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
298; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
299; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v14, v8, vcc
300; GCN-NEXT:    v_mul_lo_u32 v8, v1, v4
301; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
302; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
303; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v4, vcc
304; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v13, vcc
305; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
306; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v14, v6, vcc
307; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
308; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
309; GCN-NEXT:    v_mul_lo_u32 v7, v3, v4
310; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
311; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
312; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
313; GCN-NEXT:    v_sub_i32_e32 v6, vcc, v1, v5
314; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
315; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v6, v3, vcc
316; GCN-NEXT:    v_sub_i32_e64 v6, s[4:5], v0, v2
317; GCN-NEXT:    v_subbrev_u32_e64 v7, s[6:7], 0, v4, s[4:5]
318; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v7, v3
319; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
320; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
321; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v2
322; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[6:7]
323; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v7, v3
324; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
325; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v3, s[4:5]
326; GCN-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[6:7]
327; GCN-NEXT:    v_sub_i32_e64 v9, s[4:5], v6, v2
328; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
329; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
330; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
331; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
332; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
333; GCN-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
334; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v8
335; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
336; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v9, s[4:5]
337; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v4, s[4:5]
338; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
339; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
340; GCN-NEXT:    s_setpc_b64 s[30:31]
341;
342; GCN-IR-LABEL: v_test_urem_i64:
343; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
344; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
345; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[2:3]
346; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
347; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v2
348; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
349; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
350; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v3
351; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
352; GCN-IR-NEXT:    v_cndmask_b32_e32 v10, v5, v4, vcc
353; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
354; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
355; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
356; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
357; GCN-IR-NEXT:    v_cndmask_b32_e32 v12, v5, v4, vcc
358; GCN-IR-NEXT:    v_sub_i32_e32 v5, vcc, v10, v12
359; GCN-IR-NEXT:    v_subb_u32_e64 v6, s[6:7], 0, 0, vcc
360; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[5:6]
361; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
362; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
363; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[5:6]
364; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
365; GCN-IR-NEXT:    v_mov_b32_e32 v13, v11
366; GCN-IR-NEXT:    v_cndmask_b32_e64 v7, v1, 0, s[4:5]
367; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v0, 0, s[4:5]
368; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
369; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
370; GCN-IR-NEXT:    s_cbranch_execz BB1_6
371; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
372; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 1, v5
373; GCN-IR-NEXT:    v_addc_u32_e32 v8, vcc, 0, v6, vcc
374; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v5
375; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[7:8], v[5:6]
376; GCN-IR-NEXT:    v_mov_b32_e32 v8, 0
377; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[0:1], v4
378; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
379; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
380; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
381; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
382; GCN-IR-NEXT:    s_cbranch_execz BB1_5
383; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
384; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, -1, v2
385; GCN-IR-NEXT:    v_lshr_b64 v[14:15], v[0:1], v7
386; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, -1, v3, vcc
387; GCN-IR-NEXT:    v_not_b32_e32 v8, v10
388; GCN-IR-NEXT:    v_not_b32_e32 v9, v11
389; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, v8, v12
390; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, v9, v13, vcc
391; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
392; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
393; GCN-IR-NEXT:  BB1_3: ; %udiv-do-while
394; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
395; GCN-IR-NEXT:    v_lshl_b64 v[14:15], v[14:15], 1
396; GCN-IR-NEXT:    v_lshrrev_b32_e32 v8, 31, v5
397; GCN-IR-NEXT:    v_or_b32_e32 v14, v14, v8
398; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
399; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, v6, v14
400; GCN-IR-NEXT:    v_subb_u32_e32 v8, vcc, v7, v15, vcc
401; GCN-IR-NEXT:    v_or_b32_e32 v4, v12, v4
402; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v8
403; GCN-IR-NEXT:    v_and_b32_e32 v17, v12, v2
404; GCN-IR-NEXT:    v_and_b32_e32 v8, 1, v12
405; GCN-IR-NEXT:    v_and_b32_e32 v16, v12, v3
406; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v10
407; GCN-IR-NEXT:    v_or_b32_e32 v5, v13, v5
408; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v11, vcc
409; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[10:11]
410; GCN-IR-NEXT:    v_mov_b32_e32 v10, v12
411; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
412; GCN-IR-NEXT:    v_sub_i32_e64 v14, s[4:5], v14, v17
413; GCN-IR-NEXT:    v_mov_b32_e32 v11, v13
414; GCN-IR-NEXT:    v_mov_b32_e32 v13, v9
415; GCN-IR-NEXT:    v_subb_u32_e64 v15, s[4:5], v15, v16, s[4:5]
416; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
417; GCN-IR-NEXT:    v_mov_b32_e32 v12, v8
418; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
419; GCN-IR-NEXT:    s_cbranch_execnz BB1_3
420; GCN-IR-NEXT:  ; %bb.4: ; %Flow
421; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
422; GCN-IR-NEXT:  BB1_5: ; %Flow3
423; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
424; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
425; GCN-IR-NEXT:    v_or_b32_e32 v7, v9, v5
426; GCN-IR-NEXT:    v_or_b32_e32 v4, v8, v4
427; GCN-IR-NEXT:  BB1_6: ; %Flow4
428; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
429; GCN-IR-NEXT:    v_mul_lo_u32 v5, v2, v7
430; GCN-IR-NEXT:    v_mul_hi_u32 v6, v2, v4
431; GCN-IR-NEXT:    v_mul_lo_u32 v3, v3, v4
432; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, v4
433; GCN-IR-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
434; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
435; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
436; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
437; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
438  %result = urem i64 %x, %y
439  ret i64 %result
440}
441
442define amdgpu_kernel void @s_test_urem31_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
443; GCN-LABEL: s_test_urem31_i64:
444; GCN:       ; %bb.0:
445; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
446; GCN-NEXT:    s_waitcnt lgkmcnt(0)
447; GCN-NEXT:    s_lshr_b32 s4, s2, 1
448; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
449; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
450; GCN-NEXT:    s_waitcnt lgkmcnt(0)
451; GCN-NEXT:    s_mov_b32 s2, -1
452; GCN-NEXT:    s_lshr_b32 s5, s3, 1
453; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s5
454; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
455; GCN-NEXT:    s_mov_b32 s3, 0xf000
456; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
457; GCN-NEXT:    v_trunc_f32_e32 v2, v2
458; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
459; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
460; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
461; GCN-NEXT:    v_mov_b32_e32 v1, 0
462; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
463; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
464; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
465; GCN-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
466; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
467; GCN-NEXT:    s_endpgm
468;
469; GCN-IR-LABEL: s_test_urem31_i64:
470; GCN-IR:       ; %bb.0:
471; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xe
472; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
473; GCN-IR-NEXT:    s_lshr_b32 s4, s2, 1
474; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
475; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
476; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
477; GCN-IR-NEXT:    s_mov_b32 s2, -1
478; GCN-IR-NEXT:    s_lshr_b32 s5, s3, 1
479; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s5
480; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
481; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
482; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
483; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
484; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
485; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
486; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
487; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
488; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
489; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
490; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
491; GCN-IR-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
492; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
493; GCN-IR-NEXT:    s_endpgm
494  %1 = lshr i64 %x, 33
495  %2 = lshr i64 %y, 33
496  %result = urem i64 %1, %2
497  store i64 %result, i64 addrspace(1)* %out
498  ret void
499}
500
501define amdgpu_kernel void @s_test_urem31_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
502; GCN-LABEL: s_test_urem31_v2i64:
503; GCN:       ; %bb.0:
504; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
505; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
506; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
507; GCN-NEXT:    s_mov_b32 s7, 0xf000
508; GCN-NEXT:    s_mov_b32 s6, -1
509; GCN-NEXT:    s_waitcnt lgkmcnt(0)
510; GCN-NEXT:    s_lshr_b32 s2, s9, 1
511; GCN-NEXT:    s_lshr_b32 s0, s1, 1
512; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
513; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s2
514; GCN-NEXT:    s_lshr_b32 s3, s3, 1
515; GCN-NEXT:    v_cvt_f32_u32_e32 v4, s3
516; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
517; GCN-NEXT:    s_lshr_b32 s1, s11, 1
518; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s1
519; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
520; GCN-NEXT:    v_trunc_f32_e32 v2, v2
521; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
522; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
523; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v4
524; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
525; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
526; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
527; GCN-NEXT:    v_mul_f32_e32 v2, v3, v2
528; GCN-NEXT:    v_trunc_f32_e32 v2, v2
529; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
530; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
531; GCN-NEXT:    v_mad_f32 v2, -v2, v4, v3
532; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
533; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
534; GCN-NEXT:    v_mul_lo_u32 v2, v2, s3
535; GCN-NEXT:    v_mov_b32_e32 v1, 0
536; GCN-NEXT:    s_brev_b32 s0, -2
537; GCN-NEXT:    v_and_b32_e32 v0, s0, v0
538; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
539; GCN-NEXT:    v_and_b32_e32 v2, s0, v2
540; GCN-NEXT:    v_mov_b32_e32 v3, v1
541; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
542; GCN-NEXT:    s_endpgm
543;
544; GCN-IR-LABEL: s_test_urem31_v2i64:
545; GCN-IR:       ; %bb.0:
546; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
547; GCN-IR-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
548; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
549; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
550; GCN-IR-NEXT:    s_mov_b32 s6, -1
551; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
552; GCN-IR-NEXT:    s_lshr_b32 s2, s9, 1
553; GCN-IR-NEXT:    s_lshr_b32 s0, s1, 1
554; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
555; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s2
556; GCN-IR-NEXT:    s_lshr_b32 s3, s3, 1
557; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v4, s3
558; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
559; GCN-IR-NEXT:    s_lshr_b32 s1, s11, 1
560; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v3, s1
561; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
562; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
563; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
564; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
565; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v4
566; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
567; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
568; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
569; GCN-IR-NEXT:    v_mul_f32_e32 v2, v3, v2
570; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
571; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
572; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
573; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v4, v3
574; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
575; GCN-IR-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
576; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, s3
577; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
578; GCN-IR-NEXT:    s_brev_b32 s0, -2
579; GCN-IR-NEXT:    v_and_b32_e32 v0, s0, v0
580; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
581; GCN-IR-NEXT:    v_and_b32_e32 v2, s0, v2
582; GCN-IR-NEXT:    v_mov_b32_e32 v3, v1
583; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
584; GCN-IR-NEXT:    s_endpgm
585  %1 = lshr <2 x i64> %x, <i64 33, i64 33>
586  %2 = lshr <2 x i64> %y, <i64 33, i64 33>
587  %result = urem <2 x i64> %1, %2
588  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
589  ret void
590}
591
592define amdgpu_kernel void @s_test_urem24_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
593; GCN-LABEL: s_test_urem24_i64:
594; GCN:       ; %bb.0:
595; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
596; GCN-NEXT:    s_waitcnt lgkmcnt(0)
597; GCN-NEXT:    s_lshr_b32 s4, s2, 8
598; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
599; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
600; GCN-NEXT:    s_waitcnt lgkmcnt(0)
601; GCN-NEXT:    s_mov_b32 s2, -1
602; GCN-NEXT:    s_lshr_b32 s5, s3, 8
603; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s5
604; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
605; GCN-NEXT:    s_mov_b32 s3, 0xf000
606; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
607; GCN-NEXT:    v_trunc_f32_e32 v2, v2
608; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
609; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
610; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
611; GCN-NEXT:    v_mov_b32_e32 v1, 0
612; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
613; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
614; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
615; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
616; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
617; GCN-NEXT:    s_endpgm
618;
619; GCN-IR-LABEL: s_test_urem24_i64:
620; GCN-IR:       ; %bb.0:
621; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xe
622; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
623; GCN-IR-NEXT:    s_lshr_b32 s4, s2, 8
624; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
625; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
626; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
627; GCN-IR-NEXT:    s_mov_b32 s2, -1
628; GCN-IR-NEXT:    s_lshr_b32 s5, s3, 8
629; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s5
630; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
631; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
632; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
633; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
634; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
635; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
636; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
637; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
638; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
639; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
640; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
641; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
642; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
643; GCN-IR-NEXT:    s_endpgm
644  %1 = lshr i64 %x, 40
645  %2 = lshr i64 %y, 40
646  %result = urem i64 %1, %2
647  store i64 %result, i64 addrspace(1)* %out
648  ret void
649}
650
651define amdgpu_kernel void @s_test_urem23_64_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
652; GCN-LABEL: s_test_urem23_64_v2i64:
653; GCN:       ; %bb.0:
654; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
655; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
656; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
657; GCN-NEXT:    s_mov_b32 s7, 0xf000
658; GCN-NEXT:    s_mov_b32 s6, -1
659; GCN-NEXT:    s_waitcnt lgkmcnt(0)
660; GCN-NEXT:    s_lshr_b32 s2, s9, 1
661; GCN-NEXT:    s_lshr_b32 s0, s1, 1
662; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
663; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s2
664; GCN-NEXT:    s_lshr_b32 s3, s3, 9
665; GCN-NEXT:    v_cvt_f32_u32_e32 v4, s3
666; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
667; GCN-NEXT:    s_lshr_b32 s1, s11, 9
668; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s1
669; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
670; GCN-NEXT:    v_trunc_f32_e32 v2, v2
671; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
672; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
673; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v4
674; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
675; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
676; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
677; GCN-NEXT:    v_mul_f32_e32 v2, v3, v2
678; GCN-NEXT:    v_trunc_f32_e32 v2, v2
679; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
680; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
681; GCN-NEXT:    v_mad_f32 v2, -v2, v4, v3
682; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
683; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
684; GCN-NEXT:    v_mul_lo_u32 v2, v2, s3
685; GCN-NEXT:    v_mov_b32_e32 v1, 0
686; GCN-NEXT:    s_brev_b32 s0, -2
687; GCN-NEXT:    v_and_b32_e32 v0, s0, v0
688; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
689; GCN-NEXT:    v_and_b32_e32 v2, s0, v2
690; GCN-NEXT:    v_mov_b32_e32 v3, v1
691; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
692; GCN-NEXT:    s_endpgm
693;
694; GCN-IR-LABEL: s_test_urem23_64_v2i64:
695; GCN-IR:       ; %bb.0:
696; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
697; GCN-IR-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
698; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
699; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
700; GCN-IR-NEXT:    s_mov_b32 s6, -1
701; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
702; GCN-IR-NEXT:    s_lshr_b32 s2, s9, 1
703; GCN-IR-NEXT:    s_lshr_b32 s0, s1, 1
704; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
705; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s2
706; GCN-IR-NEXT:    s_lshr_b32 s3, s3, 9
707; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v4, s3
708; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
709; GCN-IR-NEXT:    s_lshr_b32 s1, s11, 9
710; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v3, s1
711; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
712; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
713; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
714; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
715; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v4
716; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
717; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
718; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
719; GCN-IR-NEXT:    v_mul_f32_e32 v2, v3, v2
720; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
721; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
722; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
723; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v4, v3
724; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
725; GCN-IR-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
726; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, s3
727; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
728; GCN-IR-NEXT:    s_brev_b32 s0, -2
729; GCN-IR-NEXT:    v_and_b32_e32 v0, s0, v0
730; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
731; GCN-IR-NEXT:    v_and_b32_e32 v2, s0, v2
732; GCN-IR-NEXT:    v_mov_b32_e32 v3, v1
733; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
734; GCN-IR-NEXT:    s_endpgm
735  %1 = lshr <2 x i64> %x, <i64 33, i64 41>
736  %2 = lshr <2 x i64> %y, <i64 33, i64 41>
737  %result = urem <2 x i64> %1, %2
738  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
739  ret void
740}
741
742define amdgpu_kernel void @s_test_urem_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
743; GCN-LABEL: s_test_urem_k_num_i64:
744; GCN:       ; %bb.0:
745; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
746; GCN-NEXT:    v_mov_b32_e32 v2, 0
747; GCN-NEXT:    s_mov_b32 s11, 0xf000
748; GCN-NEXT:    s_mov_b32 s10, -1
749; GCN-NEXT:    s_waitcnt lgkmcnt(0)
750; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s6
751; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s7
752; GCN-NEXT:    s_sub_u32 s2, 0, s6
753; GCN-NEXT:    s_subb_u32 s3, 0, s7
754; GCN-NEXT:    s_mov_b32 s8, s4
755; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
756; GCN-NEXT:    v_rcp_f32_e32 v0, v0
757; GCN-NEXT:    v_mov_b32_e32 v1, 0
758; GCN-NEXT:    s_mov_b32 s9, s5
759; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
760; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
761; GCN-NEXT:    v_trunc_f32_e32 v3, v3
762; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
763; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
764; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
765; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
766; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
767; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
768; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
769; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
770; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
771; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
772; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
773; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
774; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
775; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
776; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
777; GCN-NEXT:    v_mul_hi_u32 v10, v3, v4
778; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
779; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
780; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
781; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
782; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
783; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
784; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
785; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
786; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
787; GCN-NEXT:    v_mul_lo_u32 v6, s2, v4
788; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
789; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
790; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
791; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
792; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
793; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
794; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
795; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
796; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
797; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
798; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
799; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
800; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
801; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
802; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
803; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
804; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
805; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
806; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
807; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
808; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
809; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
810; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
811; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
812; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
813; GCN-NEXT:    v_mul_hi_u32 v3, v3, 24
814; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
815; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v2, v3, vcc
816; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
817; GCN-NEXT:    v_mul_lo_u32 v1, s6, v1
818; GCN-NEXT:    v_mul_hi_u32 v2, s6, v0
819; GCN-NEXT:    v_mul_lo_u32 v3, s7, v0
820; GCN-NEXT:    v_mul_lo_u32 v0, s6, v0
821; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
822; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
823; GCN-NEXT:    v_sub_i32_e64 v0, s[0:1], 24, v0
824; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
825; GCN-NEXT:    v_mov_b32_e32 v3, s7
826; GCN-NEXT:    v_subb_u32_e64 v2, vcc, v2, v3, s[0:1]
827; GCN-NEXT:    v_subrev_i32_e64 v4, s[2:3], s6, v0
828; GCN-NEXT:    v_subbrev_u32_e64 v5, vcc, 0, v2, s[2:3]
829; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s7, v5
830; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
831; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s6, v4
832; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
833; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s7, v5
834; GCN-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc
835; GCN-NEXT:    v_subb_u32_e64 v2, vcc, v2, v3, s[2:3]
836; GCN-NEXT:    v_subrev_i32_e32 v3, vcc, s6, v4
837; GCN-NEXT:    v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
838; GCN-NEXT:    v_subb_u32_e64 v1, vcc, 0, v1, s[0:1]
839; GCN-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v6
840; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
841; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[2:3]
842; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
843; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
844; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
845; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s7, v1
846; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
847; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
848; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
849; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[2:3]
850; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
851; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
852; GCN-NEXT:    s_endpgm
853;
854; GCN-IR-LABEL: s_test_urem_k_num_i64:
855; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
856; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
857; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
858; GCN-IR-NEXT:    s_flbit_i32_b32 s4, s2
859; GCN-IR-NEXT:    s_add_i32 s4, s4, 32
860; GCN-IR-NEXT:    s_flbit_i32_b32 s5, s3
861; GCN-IR-NEXT:    s_cmp_eq_u32 s3, 0
862; GCN-IR-NEXT:    s_cselect_b32 s8, s4, s5
863; GCN-IR-NEXT:    s_add_u32 s6, s8, 0xffffffc5
864; GCN-IR-NEXT:    s_addc_u32 s7, 0, -1
865; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
866; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[6:7], 63
867; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0
868; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
869; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[6:7], 63
870; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
871; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
872; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
873; GCN-IR-NEXT:    s_cbranch_vccz BB6_5
874; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
875; GCN-IR-NEXT:    s_add_u32 s12, s6, 1
876; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
877; GCN-IR-NEXT:    s_addc_u32 s13, s7, 0
878; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
879; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[12:13], v[0:1]
880; GCN-IR-NEXT:    s_sub_i32 s6, 63, s6
881; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
882; GCN-IR-NEXT:    s_lshl_b64 s[10:11], 24, s6
883; GCN-IR-NEXT:    s_cbranch_vccz BB6_4
884; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
885; GCN-IR-NEXT:    s_lshr_b64 s[14:15], 24, s12
886; GCN-IR-NEXT:    s_add_u32 s6, s2, -1
887; GCN-IR-NEXT:    s_addc_u32 s7, s3, -1
888; GCN-IR-NEXT:    s_sub_u32 s8, 58, s8
889; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
890; GCN-IR-NEXT:    s_mov_b64 s[12:13], 0
891; GCN-IR-NEXT:    s_mov_b32 s5, 0
892; GCN-IR-NEXT:  BB6_3: ; %udiv-do-while
893; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
894; GCN-IR-NEXT:    s_lshr_b32 s4, s11, 31
895; GCN-IR-NEXT:    s_lshl_b64 s[14:15], s[14:15], 1
896; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
897; GCN-IR-NEXT:    s_or_b64 s[14:15], s[14:15], s[4:5]
898; GCN-IR-NEXT:    s_or_b64 s[10:11], s[12:13], s[10:11]
899; GCN-IR-NEXT:    s_sub_u32 s4, s6, s14
900; GCN-IR-NEXT:    s_subb_u32 s4, s7, s15
901; GCN-IR-NEXT:    s_ashr_i32 s12, s4, 31
902; GCN-IR-NEXT:    s_mov_b32 s13, s12
903; GCN-IR-NEXT:    s_and_b32 s4, s12, 1
904; GCN-IR-NEXT:    s_and_b64 s[16:17], s[12:13], s[2:3]
905; GCN-IR-NEXT:    s_sub_u32 s14, s14, s16
906; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
907; GCN-IR-NEXT:    s_subb_u32 s15, s15, s17
908; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
909; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
910; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
911; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]
912; GCN-IR-NEXT:    s_mov_b64 s[12:13], s[4:5]
913; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
914; GCN-IR-NEXT:    s_cbranch_vccz BB6_3
915; GCN-IR-NEXT:  BB6_4: ; %Flow5
916; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[10:11], 1
917; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], s[6:7]
918; GCN-IR-NEXT:    v_mov_b32_e32 v0, s4
919; GCN-IR-NEXT:    v_mov_b32_e32 v1, s5
920; GCN-IR-NEXT:    s_branch BB6_6
921; GCN-IR-NEXT:  BB6_5:
922; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
923; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[10:11]
924; GCN-IR-NEXT:  BB6_6: ; %udiv-end
925; GCN-IR-NEXT:    v_mul_lo_u32 v1, s2, v1
926; GCN-IR-NEXT:    v_mul_hi_u32 v2, s2, v0
927; GCN-IR-NEXT:    v_mul_lo_u32 v3, s3, v0
928; GCN-IR-NEXT:    v_mul_lo_u32 v0, s2, v0
929; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
930; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
931; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
932; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
933; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
934; GCN-IR-NEXT:    s_mov_b32 s2, -1
935; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
936; GCN-IR-NEXT:    s_endpgm
937  %result = urem i64 24, %x
938  store i64 %result, i64 addrspace(1)* %out
939  ret void
940}
941
942define amdgpu_kernel void @s_test_urem_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
943; GCN-LABEL: s_test_urem_k_den_i64:
944; GCN:       ; %bb.0:
945; GCN-NEXT:    v_mov_b32_e32 v0, 0x4f800000
946; GCN-NEXT:    v_madak_f32 v0, 0, v0, 0x41c00000
947; GCN-NEXT:    v_rcp_f32_e32 v0, v0
948; GCN-NEXT:    s_movk_i32 s2, 0xffe8
949; GCN-NEXT:    v_mov_b32_e32 v8, 0
950; GCN-NEXT:    v_mov_b32_e32 v7, 0
951; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
952; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
953; GCN-NEXT:    v_trunc_f32_e32 v1, v1
954; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
955; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
956; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
957; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
958; GCN-NEXT:    s_mov_b32 s7, 0xf000
959; GCN-NEXT:    v_mul_hi_u32 v2, v0, s2
960; GCN-NEXT:    v_mul_lo_u32 v3, v1, s2
961; GCN-NEXT:    v_mul_lo_u32 v4, v0, s2
962; GCN-NEXT:    s_mov_b32 s6, -1
963; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
964; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
965; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
966; GCN-NEXT:    v_mul_hi_u32 v6, v0, v4
967; GCN-NEXT:    v_mul_hi_u32 v3, v0, v2
968; GCN-NEXT:    v_mul_hi_u32 v9, v1, v2
969; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
970; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
971; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
972; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
973; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v3, vcc
974; GCN-NEXT:    s_waitcnt lgkmcnt(0)
975; GCN-NEXT:    s_mov_b32 s4, s8
976; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
977; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
978; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
979; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
980; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
981; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
982; GCN-NEXT:    v_mul_hi_u32 v4, v0, s2
983; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
984; GCN-NEXT:    v_mul_lo_u32 v5, v2, s2
985; GCN-NEXT:    v_mul_lo_u32 v6, v0, s2
986; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v0, v4
987; GCN-NEXT:    s_mov_b32 s5, s9
988; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
989; GCN-NEXT:    v_mul_lo_u32 v5, v0, v4
990; GCN-NEXT:    v_mul_hi_u32 v9, v0, v6
991; GCN-NEXT:    v_mul_hi_u32 v10, v0, v4
992; GCN-NEXT:    v_mul_hi_u32 v11, v2, v4
993; GCN-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
994; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v8, v10, vcc
995; GCN-NEXT:    v_mul_lo_u32 v10, v2, v6
996; GCN-NEXT:    v_mul_hi_u32 v6, v2, v6
997; GCN-NEXT:    v_mul_lo_u32 v2, v2, v4
998; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v10
999; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v6, vcc
1000; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v11, v7, vcc
1001; GCN-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
1002; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
1003; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
1004; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
1005; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
1006; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
1007; GCN-NEXT:    v_mul_lo_u32 v2, s10, v1
1008; GCN-NEXT:    v_mul_hi_u32 v3, s10, v0
1009; GCN-NEXT:    v_mul_hi_u32 v4, s10, v1
1010; GCN-NEXT:    v_mul_hi_u32 v5, s11, v1
1011; GCN-NEXT:    v_mul_lo_u32 v1, s11, v1
1012; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1013; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
1014; GCN-NEXT:    v_mul_lo_u32 v4, s11, v0
1015; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
1016; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
1017; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
1018; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
1019; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
1020; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v8, v2, vcc
1021; GCN-NEXT:    v_mul_hi_u32 v2, v0, 24
1022; GCN-NEXT:    v_mul_lo_u32 v1, v1, 24
1023; GCN-NEXT:    v_mul_lo_u32 v0, v0, 24
1024; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1025; GCN-NEXT:    v_mov_b32_e32 v2, s11
1026; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s10, v0
1027; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1028; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v0
1029; GCN-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v1, vcc
1030; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v2
1031; GCN-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v3, vcc
1032; GCN-NEXT:    v_cmp_lt_u32_e32 vcc, 23, v2
1033; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1034; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
1035; GCN-NEXT:    v_cndmask_b32_e32 v6, -1, v6, vcc
1036; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
1037; GCN-NEXT:    v_cmp_lt_u32_e32 vcc, 23, v0
1038; GCN-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
1039; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
1040; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
1041; GCN-NEXT:    v_cndmask_b32_e32 v5, -1, v5, vcc
1042; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
1043; GCN-NEXT:    v_cndmask_b32_e64 v2, v2, v4, s[0:1]
1044; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
1045; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
1046; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1047; GCN-NEXT:    s_endpgm
1048;
1049; GCN-IR-LABEL: s_test_urem_k_den_i64:
1050; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1051; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1052; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1053; GCN-IR-NEXT:    s_flbit_i32_b32 s4, s2
1054; GCN-IR-NEXT:    s_add_i32 s4, s4, 32
1055; GCN-IR-NEXT:    s_flbit_i32_b32 s5, s3
1056; GCN-IR-NEXT:    s_cmp_eq_u32 s3, 0
1057; GCN-IR-NEXT:    s_cselect_b32 s6, s4, s5
1058; GCN-IR-NEXT:    s_sub_u32 s8, 59, s6
1059; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
1060; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
1061; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[8:9], 63
1062; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0
1063; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
1064; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[8:9], 63
1065; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
1066; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
1067; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
1068; GCN-IR-NEXT:    s_cbranch_vccz BB7_5
1069; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1070; GCN-IR-NEXT:    s_add_u32 s10, s8, 1
1071; GCN-IR-NEXT:    v_mov_b32_e32 v0, s8
1072; GCN-IR-NEXT:    s_addc_u32 s11, s9, 0
1073; GCN-IR-NEXT:    v_mov_b32_e32 v1, s9
1074; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
1075; GCN-IR-NEXT:    s_sub_i32 s7, 63, s8
1076; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, vcc
1077; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[2:3], s7
1078; GCN-IR-NEXT:    s_cbranch_vccz BB7_4
1079; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1080; GCN-IR-NEXT:    s_lshr_b64 s[12:13], s[2:3], s10
1081; GCN-IR-NEXT:    s_add_u32 s6, s6, 0xffffffc4
1082; GCN-IR-NEXT:    s_addc_u32 s7, 0, -1
1083; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1084; GCN-IR-NEXT:    s_mov_b32 s5, 0
1085; GCN-IR-NEXT:  BB7_3: ; %udiv-do-while
1086; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1087; GCN-IR-NEXT:    s_lshr_b32 s4, s9, 31
1088; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
1089; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
1090; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[4:5]
1091; GCN-IR-NEXT:    s_or_b64 s[8:9], s[10:11], s[8:9]
1092; GCN-IR-NEXT:    s_sub_u32 s4, 23, s12
1093; GCN-IR-NEXT:    s_subb_u32 s4, 0, s13
1094; GCN-IR-NEXT:    s_ashr_i32 s10, s4, 31
1095; GCN-IR-NEXT:    s_and_b32 s4, s10, 1
1096; GCN-IR-NEXT:    s_and_b32 s10, s10, 24
1097; GCN-IR-NEXT:    s_sub_u32 s12, s12, s10
1098; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
1099; GCN-IR-NEXT:    s_subb_u32 s13, s13, 0
1100; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
1101; GCN-IR-NEXT:    s_add_u32 s6, s6, 1
1102; GCN-IR-NEXT:    s_addc_u32 s7, s7, 0
1103; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
1104; GCN-IR-NEXT:    s_mov_b64 s[10:11], s[4:5]
1105; GCN-IR-NEXT:    s_and_b64 vcc, exec, vcc
1106; GCN-IR-NEXT:    s_cbranch_vccz BB7_3
1107; GCN-IR-NEXT:  BB7_4: ; %Flow5
1108; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[8:9], 1
1109; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], s[6:7]
1110; GCN-IR-NEXT:    v_mov_b32_e32 v0, s4
1111; GCN-IR-NEXT:    v_mov_b32_e32 v1, s5
1112; GCN-IR-NEXT:    s_branch BB7_6
1113; GCN-IR-NEXT:  BB7_5:
1114; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
1115; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[10:11]
1116; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1117; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[10:11]
1118; GCN-IR-NEXT:  BB7_6: ; %udiv-end
1119; GCN-IR-NEXT:    v_mul_hi_u32 v2, v0, 24
1120; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, 24
1121; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, 24
1122; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1123; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1124; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1125; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1126; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1127; GCN-IR-NEXT:    s_mov_b32 s2, -1
1128; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1129; GCN-IR-NEXT:    s_endpgm
1130  %result = urem i64 %x, 24
1131  store i64 %result, i64 addrspace(1)* %out
1132  ret void
1133}
1134
1135; FIXME: Constant bus violation
1136; define i64 @v_test_urem_k_num_i64(i64 %x) {
1137;   %result = urem i64 24, %x
1138;   ret i64 %result
1139; }
1140
1141define i64 @v_test_urem_pow2_k_num_i64(i64 %x) {
1142; GCN-LABEL: v_test_urem_pow2_k_num_i64:
1143; GCN:       ; %bb.0:
1144; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1145; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1146; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1147; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1148; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1149; GCN-NEXT:    v_mov_b32_e32 v12, 0
1150; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1151; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1152; GCN-NEXT:    v_mov_b32_e32 v11, 0
1153; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1154; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1155; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1156; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1157; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1158; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1159; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1160; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1161; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1162; GCN-NEXT:    v_mul_lo_u32 v9, v4, v2
1163; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1164; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1165; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
1166; GCN-NEXT:    v_mul_hi_u32 v10, v2, v9
1167; GCN-NEXT:    v_mul_hi_u32 v7, v2, v6
1168; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
1169; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1170; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
1171; GCN-NEXT:    v_mul_lo_u32 v10, v3, v9
1172; GCN-NEXT:    v_mul_hi_u32 v9, v3, v9
1173; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v7, vcc
1174; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
1175; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
1176; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v11, vcc
1177; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1178; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v6
1179; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v8, vcc
1180; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v3, v7, s[4:5]
1181; GCN-NEXT:    v_mul_lo_u32 v8, v4, v6
1182; GCN-NEXT:    v_mul_hi_u32 v9, v4, v2
1183; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1184; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1185; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1186; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
1187; GCN-NEXT:    v_mul_lo_u32 v10, v2, v5
1188; GCN-NEXT:    v_mul_hi_u32 v13, v2, v4
1189; GCN-NEXT:    v_mul_hi_u32 v14, v2, v5
1190; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
1191; GCN-NEXT:    v_mul_lo_u32 v4, v6, v4
1192; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v10
1193; GCN-NEXT:    v_mul_hi_u32 v8, v6, v5
1194; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v12, v14, vcc
1195; GCN-NEXT:    v_mul_lo_u32 v5, v6, v5
1196; GCN-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
1197; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v13, v9, vcc
1198; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v11, vcc
1199; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1200; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
1201; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
1202; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
1203; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1204; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
1205; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1206; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
1207; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1208; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
1209; GCN-NEXT:    s_mov_b32 s4, 0x8000
1210; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1211; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1212; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s4, v2
1213; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1214; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
1215; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1216; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
1217; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1218; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
1219; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1220; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1
1221; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1222; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1223; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1224; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v0
1225; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1226; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1227; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1228; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1229; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1230; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1231; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1232; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
1233; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1234; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1235; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1236; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1237; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1238; GCN-NEXT:    s_setpc_b64 s[30:31]
1239;
1240; GCN-IR-LABEL: v_test_urem_pow2_k_num_i64:
1241; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1242; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1243; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1244; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1245; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1246; GCN-IR-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
1247; GCN-IR-NEXT:    v_cndmask_b32_e32 v8, v3, v2, vcc
1248; GCN-IR-NEXT:    s_movk_i32 s6, 0xffd0
1249; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, s6, v8
1250; GCN-IR-NEXT:    v_addc_u32_e64 v3, s[6:7], 0, -1, vcc
1251; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1252; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[2:3]
1253; GCN-IR-NEXT:    s_mov_b32 s8, 0x8000
1254; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1255; GCN-IR-NEXT:    v_mov_b32_e32 v4, s8
1256; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[2:3]
1257; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
1258; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v4, 0, s[4:5]
1259; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1260; GCN-IR-NEXT:    s_mov_b32 s9, 0
1261; GCN-IR-NEXT:    v_mov_b32_e32 v5, v9
1262; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1263; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1264; GCN-IR-NEXT:    s_cbranch_execz BB8_6
1265; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1266; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 1, v2
1267; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, 0, v3, vcc
1268; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[6:7], v[2:3]
1269; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v2
1270; GCN-IR-NEXT:    v_lshl_b64 v[2:3], s[8:9], v2
1271; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1272; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1273; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1274; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1275; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
1276; GCN-IR-NEXT:    s_cbranch_execz BB8_5
1277; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1278; GCN-IR-NEXT:    s_mov_b32 s5, 0
1279; GCN-IR-NEXT:    s_mov_b32 s4, 0x8000
1280; GCN-IR-NEXT:    v_lshr_b64 v[10:11], s[4:5], v6
1281; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, -1, v0
1282; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, -1, v1, vcc
1283; GCN-IR-NEXT:    v_sub_i32_e32 v8, vcc, 47, v8
1284; GCN-IR-NEXT:    v_mov_b32_e32 v12, 0
1285; GCN-IR-NEXT:    v_subb_u32_e32 v9, vcc, 0, v9, vcc
1286; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1287; GCN-IR-NEXT:  BB8_3: ; %udiv-do-while
1288; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1289; GCN-IR-NEXT:    v_lshl_b64 v[10:11], v[10:11], 1
1290; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1291; GCN-IR-NEXT:    v_or_b32_e32 v10, v10, v4
1292; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1293; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, v6, v10
1294; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, v7, v11, vcc
1295; GCN-IR-NEXT:    v_or_b32_e32 v2, v12, v2
1296; GCN-IR-NEXT:    v_ashrrev_i32_e32 v12, 31, v4
1297; GCN-IR-NEXT:    v_and_b32_e32 v15, v12, v0
1298; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v12
1299; GCN-IR-NEXT:    v_and_b32_e32 v14, v12, v1
1300; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
1301; GCN-IR-NEXT:    v_or_b32_e32 v3, v13, v3
1302; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
1303; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9]
1304; GCN-IR-NEXT:    v_mov_b32_e32 v8, v12
1305; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1306; GCN-IR-NEXT:    v_sub_i32_e64 v10, s[4:5], v10, v15
1307; GCN-IR-NEXT:    v_mov_b32_e32 v9, v13
1308; GCN-IR-NEXT:    v_mov_b32_e32 v13, v5
1309; GCN-IR-NEXT:    v_subb_u32_e64 v11, s[4:5], v11, v14, s[4:5]
1310; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
1311; GCN-IR-NEXT:    v_mov_b32_e32 v12, v4
1312; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
1313; GCN-IR-NEXT:    s_cbranch_execnz BB8_3
1314; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1315; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1316; GCN-IR-NEXT:  BB8_5: ; %Flow3
1317; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1318; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1319; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1320; GCN-IR-NEXT:    v_or_b32_e32 v4, v4, v2
1321; GCN-IR-NEXT:  BB8_6: ; %Flow4
1322; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1323; GCN-IR-NEXT:    v_mul_lo_u32 v2, v0, v5
1324; GCN-IR-NEXT:    v_mul_hi_u32 v3, v0, v4
1325; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v4
1326; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v4
1327; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1328; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1329; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1330; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1331; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1332  %result = urem i64 32768, %x
1333  ret i64 %result
1334}
1335
1336define i64 @v_test_urem_pow2_k_den_i64(i64 %x) {
1337; GCN-LABEL: v_test_urem_pow2_k_den_i64:
1338; GCN:       ; %bb.0:
1339; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1340; GCN-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
1341; GCN-NEXT:    v_mov_b32_e32 v1, 0
1342; GCN-NEXT:    s_setpc_b64 s[30:31]
1343;
1344; GCN-IR-LABEL: v_test_urem_pow2_k_den_i64:
1345; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1346; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1347; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1348; GCN-IR-NEXT:    v_add_i32_e64 v2, s[4:5], 32, v2
1349; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1350; GCN-IR-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v1
1351; GCN-IR-NEXT:    v_cndmask_b32_e64 v6, v3, v2, s[4:5]
1352; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 48, v6
1353; GCN-IR-NEXT:    v_subb_u32_e64 v3, s[4:5], 0, 0, s[4:5]
1354; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1355; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[2:3]
1356; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1357; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[2:3]
1358; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1359; GCN-IR-NEXT:    v_cndmask_b32_e64 v5, v1, 0, s[4:5]
1360; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v0, 0, s[4:5]
1361; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1362; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1363; GCN-IR-NEXT:    s_cbranch_execz BB9_6
1364; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1365; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 1, v2
1366; GCN-IR-NEXT:    v_addc_u32_e32 v8, vcc, 0, v3, vcc
1367; GCN-IR-NEXT:    v_cmp_ge_u64_e32 vcc, v[7:8], v[2:3]
1368; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v2
1369; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1370; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[0:1], v2
1371; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0
1372; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1373; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1374; GCN-IR-NEXT:    s_xor_b64 s[10:11], exec, s[4:5]
1375; GCN-IR-NEXT:    s_cbranch_execz BB9_5
1376; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1377; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1378; GCN-IR-NEXT:    v_lshr_b64 v[8:9], v[0:1], v7
1379; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 0xffffffcf, v6
1380; GCN-IR-NEXT:    v_addc_u32_e64 v7, s[4:5], 0, -1, vcc
1381; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1382; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1383; GCN-IR-NEXT:  BB9_3: ; %udiv-do-while
1384; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1385; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1386; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1387; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1388; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1389; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, s12, v8
1390; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, 0, v9, vcc
1391; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1392; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1393; GCN-IR-NEXT:    v_and_b32_e32 v12, 0x8000, v10
1394; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1395; GCN-IR-NEXT:    v_add_i32_e32 v10, vcc, 1, v6
1396; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1397; GCN-IR-NEXT:    v_addc_u32_e32 v11, vcc, 0, v7, vcc
1398; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7]
1399; GCN-IR-NEXT:    v_mov_b32_e32 v6, v10
1400; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1401; GCN-IR-NEXT:    v_mov_b32_e32 v7, v11
1402; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1403; GCN-IR-NEXT:    v_mov_b32_e32 v13, 0
1404; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v12
1405; GCN-IR-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v13, s[4:5]
1406; GCN-IR-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
1407; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1408; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[8:9]
1409; GCN-IR-NEXT:    s_cbranch_execnz BB9_3
1410; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1411; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1412; GCN-IR-NEXT:  BB9_5: ; %Flow3
1413; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1414; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1415; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1416; GCN-IR-NEXT:    v_or_b32_e32 v4, v4, v2
1417; GCN-IR-NEXT:  BB9_6: ; %Flow4
1418; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1419; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[4:5], 15
1420; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1421; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1422; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1423  %result = urem i64 %x, 32768
1424  ret i64 %result
1425}
1426
1427define amdgpu_kernel void @s_test_urem24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1428; GCN-LABEL: s_test_urem24_k_num_i64:
1429; GCN:       ; %bb.0:
1430; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1431; GCN-NEXT:    s_mov_b32 s5, 0x41c00000
1432; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1433; GCN-NEXT:    s_mov_b32 s2, -1
1434; GCN-NEXT:    s_lshr_b32 s4, s3, 8
1435; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
1436; GCN-NEXT:    s_mov_b32 s3, 0xf000
1437; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1438; GCN-NEXT:    v_mul_f32_e32 v1, s5, v1
1439; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1440; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1441; GCN-NEXT:    v_mad_f32 v1, -v1, v0, s5
1442; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1443; GCN-NEXT:    v_mov_b32_e32 v1, 0
1444; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1445; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
1446; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1447; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1448; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1449; GCN-NEXT:    s_endpgm
1450;
1451; GCN-IR-LABEL: s_test_urem24_k_num_i64:
1452; GCN-IR:       ; %bb.0:
1453; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1454; GCN-IR-NEXT:    s_mov_b32 s5, 0x41c00000
1455; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1456; GCN-IR-NEXT:    s_mov_b32 s2, -1
1457; GCN-IR-NEXT:    s_lshr_b32 s4, s3, 8
1458; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
1459; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1460; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1461; GCN-IR-NEXT:    v_mul_f32_e32 v1, s5, v1
1462; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1463; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1464; GCN-IR-NEXT:    v_mad_f32 v1, -v1, v0, s5
1465; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1466; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1467; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1468; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
1469; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1470; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1471; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1472; GCN-IR-NEXT:    s_endpgm
1473  %x.shr = lshr i64 %x, 40
1474  %result = urem i64 24, %x.shr
1475  store i64 %result, i64 addrspace(1)* %out
1476  ret void
1477}
1478
1479define amdgpu_kernel void @s_test_urem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1480; GCN-LABEL: s_test_urem24_k_den_i64:
1481; GCN:       ; %bb.0:
1482; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1483; GCN-NEXT:    s_mov_b32 s1, 0x46b6fe00
1484; GCN-NEXT:    s_movk_i32 s0, 0x5b7f
1485; GCN-NEXT:    s_mov_b32 s3, 0xf000
1486; GCN-NEXT:    s_mov_b32 s2, -1
1487; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1488; GCN-NEXT:    s_lshr_b32 s6, s7, 8
1489; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s6
1490; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1491; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1492; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1493; GCN-NEXT:    v_mad_f32 v0, -v1, s1, v0
1494; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s1
1495; GCN-NEXT:    s_mov_b32 s1, s5
1496; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1497; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
1498; GCN-NEXT:    s_mov_b32 s0, s4
1499; GCN-NEXT:    v_mov_b32_e32 v1, 0
1500; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
1501; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1502; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1503; GCN-NEXT:    s_endpgm
1504;
1505; GCN-IR-LABEL: s_test_urem24_k_den_i64:
1506; GCN-IR:       ; %bb.0:
1507; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
1508; GCN-IR-NEXT:    s_mov_b32 s1, 0x46b6fe00
1509; GCN-IR-NEXT:    s_movk_i32 s0, 0x5b7f
1510; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1511; GCN-IR-NEXT:    s_mov_b32 s2, -1
1512; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1513; GCN-IR-NEXT:    s_lshr_b32 s6, s7, 8
1514; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s6
1515; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1516; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1517; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1518; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s1, v0
1519; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s1
1520; GCN-IR-NEXT:    s_mov_b32 s1, s5
1521; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1522; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
1523; GCN-IR-NEXT:    s_mov_b32 s0, s4
1524; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1525; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
1526; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1527; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1528; GCN-IR-NEXT:    s_endpgm
1529  %x.shr = lshr i64 %x, 40
1530  %result = urem i64 %x.shr, 23423
1531  store i64 %result, i64 addrspace(1)* %out
1532  ret void
1533}
1534
1535define i64 @v_test_urem24_k_num_i64(i64 %x) {
1536; GCN-LABEL: v_test_urem24_k_num_i64:
1537; GCN:       ; %bb.0:
1538; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1539; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1540; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v0
1541; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
1542; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1543; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
1544; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1545; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
1546; GCN-NEXT:    v_mad_f32 v2, -v2, v1, s4
1547; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1548; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1549; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
1550; GCN-NEXT:    v_mov_b32_e32 v1, 0
1551; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1552; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1553; GCN-NEXT:    s_setpc_b64 s[30:31]
1554;
1555; GCN-IR-LABEL: v_test_urem24_k_num_i64:
1556; GCN-IR:       ; %bb.0:
1557; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1558; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1559; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, v0
1560; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
1561; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1562; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
1563; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1564; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
1565; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v1, s4
1566; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1567; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1568; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
1569; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1570; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1571; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1572; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1573  %x.shr = lshr i64 %x, 40
1574  %result = urem i64 24, %x.shr
1575  ret i64 %result
1576}
1577
1578define i64 @v_test_urem24_pow2_k_num_i64(i64 %x) {
1579; GCN-LABEL: v_test_urem24_pow2_k_num_i64:
1580; GCN:       ; %bb.0:
1581; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1582; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1583; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v0
1584; GCN-NEXT:    s_mov_b32 s4, 0x47000000
1585; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1586; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
1587; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1588; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
1589; GCN-NEXT:    v_mad_f32 v2, -v2, v1, s4
1590; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1591; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1592; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
1593; GCN-NEXT:    v_mov_b32_e32 v1, 0
1594; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1595; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1596; GCN-NEXT:    s_setpc_b64 s[30:31]
1597;
1598; GCN-IR-LABEL: v_test_urem24_pow2_k_num_i64:
1599; GCN-IR:       ; %bb.0:
1600; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1601; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1602; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, v0
1603; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
1604; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1605; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
1606; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1607; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
1608; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v1, s4
1609; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1610; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1611; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
1612; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1613; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1614; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1615; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1616  %x.shr = lshr i64 %x, 40
1617  %result = urem i64 32768, %x.shr
1618  ret i64 %result
1619}
1620
1621define i64 @v_test_urem24_pow2_k_den_i64(i64 %x) {
1622; GCN-LABEL: v_test_urem24_pow2_k_den_i64:
1623; GCN:       ; %bb.0:
1624; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1625; GCN-NEXT:    v_bfe_u32 v0, v1, 8, 15
1626; GCN-NEXT:    v_mov_b32_e32 v1, 0
1627; GCN-NEXT:    s_setpc_b64 s[30:31]
1628;
1629; GCN-IR-LABEL: v_test_urem24_pow2_k_den_i64:
1630; GCN-IR:       ; %bb.0:
1631; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1632; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1633; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, v0
1634; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
1635; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38000000, v1
1636; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1637; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
1638; GCN-IR-NEXT:    v_mad_f32 v1, -v2, s4, v1
1639; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
1640; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1641; GCN-IR-NEXT:    v_lshlrev_b32_e32 v1, 15, v1
1642; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
1643; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1644; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1645; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1646  %x.shr = lshr i64 %x, 40
1647  %result = urem i64 %x.shr, 32768
1648  ret i64 %result
1649}
1650