1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
4
5define amdgpu_kernel void @s_test_urem_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
6; GCN-LABEL: s_test_urem_i64:
7; GCN:       ; %bb.0:
8; GCN-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
9; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
10; GCN-NEXT:    s_mov_b32 s7, 0xf000
11; GCN-NEXT:    s_mov_b32 s6, -1
12; GCN-NEXT:    s_waitcnt lgkmcnt(0)
13; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
14; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
15; GCN-NEXT:    s_sub_u32 s0, 0, s12
16; GCN-NEXT:    s_subb_u32 s1, 0, s13
17; GCN-NEXT:    s_mov_b32 s4, s8
18; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
19; GCN-NEXT:    v_rcp_f32_e32 v0, v0
20; GCN-NEXT:    v_mov_b32_e32 v1, 0
21; GCN-NEXT:    s_mov_b32 s5, s9
22; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
23; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
24; GCN-NEXT:    v_trunc_f32_e32 v2, v2
25; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
26; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
27; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
28; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
29; GCN-NEXT:    v_mul_hi_u32 v4, s0, v0
30; GCN-NEXT:    v_mul_lo_u32 v6, s1, v0
31; GCN-NEXT:    v_mul_lo_u32 v5, s0, v0
32; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
33; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
34; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
35; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
36; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
37; GCN-NEXT:    v_mul_lo_u32 v7, v2, v5
38; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
39; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
40; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
41; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
42; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
43; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
44; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
45; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
46; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
47; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
48; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
49; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
50; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
51; GCN-NEXT:    v_mul_hi_u32 v4, s0, v0
52; GCN-NEXT:    v_mul_lo_u32 v5, s1, v0
53; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
54; GCN-NEXT:    v_mul_lo_u32 v4, s0, v0
55; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
56; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
57; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
58; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
59; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
60; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
61; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
62; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
63; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
64; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
65; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
66; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
67; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v1, vcc
68; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
69; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
70; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
71; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
72; GCN-NEXT:    v_mul_lo_u32 v3, s10, v2
73; GCN-NEXT:    v_mul_hi_u32 v4, s10, v0
74; GCN-NEXT:    v_mul_hi_u32 v5, s10, v2
75; GCN-NEXT:    v_mul_hi_u32 v6, s11, v2
76; GCN-NEXT:    v_mul_lo_u32 v2, s11, v2
77; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
78; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
79; GCN-NEXT:    v_mul_lo_u32 v5, s11, v0
80; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
81; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
82; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
83; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
84; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
85; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
86; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
87; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
88; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
89; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
90; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
91; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
92; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
93; GCN-NEXT:    v_mov_b32_e32 v3, s13
94; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s10, v0
95; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
96; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
97; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
98; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
99; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
100; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
101; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
102; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
103; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
104; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
105; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
106; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
107; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
108; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
109; GCN-NEXT:    v_mov_b32_e32 v5, s11
110; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
111; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
112; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
113; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
114; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
115; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
116; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
117; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
118; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
119; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
120; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
121; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
122; GCN-NEXT:    s_endpgm
123;
124; GCN-IR-LABEL: s_test_urem_i64:
125; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
126; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
127; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
128; GCN-IR-NEXT:    s_mov_b64 s[6:7], 0
129; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
130; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[4:5], 0
131; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
132; GCN-IR-NEXT:    s_flbit_i32_b32 s12, s4
133; GCN-IR-NEXT:    s_add_i32 s14, s12, 32
134; GCN-IR-NEXT:    s_or_b64 s[12:13], s[8:9], s[10:11]
135; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s5
136; GCN-IR-NEXT:    s_min_u32 s10, s14, s8
137; GCN-IR-NEXT:    s_flbit_i32_b32 s8, s2
138; GCN-IR-NEXT:    s_add_i32 s8, s8, 32
139; GCN-IR-NEXT:    s_flbit_i32_b32 s9, s3
140; GCN-IR-NEXT:    s_min_u32 s14, s8, s9
141; GCN-IR-NEXT:    s_sub_u32 s8, s10, s14
142; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
143; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[16:17], s[8:9], 63
144; GCN-IR-NEXT:    s_mov_b32 s11, 0
145; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[16:17]
146; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[16:17], s[8:9], 63
147; GCN-IR-NEXT:    s_xor_b64 s[18:19], s[12:13], -1
148; GCN-IR-NEXT:    s_and_b64 s[16:17], s[18:19], s[16:17]
149; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
150; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_5
151; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
152; GCN-IR-NEXT:    s_add_u32 s12, s8, 1
153; GCN-IR-NEXT:    s_addc_u32 s13, s9, 0
154; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[16:17], s[12:13], 0
155; GCN-IR-NEXT:    s_sub_i32 s8, 63, s8
156; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[16:17]
157; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[2:3], s8
158; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_4
159; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
160; GCN-IR-NEXT:    s_lshr_b64 s[12:13], s[2:3], s12
161; GCN-IR-NEXT:    s_add_u32 s16, s4, -1
162; GCN-IR-NEXT:    s_addc_u32 s17, s5, -1
163; GCN-IR-NEXT:    s_not_b64 s[6:7], s[10:11]
164; GCN-IR-NEXT:    s_mov_b32 s15, s11
165; GCN-IR-NEXT:    s_add_u32 s10, s6, s14
166; GCN-IR-NEXT:    s_addc_u32 s11, s7, s11
167; GCN-IR-NEXT:    s_mov_b64 s[14:15], 0
168; GCN-IR-NEXT:    s_mov_b32 s7, 0
169; GCN-IR-NEXT:  .LBB0_3: ; %udiv-do-while
170; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
171; GCN-IR-NEXT:    s_lshl_b64 s[12:13], s[12:13], 1
172; GCN-IR-NEXT:    s_lshr_b32 s6, s9, 31
173; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
174; GCN-IR-NEXT:    s_or_b64 s[12:13], s[12:13], s[6:7]
175; GCN-IR-NEXT:    s_or_b64 s[8:9], s[14:15], s[8:9]
176; GCN-IR-NEXT:    s_sub_u32 s6, s16, s12
177; GCN-IR-NEXT:    s_subb_u32 s6, s17, s13
178; GCN-IR-NEXT:    s_ashr_i32 s14, s6, 31
179; GCN-IR-NEXT:    s_mov_b32 s15, s14
180; GCN-IR-NEXT:    s_and_b32 s6, s14, 1
181; GCN-IR-NEXT:    s_and_b64 s[14:15], s[14:15], s[4:5]
182; GCN-IR-NEXT:    s_sub_u32 s12, s12, s14
183; GCN-IR-NEXT:    s_subb_u32 s13, s13, s15
184; GCN-IR-NEXT:    s_add_u32 s10, s10, 1
185; GCN-IR-NEXT:    s_addc_u32 s11, s11, 0
186; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[18:19], s[10:11], 0
187; GCN-IR-NEXT:    s_mov_b64 s[14:15], s[6:7]
188; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[18:19]
189; GCN-IR-NEXT:    s_cbranch_vccz .LBB0_3
190; GCN-IR-NEXT:  .LBB0_4: ; %Flow6
191; GCN-IR-NEXT:    s_lshl_b64 s[8:9], s[8:9], 1
192; GCN-IR-NEXT:    s_or_b64 s[6:7], s[6:7], s[8:9]
193; GCN-IR-NEXT:    v_mov_b32_e32 v0, s6
194; GCN-IR-NEXT:    v_mov_b32_e32 v1, s7
195; GCN-IR-NEXT:    s_branch .LBB0_6
196; GCN-IR-NEXT:  .LBB0_5:
197; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
198; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[12:13]
199; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
200; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[12:13]
201; GCN-IR-NEXT:  .LBB0_6: ; %udiv-end
202; GCN-IR-NEXT:    v_mul_lo_u32 v1, s4, v1
203; GCN-IR-NEXT:    v_mul_hi_u32 v2, s4, v0
204; GCN-IR-NEXT:    v_mul_lo_u32 v3, s5, v0
205; GCN-IR-NEXT:    v_mul_lo_u32 v0, s4, v0
206; GCN-IR-NEXT:    s_mov_b32 s11, 0xf000
207; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
208; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
209; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
210; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
211; GCN-IR-NEXT:    s_mov_b32 s10, -1
212; GCN-IR-NEXT:    s_mov_b32 s8, s0
213; GCN-IR-NEXT:    s_mov_b32 s9, s1
214; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
215; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
216; GCN-IR-NEXT:    s_endpgm
217  %result = urem i64 %x, %y
218  store i64 %result, i64 addrspace(1)* %out
219  ret void
220}
221
222define i64 @v_test_urem_i64(i64 %x, i64 %y) {
223; GCN-LABEL: v_test_urem_i64:
224; GCN:       ; %bb.0:
225; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
226; GCN-NEXT:    v_cvt_f32_u32_e32 v4, v2
227; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v3
228; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v2
229; GCN-NEXT:    v_subb_u32_e32 v7, vcc, 0, v3, vcc
230; GCN-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
231; GCN-NEXT:    v_rcp_f32_e32 v4, v4
232; GCN-NEXT:    v_mov_b32_e32 v13, 0
233; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
234; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
235; GCN-NEXT:    v_trunc_f32_e32 v5, v5
236; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
237; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
238; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
239; GCN-NEXT:    v_mul_lo_u32 v8, v6, v5
240; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
241; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
242; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
243; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
244; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
245; GCN-NEXT:    v_mul_lo_u32 v10, v4, v8
246; GCN-NEXT:    v_mul_hi_u32 v11, v4, v9
247; GCN-NEXT:    v_mul_hi_u32 v12, v4, v8
248; GCN-NEXT:    v_mul_hi_u32 v14, v5, v8
249; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
250; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
251; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
252; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
253; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
254; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
255; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v9, vcc
256; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v13, vcc
257; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
258; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
259; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
260; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v9, vcc
261; GCN-NEXT:    v_mul_lo_u32 v8, v6, v5
262; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
263; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
264; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
265; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
266; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
267; GCN-NEXT:    v_mul_lo_u32 v10, v4, v7
268; GCN-NEXT:    v_mul_hi_u32 v11, v4, v6
269; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
270; GCN-NEXT:    v_mul_hi_u32 v9, v5, v6
271; GCN-NEXT:    v_mul_lo_u32 v6, v5, v6
272; GCN-NEXT:    v_mul_hi_u32 v8, v5, v7
273; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
274; GCN-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
275; GCN-NEXT:    v_mul_lo_u32 v7, v5, v7
276; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
277; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
278; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v8, v13, vcc
279; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
280; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
281; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
282; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
283; GCN-NEXT:    v_mul_lo_u32 v6, v0, v5
284; GCN-NEXT:    v_mul_hi_u32 v7, v0, v4
285; GCN-NEXT:    v_mul_hi_u32 v8, v0, v5
286; GCN-NEXT:    v_mul_hi_u32 v9, v1, v5
287; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
288; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
289; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
290; GCN-NEXT:    v_mul_lo_u32 v8, v1, v4
291; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
292; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
293; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v4, vcc
294; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v13, vcc
295; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
296; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
297; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
298; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
299; GCN-NEXT:    v_mul_lo_u32 v7, v3, v4
300; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
301; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
302; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
303; GCN-NEXT:    v_sub_i32_e32 v6, vcc, v1, v5
304; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
305; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v6, v3, vcc
306; GCN-NEXT:    v_sub_i32_e64 v6, s[4:5], v0, v2
307; GCN-NEXT:    v_subbrev_u32_e64 v7, s[6:7], 0, v4, s[4:5]
308; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v7, v3
309; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
310; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v2
311; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
312; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[6:7]
313; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v7, v3
314; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v3, s[4:5]
315; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
316; GCN-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[6:7]
317; GCN-NEXT:    v_sub_i32_e64 v9, s[4:5], v6, v2
318; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
319; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
320; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
321; GCN-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
322; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
323; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v8
324; GCN-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
325; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v9, s[4:5]
326; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
327; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v4, s[4:5]
328; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
329; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
330; GCN-NEXT:    s_setpc_b64 s[30:31]
331;
332; GCN-IR-LABEL: v_test_urem_i64:
333; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
334; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
335; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[2:3]
336; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
337; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v2
338; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
339; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
340; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v3
341; GCN-IR-NEXT:    v_min_u32_e32 v8, v4, v5
342; GCN-IR-NEXT:    v_ffbh_u32_e32 v4, v0
343; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, 32, v4
344; GCN-IR-NEXT:    v_ffbh_u32_e32 v5, v1
345; GCN-IR-NEXT:    v_min_u32_e32 v10, v4, v5
346; GCN-IR-NEXT:    v_sub_i32_e32 v5, vcc, v8, v10
347; GCN-IR-NEXT:    v_subb_u32_e64 v6, s[6:7], 0, 0, vcc
348; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[5:6]
349; GCN-IR-NEXT:    v_mov_b32_e32 v9, 0
350; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
351; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[5:6]
352; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
353; GCN-IR-NEXT:    v_mov_b32_e32 v11, v9
354; GCN-IR-NEXT:    v_cndmask_b32_e64 v7, v1, 0, s[4:5]
355; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v0, 0, s[4:5]
356; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
357; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
358; GCN-IR-NEXT:    s_cbranch_execz .LBB1_6
359; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
360; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, 1, v5
361; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, 0, v6, vcc
362; GCN-IR-NEXT:    v_sub_i32_e64 v4, s[4:5], 63, v5
363; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[12:13]
364; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[0:1], v4
365; GCN-IR-NEXT:    v_mov_b32_e32 v6, 0
366; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
367; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
368; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
369; GCN-IR-NEXT:    s_cbranch_execz .LBB1_5
370; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
371; GCN-IR-NEXT:    v_add_i32_e32 v14, vcc, -1, v2
372; GCN-IR-NEXT:    v_addc_u32_e32 v15, vcc, -1, v3, vcc
373; GCN-IR-NEXT:    v_not_b32_e32 v7, v8
374; GCN-IR-NEXT:    v_not_b32_e32 v6, v9
375; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, v7, v10
376; GCN-IR-NEXT:    v_lshr_b64 v[12:13], v[0:1], v12
377; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, v6, v11, vcc
378; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
379; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
380; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
381; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
382; GCN-IR-NEXT:  .LBB1_3: ; %udiv-do-while
383; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
384; GCN-IR-NEXT:    v_lshl_b64 v[12:13], v[12:13], 1
385; GCN-IR-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
386; GCN-IR-NEXT:    v_or_b32_e32 v12, v12, v6
387; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
388; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, v14, v12
389; GCN-IR-NEXT:    v_subb_u32_e32 v6, vcc, v15, v13, vcc
390; GCN-IR-NEXT:    v_or_b32_e32 v4, v10, v4
391; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v6
392; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v8
393; GCN-IR-NEXT:    v_or_b32_e32 v5, v11, v5
394; GCN-IR-NEXT:    v_and_b32_e32 v6, 1, v10
395; GCN-IR-NEXT:    v_and_b32_e32 v11, v10, v3
396; GCN-IR-NEXT:    v_and_b32_e32 v10, v10, v2
397; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
398; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[8:9]
399; GCN-IR-NEXT:    v_sub_i32_e64 v12, s[4:5], v12, v10
400; GCN-IR-NEXT:    v_subb_u32_e64 v13, s[4:5], v13, v11, s[4:5]
401; GCN-IR-NEXT:    v_mov_b32_e32 v11, v7
402; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
403; GCN-IR-NEXT:    v_mov_b32_e32 v10, v6
404; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
405; GCN-IR-NEXT:    s_cbranch_execnz .LBB1_3
406; GCN-IR-NEXT:  ; %bb.4: ; %Flow
407; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
408; GCN-IR-NEXT:  .LBB1_5: ; %Flow3
409; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
410; GCN-IR-NEXT:    v_lshl_b64 v[4:5], v[4:5], 1
411; GCN-IR-NEXT:    v_or_b32_e32 v7, v7, v5
412; GCN-IR-NEXT:    v_or_b32_e32 v4, v6, v4
413; GCN-IR-NEXT:  .LBB1_6: ; %Flow4
414; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
415; GCN-IR-NEXT:    v_mul_lo_u32 v5, v2, v7
416; GCN-IR-NEXT:    v_mul_hi_u32 v6, v2, v4
417; GCN-IR-NEXT:    v_mul_lo_u32 v3, v3, v4
418; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, v4
419; GCN-IR-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
420; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
421; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
422; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
423; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
424  %result = urem i64 %x, %y
425  ret i64 %result
426}
427
428define amdgpu_kernel void @s_test_urem31_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
429; GCN-LABEL: s_test_urem31_i64:
430; GCN:       ; %bb.0:
431; GCN-NEXT:    s_load_dword s4, s[0:1], 0xe
432; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
433; GCN-NEXT:    s_waitcnt lgkmcnt(0)
434; GCN-NEXT:    s_mov_b32 s2, -1
435; GCN-NEXT:    s_lshr_b32 s4, s4, 1
436; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
437; GCN-NEXT:    s_lshr_b32 s5, s3, 1
438; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s5
439; GCN-NEXT:    s_mov_b32 s3, 0xf000
440; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
441; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
442; GCN-NEXT:    v_trunc_f32_e32 v2, v2
443; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
444; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
445; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
446; GCN-NEXT:    v_mov_b32_e32 v1, 0
447; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
448; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
449; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
450; GCN-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
451; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
452; GCN-NEXT:    s_endpgm
453;
454; GCN-IR-LABEL: s_test_urem31_i64:
455; GCN-IR:       ; %bb.0:
456; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xe
457; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
458; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
459; GCN-IR-NEXT:    s_mov_b32 s2, -1
460; GCN-IR-NEXT:    s_lshr_b32 s4, s4, 1
461; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
462; GCN-IR-NEXT:    s_lshr_b32 s5, s3, 1
463; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s5
464; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
465; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
466; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
467; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
468; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
469; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
470; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
471; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
472; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
473; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
474; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
475; GCN-IR-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
476; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
477; GCN-IR-NEXT:    s_endpgm
478  %1 = lshr i64 %x, 33
479  %2 = lshr i64 %y, 33
480  %result = urem i64 %1, %2
481  store i64 %result, i64 addrspace(1)* %out
482  ret void
483}
484
485define amdgpu_kernel void @s_test_urem31_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
486; GCN-LABEL: s_test_urem31_v2i64:
487; GCN:       ; %bb.0:
488; GCN-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
489; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
490; GCN-NEXT:    v_mov_b32_e32 v1, 0
491; GCN-NEXT:    s_mov_b32 s3, 0xf000
492; GCN-NEXT:    s_mov_b32 s2, -1
493; GCN-NEXT:    s_waitcnt lgkmcnt(0)
494; GCN-NEXT:    s_lshr_b32 s4, s5, 1
495; GCN-NEXT:    s_lshr_b32 s5, s9, 1
496; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s5
497; GCN-NEXT:    v_cvt_f32_u32_e32 v2, s4
498; GCN-NEXT:    s_lshr_b32 s6, s11, 1
499; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s6
500; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v0
501; GCN-NEXT:    s_lshr_b32 s7, s7, 1
502; GCN-NEXT:    v_cvt_f32_u32_e32 v5, s7
503; GCN-NEXT:    v_rcp_iflag_f32_e32 v6, v3
504; GCN-NEXT:    v_mul_f32_e32 v4, v2, v4
505; GCN-NEXT:    v_trunc_f32_e32 v4, v4
506; GCN-NEXT:    v_cvt_u32_f32_e32 v7, v4
507; GCN-NEXT:    v_mad_f32 v2, -v4, v0, v2
508; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v0
509; GCN-NEXT:    v_mul_f32_e32 v2, v5, v6
510; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v7, vcc
511; GCN-NEXT:    v_mul_lo_u32 v0, v0, s5
512; GCN-NEXT:    v_trunc_f32_e32 v2, v2
513; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v2
514; GCN-NEXT:    v_mad_f32 v2, -v2, v3, v5
515; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
516; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
517; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v4, vcc
518; GCN-NEXT:    v_mul_lo_u32 v2, v2, s6
519; GCN-NEXT:    s_brev_b32 s4, -2
520; GCN-NEXT:    v_and_b32_e32 v0, s4, v0
521; GCN-NEXT:    v_mov_b32_e32 v3, v1
522; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s7, v2
523; GCN-NEXT:    v_and_b32_e32 v2, s4, v2
524; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
525; GCN-NEXT:    s_endpgm
526;
527; GCN-IR-LABEL: s_test_urem31_v2i64:
528; GCN-IR:       ; %bb.0:
529; GCN-IR-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
530; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
531; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
532; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
533; GCN-IR-NEXT:    s_mov_b32 s2, -1
534; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
535; GCN-IR-NEXT:    s_lshr_b32 s4, s5, 1
536; GCN-IR-NEXT:    s_lshr_b32 s5, s9, 1
537; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s5
538; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v2, s4
539; GCN-IR-NEXT:    s_lshr_b32 s6, s11, 1
540; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v3, s6
541; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v4, v0
542; GCN-IR-NEXT:    s_lshr_b32 s7, s7, 1
543; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v5, s7
544; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v6, v3
545; GCN-IR-NEXT:    v_mul_f32_e32 v4, v2, v4
546; GCN-IR-NEXT:    v_trunc_f32_e32 v4, v4
547; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v7, v4
548; GCN-IR-NEXT:    v_mad_f32 v2, -v4, v0, v2
549; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v0
550; GCN-IR-NEXT:    v_mul_f32_e32 v2, v5, v6
551; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v7, vcc
552; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s5
553; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
554; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v4, v2
555; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v3, v5
556; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
557; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
558; GCN-IR-NEXT:    v_addc_u32_e32 v2, vcc, 0, v4, vcc
559; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, s6
560; GCN-IR-NEXT:    s_brev_b32 s4, -2
561; GCN-IR-NEXT:    v_and_b32_e32 v0, s4, v0
562; GCN-IR-NEXT:    v_mov_b32_e32 v3, v1
563; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, s7, v2
564; GCN-IR-NEXT:    v_and_b32_e32 v2, s4, v2
565; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
566; GCN-IR-NEXT:    s_endpgm
567  %1 = lshr <2 x i64> %x, <i64 33, i64 33>
568  %2 = lshr <2 x i64> %y, <i64 33, i64 33>
569  %result = urem <2 x i64> %1, %2
570  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
571  ret void
572}
573
574define amdgpu_kernel void @s_test_urem24_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
575; GCN-LABEL: s_test_urem24_i64:
576; GCN:       ; %bb.0:
577; GCN-NEXT:    s_load_dword s4, s[0:1], 0xe
578; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
579; GCN-NEXT:    s_waitcnt lgkmcnt(0)
580; GCN-NEXT:    s_mov_b32 s2, -1
581; GCN-NEXT:    s_lshr_b32 s4, s4, 8
582; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
583; GCN-NEXT:    s_lshr_b32 s5, s3, 8
584; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s5
585; GCN-NEXT:    s_mov_b32 s3, 0xf000
586; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
587; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
588; GCN-NEXT:    v_trunc_f32_e32 v2, v2
589; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
590; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
591; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
592; GCN-NEXT:    v_mov_b32_e32 v1, 0
593; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
594; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
595; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
596; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
597; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
598; GCN-NEXT:    s_endpgm
599;
600; GCN-IR-LABEL: s_test_urem24_i64:
601; GCN-IR:       ; %bb.0:
602; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xe
603; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
604; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
605; GCN-IR-NEXT:    s_mov_b32 s2, -1
606; GCN-IR-NEXT:    s_lshr_b32 s4, s4, 8
607; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
608; GCN-IR-NEXT:    s_lshr_b32 s5, s3, 8
609; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s5
610; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
611; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
612; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
613; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
614; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
615; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
616; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
617; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
618; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
619; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
620; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s5, v0
621; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
622; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
623; GCN-IR-NEXT:    s_endpgm
624  %1 = lshr i64 %x, 40
625  %2 = lshr i64 %y, 40
626  %result = urem i64 %1, %2
627  store i64 %result, i64 addrspace(1)* %out
628  ret void
629}
630
631define amdgpu_kernel void @s_test_urem23_64_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
632; GCN-LABEL: s_test_urem23_64_v2i64:
633; GCN:       ; %bb.0:
634; GCN-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
635; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
636; GCN-NEXT:    v_mov_b32_e32 v1, 0
637; GCN-NEXT:    s_mov_b32 s3, 0xf000
638; GCN-NEXT:    s_mov_b32 s2, -1
639; GCN-NEXT:    s_waitcnt lgkmcnt(0)
640; GCN-NEXT:    s_lshr_b32 s4, s5, 1
641; GCN-NEXT:    s_lshr_b32 s5, s9, 1
642; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s5
643; GCN-NEXT:    v_cvt_f32_u32_e32 v2, s4
644; GCN-NEXT:    s_lshr_b32 s6, s11, 9
645; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s6
646; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v0
647; GCN-NEXT:    s_lshr_b32 s7, s7, 9
648; GCN-NEXT:    v_cvt_f32_u32_e32 v5, s7
649; GCN-NEXT:    v_rcp_iflag_f32_e32 v6, v3
650; GCN-NEXT:    v_mul_f32_e32 v4, v2, v4
651; GCN-NEXT:    v_trunc_f32_e32 v4, v4
652; GCN-NEXT:    v_cvt_u32_f32_e32 v7, v4
653; GCN-NEXT:    v_mad_f32 v2, -v4, v0, v2
654; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v0
655; GCN-NEXT:    v_mul_f32_e32 v2, v5, v6
656; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v7, vcc
657; GCN-NEXT:    v_mul_lo_u32 v0, v0, s5
658; GCN-NEXT:    v_trunc_f32_e32 v2, v2
659; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v2
660; GCN-NEXT:    v_mad_f32 v2, -v2, v3, v5
661; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
662; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
663; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v4, vcc
664; GCN-NEXT:    v_mul_lo_u32 v2, v2, s6
665; GCN-NEXT:    s_brev_b32 s4, -2
666; GCN-NEXT:    v_and_b32_e32 v0, s4, v0
667; GCN-NEXT:    v_mov_b32_e32 v3, v1
668; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s7, v2
669; GCN-NEXT:    v_and_b32_e32 v2, s4, v2
670; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
671; GCN-NEXT:    s_endpgm
672;
673; GCN-IR-LABEL: s_test_urem23_64_v2i64:
674; GCN-IR:       ; %bb.0:
675; GCN-IR-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
676; GCN-IR-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
677; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
678; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
679; GCN-IR-NEXT:    s_mov_b32 s2, -1
680; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
681; GCN-IR-NEXT:    s_lshr_b32 s4, s5, 1
682; GCN-IR-NEXT:    s_lshr_b32 s5, s9, 1
683; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s5
684; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v2, s4
685; GCN-IR-NEXT:    s_lshr_b32 s6, s11, 9
686; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v3, s6
687; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v4, v0
688; GCN-IR-NEXT:    s_lshr_b32 s7, s7, 9
689; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v5, s7
690; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v6, v3
691; GCN-IR-NEXT:    v_mul_f32_e32 v4, v2, v4
692; GCN-IR-NEXT:    v_trunc_f32_e32 v4, v4
693; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v7, v4
694; GCN-IR-NEXT:    v_mad_f32 v2, -v4, v0, v2
695; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v0
696; GCN-IR-NEXT:    v_mul_f32_e32 v2, v5, v6
697; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v7, vcc
698; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s5
699; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
700; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v4, v2
701; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v3, v5
702; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
703; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
704; GCN-IR-NEXT:    v_addc_u32_e32 v2, vcc, 0, v4, vcc
705; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, s6
706; GCN-IR-NEXT:    s_brev_b32 s4, -2
707; GCN-IR-NEXT:    v_and_b32_e32 v0, s4, v0
708; GCN-IR-NEXT:    v_mov_b32_e32 v3, v1
709; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, s7, v2
710; GCN-IR-NEXT:    v_and_b32_e32 v2, s4, v2
711; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
712; GCN-IR-NEXT:    s_endpgm
713  %1 = lshr <2 x i64> %x, <i64 33, i64 41>
714  %2 = lshr <2 x i64> %y, <i64 33, i64 41>
715  %result = urem <2 x i64> %1, %2
716  store <2 x i64> %result, <2 x i64> addrspace(1)* %out
717  ret void
718}
719
720define amdgpu_kernel void @s_test_urem_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
721; GCN-LABEL: s_test_urem_k_num_i64:
722; GCN:       ; %bb.0:
723; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
724; GCN-NEXT:    s_mov_b32 s11, 0xf000
725; GCN-NEXT:    s_mov_b32 s10, -1
726; GCN-NEXT:    s_waitcnt lgkmcnt(0)
727; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s6
728; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s7
729; GCN-NEXT:    s_sub_u32 s0, 0, s6
730; GCN-NEXT:    s_subb_u32 s1, 0, s7
731; GCN-NEXT:    s_mov_b32 s8, s4
732; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
733; GCN-NEXT:    v_rcp_f32_e32 v0, v0
734; GCN-NEXT:    v_mov_b32_e32 v1, 0
735; GCN-NEXT:    s_mov_b32 s9, s5
736; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
737; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
738; GCN-NEXT:    v_trunc_f32_e32 v2, v2
739; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
740; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
741; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
742; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
743; GCN-NEXT:    v_mul_hi_u32 v4, s0, v0
744; GCN-NEXT:    v_mul_lo_u32 v6, s1, v0
745; GCN-NEXT:    v_mul_lo_u32 v5, s0, v0
746; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
747; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
748; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
749; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
750; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
751; GCN-NEXT:    v_mul_hi_u32 v7, v2, v5
752; GCN-NEXT:    v_mul_lo_u32 v5, v2, v5
753; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
754; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
755; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v8, vcc
756; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
757; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
758; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v7, vcc
759; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
760; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
761; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
762; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
763; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc
764; GCN-NEXT:    v_mul_lo_u32 v3, s0, v2
765; GCN-NEXT:    v_mul_hi_u32 v4, s0, v0
766; GCN-NEXT:    v_mul_lo_u32 v5, s1, v0
767; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
768; GCN-NEXT:    v_mul_lo_u32 v4, s0, v0
769; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
770; GCN-NEXT:    v_mul_lo_u32 v7, v0, v3
771; GCN-NEXT:    v_mul_hi_u32 v8, v0, v4
772; GCN-NEXT:    v_mul_hi_u32 v9, v0, v3
773; GCN-NEXT:    v_mul_hi_u32 v6, v2, v4
774; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
775; GCN-NEXT:    v_mul_hi_u32 v5, v2, v3
776; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
777; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v9, vcc
778; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
779; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
780; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v6, vcc
781; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v5, v1, vcc
782; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
783; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
784; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
785; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
786; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
787; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
788; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
789; GCN-NEXT:    v_mov_b32_e32 v3, s7
790; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
791; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v1, vcc
792; GCN-NEXT:    v_mul_lo_u32 v1, s7, v0
793; GCN-NEXT:    v_mul_hi_u32 v2, s6, v0
794; GCN-NEXT:    v_mul_lo_u32 v0, s6, v0
795; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
796; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
797; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
798; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
799; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s6, v0
800; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
801; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s7, v5
802; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
803; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s6, v4
804; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
805; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
806; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s7, v5
807; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s6, v4
808; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
809; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
810; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
811; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
812; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
813; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
814; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
815; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
816; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
817; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s7, v1
818; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
819; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
820; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
821; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
822; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
823; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
824; GCN-NEXT:    s_endpgm
825;
826; GCN-IR-LABEL: s_test_urem_k_num_i64:
827; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
828; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
829; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
830; GCN-IR-NEXT:    s_flbit_i32_b32 s4, s2
831; GCN-IR-NEXT:    s_flbit_i32_b32 s5, s3
832; GCN-IR-NEXT:    s_add_i32 s4, s4, 32
833; GCN-IR-NEXT:    s_min_u32 s8, s4, s5
834; GCN-IR-NEXT:    s_add_u32 s6, s8, 0xffffffc5
835; GCN-IR-NEXT:    s_addc_u32 s7, 0, -1
836; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
837; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[6:7], 63
838; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0
839; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
840; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[6:7], 63
841; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
842; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
843; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
844; GCN-IR-NEXT:    s_cbranch_vccz .LBB6_5
845; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
846; GCN-IR-NEXT:    s_add_u32 s10, s6, 1
847; GCN-IR-NEXT:    s_addc_u32 s11, s7, 0
848; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[10:11], 0
849; GCN-IR-NEXT:    s_sub_i32 s6, 63, s6
850; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[12:13]
851; GCN-IR-NEXT:    s_lshl_b64 s[6:7], 24, s6
852; GCN-IR-NEXT:    s_cbranch_vccz .LBB6_4
853; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
854; GCN-IR-NEXT:    s_lshr_b64 s[10:11], 24, s10
855; GCN-IR-NEXT:    s_add_u32 s14, s2, -1
856; GCN-IR-NEXT:    s_addc_u32 s15, s3, -1
857; GCN-IR-NEXT:    s_sub_u32 s8, 58, s8
858; GCN-IR-NEXT:    s_subb_u32 s9, 0, 0
859; GCN-IR-NEXT:    s_mov_b64 s[12:13], 0
860; GCN-IR-NEXT:    s_mov_b32 s5, 0
861; GCN-IR-NEXT:  .LBB6_3: ; %udiv-do-while
862; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
863; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
864; GCN-IR-NEXT:    s_lshr_b32 s4, s7, 31
865; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[6:7], 1
866; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[4:5]
867; GCN-IR-NEXT:    s_or_b64 s[6:7], s[12:13], s[6:7]
868; GCN-IR-NEXT:    s_sub_u32 s4, s14, s10
869; GCN-IR-NEXT:    s_subb_u32 s4, s15, s11
870; GCN-IR-NEXT:    s_ashr_i32 s12, s4, 31
871; GCN-IR-NEXT:    s_mov_b32 s13, s12
872; GCN-IR-NEXT:    s_and_b32 s4, s12, 1
873; GCN-IR-NEXT:    s_and_b64 s[12:13], s[12:13], s[2:3]
874; GCN-IR-NEXT:    s_sub_u32 s10, s10, s12
875; GCN-IR-NEXT:    s_subb_u32 s11, s11, s13
876; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
877; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
878; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[16:17], s[8:9], 0
879; GCN-IR-NEXT:    s_mov_b64 s[12:13], s[4:5]
880; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[16:17]
881; GCN-IR-NEXT:    s_cbranch_vccz .LBB6_3
882; GCN-IR-NEXT:  .LBB6_4: ; %Flow5
883; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[6:7], 1
884; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], s[6:7]
885; GCN-IR-NEXT:    v_mov_b32_e32 v0, s4
886; GCN-IR-NEXT:    v_mov_b32_e32 v1, s5
887; GCN-IR-NEXT:    s_branch .LBB6_6
888; GCN-IR-NEXT:  .LBB6_5:
889; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
890; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, 24, 0, s[10:11]
891; GCN-IR-NEXT:  .LBB6_6: ; %udiv-end
892; GCN-IR-NEXT:    v_mul_lo_u32 v1, s2, v1
893; GCN-IR-NEXT:    v_mul_hi_u32 v2, s2, v0
894; GCN-IR-NEXT:    v_mul_lo_u32 v3, s3, v0
895; GCN-IR-NEXT:    v_mul_lo_u32 v0, s2, v0
896; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
897; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
898; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
899; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
900; GCN-IR-NEXT:    s_mov_b32 s6, -1
901; GCN-IR-NEXT:    s_mov_b32 s4, s0
902; GCN-IR-NEXT:    s_mov_b32 s5, s1
903; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
904; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
905; GCN-IR-NEXT:    s_endpgm
906  %result = urem i64 24, %x
907  store i64 %result, i64 addrspace(1)* %out
908  ret void
909}
910
911define amdgpu_kernel void @s_test_urem_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
912; GCN-LABEL: s_test_urem_k_den_i64:
913; GCN:       ; %bb.0:
914; GCN-NEXT:    v_mov_b32_e32 v0, 0x4f800000
915; GCN-NEXT:    v_madak_f32 v0, 0, v0, 0x41c00000
916; GCN-NEXT:    v_rcp_f32_e32 v0, v0
917; GCN-NEXT:    s_movk_i32 s4, 0xffe8
918; GCN-NEXT:    v_mov_b32_e32 v2, 0
919; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
920; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
921; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
922; GCN-NEXT:    v_trunc_f32_e32 v1, v1
923; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
924; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
925; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
926; GCN-NEXT:    s_waitcnt lgkmcnt(0)
927; GCN-NEXT:    s_mov_b32 s5, s1
928; GCN-NEXT:    s_mov_b32 s7, 0xf000
929; GCN-NEXT:    v_mul_hi_u32 v3, v0, s4
930; GCN-NEXT:    v_mul_lo_u32 v5, v1, s4
931; GCN-NEXT:    v_mul_lo_u32 v4, v0, s4
932; GCN-NEXT:    s_mov_b32 s6, -1
933; GCN-NEXT:    v_subrev_i32_e32 v3, vcc, v0, v3
934; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
935; GCN-NEXT:    v_mul_hi_u32 v6, v0, v4
936; GCN-NEXT:    v_mul_lo_u32 v5, v0, v3
937; GCN-NEXT:    v_mul_hi_u32 v7, v0, v3
938; GCN-NEXT:    v_mul_hi_u32 v8, v1, v3
939; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
940; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
941; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
942; GCN-NEXT:    v_mul_lo_u32 v7, v1, v4
943; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
944; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
945; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v4, vcc
946; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v2, vcc
947; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
948; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
949; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
950; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc
951; GCN-NEXT:    v_mul_hi_u32 v3, v0, s4
952; GCN-NEXT:    v_mul_lo_u32 v4, v1, s4
953; GCN-NEXT:    v_mul_lo_u32 v5, v0, s4
954; GCN-NEXT:    s_mov_b32 s4, s0
955; GCN-NEXT:    v_subrev_i32_e32 v3, vcc, v0, v3
956; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
957; GCN-NEXT:    v_mul_lo_u32 v4, v0, v3
958; GCN-NEXT:    v_mul_hi_u32 v6, v0, v5
959; GCN-NEXT:    v_mul_hi_u32 v7, v0, v3
960; GCN-NEXT:    v_mul_hi_u32 v8, v1, v3
961; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
962; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
963; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v7, vcc
964; GCN-NEXT:    v_mul_lo_u32 v7, v1, v5
965; GCN-NEXT:    v_mul_hi_u32 v5, v1, v5
966; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
967; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
968; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v2, vcc
969; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
970; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
971; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
972; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc
973; GCN-NEXT:    v_mul_lo_u32 v3, s2, v1
974; GCN-NEXT:    v_mul_hi_u32 v4, s2, v0
975; GCN-NEXT:    v_mul_hi_u32 v5, s2, v1
976; GCN-NEXT:    v_mul_hi_u32 v6, s3, v1
977; GCN-NEXT:    v_mul_lo_u32 v1, s3, v1
978; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
979; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v5, vcc
980; GCN-NEXT:    v_mul_lo_u32 v5, s3, v0
981; GCN-NEXT:    v_mul_hi_u32 v0, s3, v0
982; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
983; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
984; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v6, v2, vcc
985; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
986; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
987; GCN-NEXT:    v_mul_lo_u32 v1, v1, 24
988; GCN-NEXT:    v_mul_hi_u32 v2, v0, 24
989; GCN-NEXT:    v_mul_lo_u32 v0, v0, 24
990; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
991; GCN-NEXT:    v_mov_b32_e32 v2, s3
992; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
993; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
994; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v0
995; GCN-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v1, vcc
996; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v2
997; GCN-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v3, vcc
998; GCN-NEXT:    v_cmp_lt_u32_e32 vcc, 23, v2
999; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
1000; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
1001; GCN-NEXT:    v_cndmask_b32_e32 v6, -1, v6, vcc
1002; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
1003; GCN-NEXT:    v_cmp_lt_u32_e64 s[0:1], 23, v0
1004; GCN-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
1005; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
1006; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v1
1007; GCN-NEXT:    v_cndmask_b32_e64 v5, -1, v5, s[0:1]
1008; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v5
1009; GCN-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
1010; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
1011; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
1012; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1013; GCN-NEXT:    s_endpgm
1014;
1015; GCN-IR-LABEL: s_test_urem_k_den_i64:
1016; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1017; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1018; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1019; GCN-IR-NEXT:    s_flbit_i32_b32 s4, s2
1020; GCN-IR-NEXT:    s_flbit_i32_b32 s5, s3
1021; GCN-IR-NEXT:    s_add_i32 s4, s4, 32
1022; GCN-IR-NEXT:    s_min_u32 s8, s4, s5
1023; GCN-IR-NEXT:    s_sub_u32 s6, 59, s8
1024; GCN-IR-NEXT:    s_subb_u32 s7, 0, 0
1025; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
1026; GCN-IR-NEXT:    v_cmp_gt_u64_e64 s[12:13], s[6:7], 63
1027; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0
1028; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[12:13]
1029; GCN-IR-NEXT:    v_cmp_ne_u64_e64 s[12:13], s[6:7], 63
1030; GCN-IR-NEXT:    s_xor_b64 s[14:15], s[10:11], -1
1031; GCN-IR-NEXT:    s_and_b64 s[12:13], s[14:15], s[12:13]
1032; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[12:13]
1033; GCN-IR-NEXT:    s_cbranch_vccz .LBB7_5
1034; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1035; GCN-IR-NEXT:    s_add_u32 s10, s6, 1
1036; GCN-IR-NEXT:    s_addc_u32 s11, s7, 0
1037; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[12:13], s[10:11], 0
1038; GCN-IR-NEXT:    s_sub_i32 s6, 63, s6
1039; GCN-IR-NEXT:    s_andn2_b64 vcc, exec, s[12:13]
1040; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[2:3], s6
1041; GCN-IR-NEXT:    s_cbranch_vccz .LBB7_4
1042; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1043; GCN-IR-NEXT:    s_lshr_b64 s[10:11], s[2:3], s10
1044; GCN-IR-NEXT:    s_add_u32 s8, s8, 0xffffffc4
1045; GCN-IR-NEXT:    s_addc_u32 s9, 0, -1
1046; GCN-IR-NEXT:    s_mov_b64 s[12:13], 0
1047; GCN-IR-NEXT:    s_mov_b32 s5, 0
1048; GCN-IR-NEXT:  .LBB7_3: ; %udiv-do-while
1049; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1050; GCN-IR-NEXT:    s_lshl_b64 s[10:11], s[10:11], 1
1051; GCN-IR-NEXT:    s_lshr_b32 s4, s7, 31
1052; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[6:7], 1
1053; GCN-IR-NEXT:    s_or_b64 s[10:11], s[10:11], s[4:5]
1054; GCN-IR-NEXT:    s_or_b64 s[6:7], s[12:13], s[6:7]
1055; GCN-IR-NEXT:    s_sub_u32 s4, 23, s10
1056; GCN-IR-NEXT:    s_subb_u32 s4, 0, s11
1057; GCN-IR-NEXT:    s_ashr_i32 s12, s4, 31
1058; GCN-IR-NEXT:    s_and_b32 s4, s12, 1
1059; GCN-IR-NEXT:    s_and_b32 s12, s12, 24
1060; GCN-IR-NEXT:    s_sub_u32 s10, s10, s12
1061; GCN-IR-NEXT:    s_subb_u32 s11, s11, 0
1062; GCN-IR-NEXT:    s_add_u32 s8, s8, 1
1063; GCN-IR-NEXT:    s_addc_u32 s9, s9, 0
1064; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[14:15], s[8:9], 0
1065; GCN-IR-NEXT:    s_mov_b64 s[12:13], s[4:5]
1066; GCN-IR-NEXT:    s_and_b64 vcc, exec, s[14:15]
1067; GCN-IR-NEXT:    s_cbranch_vccz .LBB7_3
1068; GCN-IR-NEXT:  .LBB7_4: ; %Flow5
1069; GCN-IR-NEXT:    s_lshl_b64 s[6:7], s[6:7], 1
1070; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], s[6:7]
1071; GCN-IR-NEXT:    v_mov_b32_e32 v0, s4
1072; GCN-IR-NEXT:    v_mov_b32_e32 v1, s5
1073; GCN-IR-NEXT:    s_branch .LBB7_6
1074; GCN-IR-NEXT:  .LBB7_5:
1075; GCN-IR-NEXT:    v_mov_b32_e32 v0, s3
1076; GCN-IR-NEXT:    v_cndmask_b32_e64 v1, v0, 0, s[10:11]
1077; GCN-IR-NEXT:    v_mov_b32_e32 v0, s2
1078; GCN-IR-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s[10:11]
1079; GCN-IR-NEXT:  .LBB7_6: ; %udiv-end
1080; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, 24
1081; GCN-IR-NEXT:    v_mul_hi_u32 v2, v0, 24
1082; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, 24
1083; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1084; GCN-IR-NEXT:    s_mov_b32 s6, -1
1085; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1086; GCN-IR-NEXT:    v_mov_b32_e32 v2, s3
1087; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1088; GCN-IR-NEXT:    s_mov_b32 s4, s0
1089; GCN-IR-NEXT:    s_mov_b32 s5, s1
1090; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
1091; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1092; GCN-IR-NEXT:    s_endpgm
1093  %result = urem i64 %x, 24
1094  store i64 %result, i64 addrspace(1)* %out
1095  ret void
1096}
1097
1098; FIXME: Constant bus violation
1099; define i64 @v_test_urem_k_num_i64(i64 %x) {
1100;   %result = urem i64 24, %x
1101;   ret i64 %result
1102; }
1103
1104define i64 @v_test_urem_pow2_k_num_i64(i64 %x) {
1105; GCN-LABEL: v_test_urem_pow2_k_num_i64:
1106; GCN:       ; %bb.0:
1107; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1108; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
1109; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
1110; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
1111; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
1112; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
1113; GCN-NEXT:    v_rcp_f32_e32 v2, v2
1114; GCN-NEXT:    v_mov_b32_e32 v11, 0
1115; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
1116; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
1117; GCN-NEXT:    v_trunc_f32_e32 v3, v3
1118; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
1119; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
1120; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
1121; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1122; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1123; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
1124; GCN-NEXT:    v_mul_lo_u32 v9, v4, v2
1125; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1126; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
1127; GCN-NEXT:    v_mul_lo_u32 v7, v2, v6
1128; GCN-NEXT:    v_mul_hi_u32 v8, v2, v9
1129; GCN-NEXT:    v_mul_hi_u32 v10, v2, v6
1130; GCN-NEXT:    v_mul_hi_u32 v12, v3, v6
1131; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
1132; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
1133; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v10, vcc
1134; GCN-NEXT:    v_mul_lo_u32 v10, v3, v9
1135; GCN-NEXT:    v_mul_hi_u32 v9, v3, v9
1136; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
1137; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v9, vcc
1138; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v11, vcc
1139; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1140; GCN-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
1141; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
1142; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v7, vcc
1143; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
1144; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
1145; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
1146; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
1147; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
1148; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
1149; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
1150; GCN-NEXT:    v_mul_hi_u32 v9, v2, v4
1151; GCN-NEXT:    v_mul_hi_u32 v10, v2, v5
1152; GCN-NEXT:    v_mul_hi_u32 v7, v3, v4
1153; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
1154; GCN-NEXT:    v_mul_hi_u32 v6, v3, v5
1155; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
1156; GCN-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
1157; GCN-NEXT:    v_mul_lo_u32 v5, v3, v5
1158; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
1159; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
1160; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v6, v11, vcc
1161; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
1162; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
1163; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
1164; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v3, v5, vcc
1165; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
1166; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
1167; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
1168; GCN-NEXT:    v_mul_lo_u32 v2, v0, v2
1169; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
1170; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
1171; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0x8000, v2
1172; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1173; GCN-NEXT:    v_sub_i32_e64 v5, s[4:5], v2, v0
1174; GCN-NEXT:    v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1175; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v6, v1
1176; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1177; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v5, v0
1178; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1179; GCN-NEXT:    v_cmp_eq_u32_e64 s[6:7], v6, v1
1180; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1181; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1182; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v5, v0
1183; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
1184; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1185; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
1186; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
1187; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
1188; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v0
1189; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
1190; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
1191; GCN-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
1192; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1193; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
1194; GCN-NEXT:    v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1195; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
1196; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
1197; GCN-NEXT:    s_setpc_b64 s[30:31]
1198;
1199; GCN-IR-LABEL: v_test_urem_pow2_k_num_i64:
1200; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1201; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1202; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1203; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2
1204; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1205; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1206; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 0xffffffd0, v6
1207; GCN-IR-NEXT:    v_addc_u32_e64 v3, s[6:7], 0, -1, vcc
1208; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1209; GCN-IR-NEXT:    v_cmp_lt_u64_e32 vcc, 63, v[2:3]
1210; GCN-IR-NEXT:    s_mov_b64 s[8:9], 0x8000
1211; GCN-IR-NEXT:    v_mov_b32_e32 v4, s8
1212; GCN-IR-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
1213; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[2:3]
1214; GCN-IR-NEXT:    v_mov_b32_e32 v7, 0
1215; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v4, 0, s[4:5]
1216; GCN-IR-NEXT:    s_xor_b64 s[4:5], s[4:5], -1
1217; GCN-IR-NEXT:    v_mov_b32_e32 v5, v7
1218; GCN-IR-NEXT:    s_and_b64 s[4:5], s[4:5], vcc
1219; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1220; GCN-IR-NEXT:    s_cbranch_execz .LBB8_6
1221; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1222; GCN-IR-NEXT:    v_add_i32_e32 v8, vcc, 1, v2
1223; GCN-IR-NEXT:    v_addc_u32_e32 v9, vcc, 0, v3, vcc
1224; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v2
1225; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[8:9]
1226; GCN-IR-NEXT:    v_lshl_b64 v[2:3], s[8:9], v2
1227; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1228; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1229; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1230; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1231; GCN-IR-NEXT:    s_cbranch_execz .LBB8_5
1232; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1233; GCN-IR-NEXT:    v_add_i32_e32 v12, vcc, -1, v0
1234; GCN-IR-NEXT:    s_mov_b64 s[4:5], 0x8000
1235; GCN-IR-NEXT:    v_addc_u32_e32 v13, vcc, -1, v1, vcc
1236; GCN-IR-NEXT:    v_lshr_b64 v[8:9], s[4:5], v8
1237; GCN-IR-NEXT:    v_sub_i32_e32 v6, vcc, 47, v6
1238; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1239; GCN-IR-NEXT:    v_subb_u32_e32 v7, vcc, 0, v7, vcc
1240; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1241; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1242; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1243; GCN-IR-NEXT:  .LBB8_3: ; %udiv-do-while
1244; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1245; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1246; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1247; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1248; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1249; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, v12, v8
1250; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, v13, v9, vcc
1251; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1252; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1253; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 1, v6
1254; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1255; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1256; GCN-IR-NEXT:    v_and_b32_e32 v11, v10, v1
1257; GCN-IR-NEXT:    v_and_b32_e32 v10, v10, v0
1258; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
1259; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[6:7]
1260; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v10
1261; GCN-IR-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v11, s[4:5]
1262; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1263; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1264; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1265; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1266; GCN-IR-NEXT:    s_cbranch_execnz .LBB8_3
1267; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1268; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1269; GCN-IR-NEXT:  .LBB8_5: ; %Flow3
1270; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1271; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1272; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1273; GCN-IR-NEXT:    v_or_b32_e32 v4, v4, v2
1274; GCN-IR-NEXT:  .LBB8_6: ; %Flow4
1275; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1276; GCN-IR-NEXT:    v_mul_lo_u32 v2, v0, v5
1277; GCN-IR-NEXT:    v_mul_hi_u32 v3, v0, v4
1278; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v4
1279; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v4
1280; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
1281; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
1282; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1283; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
1284; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1285  %result = urem i64 32768, %x
1286  ret i64 %result
1287}
1288
1289define i64 @v_test_urem_pow2_k_den_i64(i64 %x) {
1290; GCN-LABEL: v_test_urem_pow2_k_den_i64:
1291; GCN:       ; %bb.0:
1292; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1293; GCN-NEXT:    v_and_b32_e32 v0, 0x7fff, v0
1294; GCN-NEXT:    v_mov_b32_e32 v1, 0
1295; GCN-NEXT:    s_setpc_b64 s[30:31]
1296;
1297; GCN-IR-LABEL: v_test_urem_pow2_k_den_i64:
1298; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
1299; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1300; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
1301; GCN-IR-NEXT:    v_add_i32_e64 v2, s[4:5], 32, v2
1302; GCN-IR-NEXT:    v_ffbh_u32_e32 v3, v1
1303; GCN-IR-NEXT:    v_min_u32_e32 v6, v2, v3
1304; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 48, v6
1305; GCN-IR-NEXT:    v_subb_u32_e64 v3, s[4:5], 0, 0, s[4:5]
1306; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1307; GCN-IR-NEXT:    v_cmp_lt_u64_e64 s[4:5], 63, v[2:3]
1308; GCN-IR-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
1309; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 63, v[2:3]
1310; GCN-IR-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
1311; GCN-IR-NEXT:    v_cndmask_b32_e64 v5, v1, 0, s[4:5]
1312; GCN-IR-NEXT:    v_cndmask_b32_e64 v4, v0, 0, s[4:5]
1313; GCN-IR-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
1314; GCN-IR-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
1315; GCN-IR-NEXT:    s_cbranch_execz .LBB9_6
1316; GCN-IR-NEXT:  ; %bb.1: ; %udiv-bb1
1317; GCN-IR-NEXT:    v_add_i32_e32 v7, vcc, 1, v2
1318; GCN-IR-NEXT:    v_addc_u32_e32 v8, vcc, 0, v3, vcc
1319; GCN-IR-NEXT:    v_sub_i32_e64 v2, s[4:5], 63, v2
1320; GCN-IR-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[7:8]
1321; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[0:1], v2
1322; GCN-IR-NEXT:    v_mov_b32_e32 v4, 0
1323; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1324; GCN-IR-NEXT:    s_and_saveexec_b64 s[4:5], vcc
1325; GCN-IR-NEXT:    s_xor_b64 s[8:9], exec, s[4:5]
1326; GCN-IR-NEXT:    s_cbranch_execz .LBB9_5
1327; GCN-IR-NEXT:  ; %bb.2: ; %udiv-preheader
1328; GCN-IR-NEXT:    v_lshr_b64 v[8:9], v[0:1], v7
1329; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 0xffffffcf, v6
1330; GCN-IR-NEXT:    v_mov_b32_e32 v10, 0
1331; GCN-IR-NEXT:    v_addc_u32_e64 v7, s[4:5], 0, -1, vcc
1332; GCN-IR-NEXT:    s_mov_b64 s[10:11], 0
1333; GCN-IR-NEXT:    v_mov_b32_e32 v11, 0
1334; GCN-IR-NEXT:    v_mov_b32_e32 v5, 0
1335; GCN-IR-NEXT:    s_movk_i32 s12, 0x7fff
1336; GCN-IR-NEXT:  .LBB9_3: ; %udiv-do-while
1337; GCN-IR-NEXT:    ; =>This Inner Loop Header: Depth=1
1338; GCN-IR-NEXT:    v_lshl_b64 v[8:9], v[8:9], 1
1339; GCN-IR-NEXT:    v_lshrrev_b32_e32 v4, 31, v3
1340; GCN-IR-NEXT:    v_or_b32_e32 v8, v8, v4
1341; GCN-IR-NEXT:    v_sub_i32_e32 v4, vcc, s12, v8
1342; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1343; GCN-IR-NEXT:    v_subb_u32_e32 v4, vcc, 0, v9, vcc
1344; GCN-IR-NEXT:    v_add_i32_e32 v6, vcc, 1, v6
1345; GCN-IR-NEXT:    v_or_b32_e32 v2, v10, v2
1346; GCN-IR-NEXT:    v_ashrrev_i32_e32 v10, 31, v4
1347; GCN-IR-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
1348; GCN-IR-NEXT:    v_and_b32_e32 v4, 1, v10
1349; GCN-IR-NEXT:    v_and_b32_e32 v10, 0x8000, v10
1350; GCN-IR-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[6:7]
1351; GCN-IR-NEXT:    v_or_b32_e32 v3, v11, v3
1352; GCN-IR-NEXT:    v_sub_i32_e64 v8, s[4:5], v8, v10
1353; GCN-IR-NEXT:    v_mov_b32_e32 v11, v5
1354; GCN-IR-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5]
1355; GCN-IR-NEXT:    s_or_b64 s[10:11], vcc, s[10:11]
1356; GCN-IR-NEXT:    v_mov_b32_e32 v10, v4
1357; GCN-IR-NEXT:    s_andn2_b64 exec, exec, s[10:11]
1358; GCN-IR-NEXT:    s_cbranch_execnz .LBB9_3
1359; GCN-IR-NEXT:  ; %bb.4: ; %Flow
1360; GCN-IR-NEXT:    s_or_b64 exec, exec, s[10:11]
1361; GCN-IR-NEXT:  .LBB9_5: ; %Flow3
1362; GCN-IR-NEXT:    s_or_b64 exec, exec, s[8:9]
1363; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[2:3], 1
1364; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
1365; GCN-IR-NEXT:    v_or_b32_e32 v4, v4, v2
1366; GCN-IR-NEXT:  .LBB9_6: ; %Flow4
1367; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
1368; GCN-IR-NEXT:    v_lshl_b64 v[2:3], v[4:5], 15
1369; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
1370; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
1371; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1372  %result = urem i64 %x, 32768
1373  ret i64 %result
1374}
1375
1376define amdgpu_kernel void @s_test_urem24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
1377; GCN-LABEL: s_test_urem24_k_num_i64:
1378; GCN:       ; %bb.0:
1379; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1380; GCN-NEXT:    s_mov_b32 s5, 0x41c00000
1381; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1382; GCN-NEXT:    s_mov_b32 s2, -1
1383; GCN-NEXT:    s_lshr_b32 s4, s3, 8
1384; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
1385; GCN-NEXT:    s_mov_b32 s3, 0xf000
1386; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1387; GCN-NEXT:    v_mul_f32_e32 v1, s5, v1
1388; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1389; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1390; GCN-NEXT:    v_mad_f32 v1, -v1, v0, s5
1391; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1392; GCN-NEXT:    v_mov_b32_e32 v1, 0
1393; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1394; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
1395; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1396; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1397; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1398; GCN-NEXT:    s_endpgm
1399;
1400; GCN-IR-LABEL: s_test_urem24_k_num_i64:
1401; GCN-IR:       ; %bb.0:
1402; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1403; GCN-IR-NEXT:    s_mov_b32 s5, 0x41c00000
1404; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1405; GCN-IR-NEXT:    s_mov_b32 s2, -1
1406; GCN-IR-NEXT:    s_lshr_b32 s4, s3, 8
1407; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
1408; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
1409; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
1410; GCN-IR-NEXT:    v_mul_f32_e32 v1, s5, v1
1411; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1412; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1413; GCN-IR-NEXT:    v_mad_f32 v1, -v1, v0, s5
1414; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
1415; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1416; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1417; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
1418; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1419; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1420; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1421; GCN-IR-NEXT:    s_endpgm
1422  %x.shr = lshr i64 %x, 40
1423  %result = urem i64 24, %x.shr
1424  store i64 %result, i64 addrspace(1)* %out
1425  ret void
1426}
1427
1428define amdgpu_kernel void @s_test_urem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
1429; GCN-LABEL: s_test_urem24_k_den_i64:
1430; GCN:       ; %bb.0:
1431; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1432; GCN-NEXT:    s_mov_b32 s4, 0x46b6fe00
1433; GCN-NEXT:    s_mov_b32 s7, 0xf000
1434; GCN-NEXT:    s_mov_b32 s6, -1
1435; GCN-NEXT:    s_waitcnt lgkmcnt(0)
1436; GCN-NEXT:    s_lshr_b32 s2, s3, 8
1437; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
1438; GCN-NEXT:    s_movk_i32 s3, 0x5b7f
1439; GCN-NEXT:    s_mov_b32 s5, s1
1440; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1441; GCN-NEXT:    v_trunc_f32_e32 v1, v1
1442; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
1443; GCN-NEXT:    v_mad_f32 v0, -v1, s4, v0
1444; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
1445; GCN-NEXT:    s_mov_b32 s4, s0
1446; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1447; GCN-NEXT:    v_mul_lo_u32 v0, v0, s3
1448; GCN-NEXT:    v_mov_b32_e32 v1, 0
1449; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1450; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1451; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1452; GCN-NEXT:    s_endpgm
1453;
1454; GCN-IR-LABEL: s_test_urem24_k_den_i64:
1455; GCN-IR:       ; %bb.0:
1456; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
1457; GCN-IR-NEXT:    s_mov_b32 s4, 0x46b6fe00
1458; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
1459; GCN-IR-NEXT:    s_mov_b32 s6, -1
1460; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
1461; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 8
1462; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
1463; GCN-IR-NEXT:    s_movk_i32 s3, 0x5b7f
1464; GCN-IR-NEXT:    s_mov_b32 s5, s1
1465; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
1466; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
1467; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
1468; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s4, v0
1469; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
1470; GCN-IR-NEXT:    s_mov_b32 s4, s0
1471; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
1472; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s3
1473; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1474; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
1475; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1476; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1477; GCN-IR-NEXT:    s_endpgm
1478  %x.shr = lshr i64 %x, 40
1479  %result = urem i64 %x.shr, 23423
1480  store i64 %result, i64 addrspace(1)* %out
1481  ret void
1482}
1483
1484define i64 @v_test_urem24_k_num_i64(i64 %x) {
1485; GCN-LABEL: v_test_urem24_k_num_i64:
1486; GCN:       ; %bb.0:
1487; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1488; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1489; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v0
1490; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
1491; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1492; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
1493; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1494; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
1495; GCN-NEXT:    v_mad_f32 v2, -v2, v1, s4
1496; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1497; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1498; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
1499; GCN-NEXT:    v_mov_b32_e32 v1, 0
1500; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1501; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1502; GCN-NEXT:    s_setpc_b64 s[30:31]
1503;
1504; GCN-IR-LABEL: v_test_urem24_k_num_i64:
1505; GCN-IR:       ; %bb.0:
1506; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1507; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1508; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, v0
1509; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
1510; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1511; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
1512; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1513; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
1514; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v1, s4
1515; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1516; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1517; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
1518; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1519; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
1520; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1521; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1522  %x.shr = lshr i64 %x, 40
1523  %result = urem i64 24, %x.shr
1524  ret i64 %result
1525}
1526
1527define i64 @v_test_urem24_pow2_k_num_i64(i64 %x) {
1528; GCN-LABEL: v_test_urem24_pow2_k_num_i64:
1529; GCN:       ; %bb.0:
1530; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1531; GCN-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1532; GCN-NEXT:    v_cvt_f32_u32_e32 v1, v0
1533; GCN-NEXT:    s_mov_b32 s4, 0x47000000
1534; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1535; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
1536; GCN-NEXT:    v_trunc_f32_e32 v2, v2
1537; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
1538; GCN-NEXT:    v_mad_f32 v2, -v2, v1, s4
1539; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1540; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1541; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
1542; GCN-NEXT:    v_mov_b32_e32 v1, 0
1543; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1544; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1545; GCN-NEXT:    s_setpc_b64 s[30:31]
1546;
1547; GCN-IR-LABEL: v_test_urem24_pow2_k_num_i64:
1548; GCN-IR:       ; %bb.0:
1549; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1550; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1551; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, v0
1552; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
1553; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
1554; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
1555; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1556; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
1557; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v1, s4
1558; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
1559; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1560; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
1561; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1562; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
1563; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1564; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1565  %x.shr = lshr i64 %x, 40
1566  %result = urem i64 32768, %x.shr
1567  ret i64 %result
1568}
1569
1570define i64 @v_test_urem24_pow2_k_den_i64(i64 %x) {
1571; GCN-LABEL: v_test_urem24_pow2_k_den_i64:
1572; GCN:       ; %bb.0:
1573; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1574; GCN-NEXT:    v_bfe_u32 v0, v1, 8, 15
1575; GCN-NEXT:    v_mov_b32_e32 v1, 0
1576; GCN-NEXT:    s_setpc_b64 s[30:31]
1577;
1578; GCN-IR-LABEL: v_test_urem24_pow2_k_den_i64:
1579; GCN-IR:       ; %bb.0:
1580; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1581; GCN-IR-NEXT:    v_lshrrev_b32_e32 v0, 8, v1
1582; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, v0
1583; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
1584; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38000000, v1
1585; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
1586; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
1587; GCN-IR-NEXT:    v_mad_f32 v1, -v2, s4, v1
1588; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
1589; GCN-IR-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
1590; GCN-IR-NEXT:    v_lshlrev_b32_e32 v1, 15, v1
1591; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
1592; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
1593; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
1594; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
1595  %x.shr = lshr i64 %x, 40
1596  %result = urem i64 %x.shr, 32768
1597  ret i64 %result
1598}
1599