1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=liveintervals,twoaddressinstruction,simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck %s
3
4# Check that LiveIntervals are correctly updated when eliminating REG_SEQUENCE.
5---
6name: f
7tracksRegLiveness: true
8body:             |
9  bb.0:
10    liveins: $vgpr0, $vgpr1
11
12    ; CHECK-LABEL: name: f
13    ; CHECK: liveins: $vgpr0, $vgpr1
14    ; CHECK-NEXT: {{  $}}
15    ; CHECK-NEXT: undef %2.sub0:vreg_64 = COPY $vgpr0
16    ; CHECK-NEXT: %2.sub1:vreg_64 = COPY $vgpr1
17    ; CHECK-NEXT: $vgpr2_vgpr3 = COPY %2
18    ; CHECK-NEXT: S_NOP 0, implicit $vgpr2_vgpr3
19    %0:vgpr_32 = COPY $vgpr0
20    %1:vgpr_32 = COPY $vgpr1
21    %35:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
22    $vgpr2_vgpr3 = COPY %35
23    S_NOP 0, implicit $vgpr2_vgpr3
24...
25