1; RUN: llc -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s 2 3; RUN: llc -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mattr=+trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s 4; RUN: llc -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mattr=-trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-HSA-TRAP %s 5; RUN: llc -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s 6 7; enable trap handler feature 8; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=TRAP-BIT -check-prefix=MESA-TRAP %s 9; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=TRAP-BIT %s 10 11; disable trap handler feature 12; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=NO-TRAP-BIT -check-prefix=NOMESA-TRAP %s 13; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT %s 14 15; RUN: llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s 16 17; GCN-WARNING: warning: <unknown>:0:0: in function hsa_debugtrap void (i32 addrspace(1)*): debugtrap handler not supported 18 19 20declare void @llvm.trap() #0 21declare void @llvm.debugtrap() #1 22 23; MESA-TRAP: .section .AMDGPU.config 24; MESA-TRAP: .long 47180 25; MESA-TRAP-NEXT: .long 208 26 27; NOMESA-TRAP: .section .AMDGPU.config 28; NOMESA-TRAP: .long 47180 29; NOMESA-TRAP-NEXT: .long 144 30 31; GCN-LABEL: {{^}}hsa_trap: 32; HSA-TRAP: enable_trap_handler = 0 33; HSA-TRAP: s_mov_b64 s[0:1], s[4:5] 34; HSA-TRAP: s_trap 2 35 36; for llvm.trap in hsa path without ABI, direct generate s_endpgm instruction without any warning information 37; NO-HSA-TRAP: enable_trap_handler = 0 38; NO-HSA-TRAP: s_endpgm 39; NO-HSA-TRAP: COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 40 41; TRAP-BIT: enable_trap_handler = 1 42; NO-TRAP-BIT: enable_trap_handler = 0 43; NO-MESA-TRAP: s_endpgm 44define amdgpu_kernel void @hsa_trap(i32 addrspace(1)* nocapture readonly %arg0) { 45 store volatile i32 1, i32 addrspace(1)* %arg0 46 call void @llvm.trap() 47 unreachable 48 store volatile i32 2, i32 addrspace(1)* %arg0 49 ret void 50} 51 52; MESA-TRAP: .section .AMDGPU.config 53; MESA-TRAP: .long 47180 54; MESA-TRAP-NEXT: .long 204 55 56; NOMESA-TRAP: .section .AMDGPU.config 57; NOMESA-TRAP: .long 47180 58; NOMESA-TRAP-NEXT: .long 140 59 60; GCN-LABEL: {{^}}hsa_debugtrap: 61; HSA-TRAP: enable_trap_handler = 0 62; HSA-TRAP: s_trap 3 63; HSA-TRAP: flat_store_dword v[0:1], v3 64 65; for llvm.debugtrap in non-hsa path without ABI, generate a warning and a s_endpgm instruction 66; NO-HSA-TRAP: enable_trap_handler = 0 67; NO-HSA-TRAP: s_endpgm 68 69; TRAP-BIT: enable_trap_handler = 1 70; NO-TRAP-BIT: enable_trap_handler = 0 71; NO-MESA-TRAP: s_endpgm 72define amdgpu_kernel void @hsa_debugtrap(i32 addrspace(1)* nocapture readonly %arg0) { 73 store volatile i32 1, i32 addrspace(1)* %arg0 74 call void @llvm.debugtrap() 75 store volatile i32 2, i32 addrspace(1)* %arg0 76 ret void 77} 78 79; For non-HSA path 80; GCN-LABEL: {{^}}trap: 81; TRAP-BIT: enable_trap_handler = 1 82; NO-TRAP-BIT: enable_trap_handler = 0 83; NO-HSA-TRAP: s_endpgm 84; NO-MESA-TRAP: s_endpgm 85define amdgpu_kernel void @trap(i32 addrspace(1)* nocapture readonly %arg0) { 86 store volatile i32 1, i32 addrspace(1)* %arg0 87 call void @llvm.trap() 88 unreachable 89 store volatile i32 2, i32 addrspace(1)* %arg0 90 ret void 91} 92 93; GCN-LABEL: {{^}}non_entry_trap: 94; TRAP-BIT: enable_trap_handler = 1 95; NO-TRAP-BIT: enable_trap_handler = 0 96 97; HSA-TRAP: BB{{[0-9]_[0-9]+}}: ; %trap 98; HSA-TRAP: s_mov_b64 s[0:1], s[4:5] 99; HSA-TRAP-NEXT: s_trap 2 100define amdgpu_kernel void @non_entry_trap(i32 addrspace(1)* nocapture readonly %arg0) local_unnamed_addr { 101entry: 102 %tmp29 = load volatile i32, i32 addrspace(1)* %arg0 103 %cmp = icmp eq i32 %tmp29, -1 104 br i1 %cmp, label %ret, label %trap 105 106trap: 107 call void @llvm.trap() 108 unreachable 109 110ret: 111 store volatile i32 3, i32 addrspace(1)* %arg0 112 ret void 113} 114 115attributes #0 = { nounwind noreturn } 116attributes #1 = { nounwind } 117