1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN -enable-var-scope %s
3; RUN: llc -global-isel -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN -enable-var-scope %s
4
5; Callee with SGPR and VGPR arguments
6define hidden amdgpu_gfx float @callee(float %v.arg0, float inreg %s.arg1) {
7; GCN-LABEL: callee:
8; GCN:       ; %bb.0:
9; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
10; GCN-NEXT:    v_add_f32_e32 v0, s4, v0
11; GCN-NEXT:    s_setpc_b64 s[30:31]
12  %add = fadd float %v.arg0, %s.arg1
13  ret float %add
14}
15
16define amdgpu_gfx float @caller(float %arg0) {
17; GCN-LABEL: caller:
18; GCN:       ; %bb.0:
19; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
20; GCN-NEXT:    v_add_f32_e32 v0, 1.0, v0
21; GCN-NEXT:    s_mov_b32 s4, 2.0
22; GCN-NEXT:    s_getpc_b64 s[6:7]
23; GCN-NEXT:    s_add_u32 s6, s6, callee@rel32@lo+4
24; GCN-NEXT:    s_addc_u32 s7, s7, callee@rel32@hi+12
25; GCN-NEXT:    s_setpc_b64 s[6:7]
26  %add = fadd float %arg0, 1.0
27  %call = tail call amdgpu_gfx float @callee(float %add, float inreg 2.0)
28  ret float %call
29}
30