1; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2
3
4; GCN-LABEL: {{^}}sub_var_var_i1:
5; GCN: s_xor_b64
6define amdgpu_kernel void @sub_var_var_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in0, i1 addrspace(1)* %in1) {
7  %a = load volatile i1, i1 addrspace(1)* %in0
8  %b = load volatile i1, i1 addrspace(1)* %in1
9  %sub = sub i1 %a, %b
10  store i1 %sub, i1 addrspace(1)* %out
11  ret void
12}
13
14; GCN-LABEL: {{^}}sub_var_imm_i1:
15; GCN: s_not_b64
16define amdgpu_kernel void @sub_var_imm_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) {
17  %a = load volatile i1, i1 addrspace(1)* %in
18  %sub = sub i1 %a, 1
19  store i1 %sub, i1 addrspace(1)* %out
20  ret void
21}
22
23; GCN-LABEL: {{^}}sub_i1_cf:
24; GCN: v_cmp_ne_u32_e32 vcc, 0, {{v[0-9]+}}
25; GCN-NEXT: s_not_b64 s{{\[[0-9]+:[0-9]+\]}}, vcc
26define amdgpu_kernel void @sub_i1_cf(i1 addrspace(1)* %out, i1 addrspace(1)* %a, i1 addrspace(1)* %b) {
27entry:
28  %tid = call i32 @llvm.amdgcn.workitem.id.x()
29  %d_cmp = icmp ult i32 %tid, 16
30  br i1 %d_cmp, label %if, label %else
31
32if:
33  %0 = load volatile i1, i1 addrspace(1)* %a
34  br label %endif
35
36else:
37  %1 = load volatile i1, i1 addrspace(1)* %b
38  br label %endif
39
40endif:
41  %2 = phi i1 [%0, %if], [%1, %else]
42  %3 = sub i1 %2, -1
43  store i1 %3, i1 addrspace(1)* %out
44  ret void
45}
46
47declare i32 @llvm.amdgcn.workitem.id.x()
48