1; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,WAVE64 %s
2; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,WAVE32 %s
3; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,WAVE32 %s
4
5
6; GCN-LABEL: {{^}}sub_var_var_i1:
7; WAVE32: s_xor_b32
8; WAVE64: s_xor_b64
9define amdgpu_kernel void @sub_var_var_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in0, i1 addrspace(1)* %in1) {
10  %a = load volatile i1, i1 addrspace(1)* %in0
11  %b = load volatile i1, i1 addrspace(1)* %in1
12  %sub = sub i1 %a, %b
13  store i1 %sub, i1 addrspace(1)* %out
14  ret void
15}
16
17; GCN-LABEL: {{^}}sub_var_imm_i1:
18; WAVE32: s_not_b32
19; WAVE64: s_not_b64
20define amdgpu_kernel void @sub_var_imm_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) {
21  %a = load volatile i1, i1 addrspace(1)* %in
22  %sub = sub i1 %a, 1
23  store i1 %sub, i1 addrspace(1)* %out
24  ret void
25}
26
27; GCN-LABEL: {{^}}sub_i1_cf:
28; GCN: ; %endif
29; WAVE32: s_not_b32
30; WAVE64: s_not_b64
31define amdgpu_kernel void @sub_i1_cf(i1 addrspace(1)* %out, i1 addrspace(1)* %a, i1 addrspace(1)* %b) {
32entry:
33  %tid = call i32 @llvm.amdgcn.workitem.id.x()
34  %d_cmp = icmp ult i32 %tid, 16
35  br i1 %d_cmp, label %if, label %else
36
37if:
38  %0 = load volatile i1, i1 addrspace(1)* %a
39  br label %endif
40
41else:
42  %1 = load volatile i1, i1 addrspace(1)* %b
43  br label %endif
44
45endif:
46  %2 = phi i1 [%0, %if], [%1, %else]
47  %3 = sub i1 %2, -1
48  store i1 %3, i1 addrspace(1)* %out
49  ret void
50}
51
52declare i32 @llvm.amdgcn.workitem.id.x()
53