1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx1010 %s -o - | FileCheck %s
3
4define i32 @xori64i32(i64 %a) {
5; CHECK-LABEL: xori64i32:
6; CHECK:       ; %bb.0:
7; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
8; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
9; CHECK-NEXT:    v_ashrrev_i32_e32 v0, 31, v1
10; CHECK-NEXT:    v_xor_b32_e32 v0, 0x7fffffff, v0
11; CHECK-NEXT:    s_setpc_b64 s[30:31]
12  %shr4 = ashr i64 %a, 63
13  %conv5 = trunc i64 %shr4 to i32
14  %xor = xor i32 %conv5, 2147483647
15  ret i32 %xor
16}
17
18define i64 @selecti64i64(i64 %a) {
19; CHECK-LABEL: selecti64i64:
20; CHECK:       ; %bb.0:
21; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
22; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
23; CHECK-NEXT:    v_ashrrev_i32_e32 v1, 31, v1
24; CHECK-NEXT:    v_xor_b32_e32 v0, 0x7fffffff, v1
25; CHECK-NEXT:    s_setpc_b64 s[30:31]
26  %c = icmp sgt i64 %a, -1
27  %s = select i1 %c, i64 2147483647, i64 -2147483648
28  ret i64 %s
29}
30
31define i32 @selecti64i32(i64 %a) {
32; CHECK-LABEL: selecti64i32:
33; CHECK:       ; %bb.0:
34; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
35; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
36; CHECK-NEXT:    v_ashrrev_i32_e32 v0, 31, v1
37; CHECK-NEXT:    v_xor_b32_e32 v0, 0x7fffffff, v0
38; CHECK-NEXT:    s_setpc_b64 s[30:31]
39  %c = icmp sgt i64 %a, -1
40  %s = select i1 %c, i32 2147483647, i32 -2147483648
41  ret i32 %s
42}
43
44define i64 @selecti32i64(i32 %a) {
45; CHECK-LABEL: selecti32i64:
46; CHECK:       ; %bb.0:
47; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
48; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
49; CHECK-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
50; CHECK-NEXT:    v_xor_b32_e32 v0, 0x7fffffff, v1
51; CHECK-NEXT:    v_ashrrev_i32_e32 v1, 31, v1
52; CHECK-NEXT:    s_setpc_b64 s[30:31]
53  %c = icmp sgt i32 %a, -1
54  %s = select i1 %c, i64 2147483647, i64 -2147483648
55  ret i64 %s
56}
57
58
59
60define i8 @xori32i8(i32 %a) {
61; CHECK-LABEL: xori32i8:
62; CHECK:       ; %bb.0:
63; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
64; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
65; CHECK-NEXT:    v_ashrrev_i32_e32 v0, 31, v0
66; CHECK-NEXT:    v_xor_b32_e32 v0, 0x54, v0
67; CHECK-NEXT:    s_setpc_b64 s[30:31]
68  %shr4 = ashr i32 %a, 31
69  %conv5 = trunc i32 %shr4 to i8
70  %xor = xor i8 %conv5, 84
71  ret i8 %xor
72}
73
74define i32 @selecti32i32(i32 %a) {
75; CHECK-LABEL: selecti32i32:
76; CHECK:       ; %bb.0:
77; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
78; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
79; CHECK-NEXT:    v_ashrrev_i32_e32 v0, 31, v0
80; CHECK-NEXT:    v_xor_b32_e32 v0, 0x54, v0
81; CHECK-NEXT:    s_setpc_b64 s[30:31]
82  %c = icmp sgt i32 %a, -1
83  %s = select i1 %c, i32 84, i32 -85
84  ret i32 %s
85}
86
87define i8 @selecti32i8(i32 %a) {
88; CHECK-LABEL: selecti32i8:
89; CHECK:       ; %bb.0:
90; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
91; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
92; CHECK-NEXT:    v_ashrrev_i32_e32 v0, 31, v0
93; CHECK-NEXT:    v_xor_b32_e32 v0, 0x54, v0
94; CHECK-NEXT:    s_setpc_b64 s[30:31]
95  %c = icmp sgt i32 %a, -1
96  %s = select i1 %c, i8 84, i8 -85
97  ret i8 %s
98}
99
100define i32 @selecti8i32(i8 %a) {
101; CHECK-LABEL: selecti8i32:
102; CHECK:       ; %bb.0:
103; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
104; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
105; CHECK-NEXT:    v_bfe_i32 v0, v0, 0, 8
106; CHECK-NEXT:    v_mov_b32_e32 v1, 0x54
107; CHECK-NEXT:    v_ashrrev_i16 v0, 7, v0
108; CHECK-NEXT:    v_xor_b32_sdwa v0, sext(v0), v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
109; CHECK-NEXT:    s_setpc_b64 s[30:31]
110  %c = icmp sgt i8 %a, -1
111  %s = select i1 %c, i32 84, i32 -85
112  ret i32 %s
113}
114
115define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
116; CHECK-LABEL: icmpasreq:
117; CHECK:       ; %bb.0:
118; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
119; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
120; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 0, v0
121; CHECK-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc_lo
122; CHECK-NEXT:    s_setpc_b64 s[30:31]
123  %sh = ashr i32 %input, 31
124  %c = icmp eq i32 %sh, -1
125  %s = select i1 %c, i32 %a, i32 %b
126  ret i32 %s
127}
128
129define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
130; CHECK-LABEL: icmpasrne:
131; CHECK:       ; %bb.0:
132; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
133; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
134; CHECK-NEXT:    v_cmp_lt_i32_e32 vcc_lo, -1, v0
135; CHECK-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc_lo
136; CHECK-NEXT:    s_setpc_b64 s[30:31]
137  %sh = ashr i32 %input, 31
138  %c = icmp ne i32 %sh, -1
139  %s = select i1 %c, i32 %a, i32 %b
140  ret i32 %s
141}
142
143define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
144; CHECK-LABEL: oneusecmp:
145; CHECK:       ; %bb.0:
146; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
147; CHECK-NEXT:    s_waitcnt_vscnt null, 0x0
148; CHECK-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 0, v0
149; CHECK-NEXT:    v_ashrrev_i32_e32 v3, 31, v0
150; CHECK-NEXT:    v_cndmask_b32_e32 v0, v1, v2, vcc_lo
151; CHECK-NEXT:    v_xad_u32 v0, 0x7f, v3, v0
152; CHECK-NEXT:    s_setpc_b64 s[30:31]
153  %c = icmp sle i32 %a, -1
154  %s = select i1 %c, i32 -128, i32 127
155  %s2 = select i1 %c, i32 %d, i32 %b
156  %x = add i32 %s, %s2
157  ret i32 %x
158}
159