1; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=MEMTIME -check-prefix=SIVI -check-prefix=GCN %s
2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=MEMTIME -check-prefix=SIVI -check-prefix=GCN %s
3; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=MEMTIME -check-prefix=GCN %s
4; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GETREG,GETREG-SDAG -check-prefix=GCN %s
5
6declare i64 @llvm.readcyclecounter() #0
7
8; GCN-LABEL: {{^}}test_readcyclecounter:
9; MEMTIME-DAG: s_memtime s{{\[[0-9]+:[0-9]+\]}}
10; GCN-DAG:     s_load_dwordx2
11; GCN-DAG:     lgkmcnt
12; MEMTIME:     store_dwordx2
13; SIVI-NOT:    lgkmcnt
14; MEMTIME:     s_memtime s{{\[[0-9]+:[0-9]+\]}}
15; MEMTIME:     store_dwordx2
16
17; GETREG-GISEL-DAG:  s_mov_b32 s[[SZERO:[0-9]+]], 0
18; GETREG-GISEL-DAG:  v_mov_b32_e32 v[[ZERO:[0-9]+]], s[[SZERO]]
19; GETREG-SDAG-DAG:  v_mov_b32_e32 v[[ZERO:[0-9]+]], 0
20; GETREG-DAG:  s_getreg_b32 [[CNT1:s[0-9]+]], hwreg(HW_REG_SHADER_CYCLES, 0, 20)
21; GETREG-DAG:  v_mov_b32_e32 v[[VCNT1:[0-9]+]], [[CNT1]]
22; GETREG:      global_store_dwordx2 v{{.+}}, v{{\[}}[[VCNT1]]:[[ZERO]]]
23; GETREG:      s_getreg_b32 [[CNT2:s[0-9]+]], hwreg(HW_REG_SHADER_CYCLES, 0, 20)
24; GETREG:      v_mov_b32_e32 v[[VCNT2:[0-9]+]], [[CNT2]]
25; GETREG:      global_store_dwordx2 v{{.+}}, v{{\[}}[[VCNT2]]:[[ZERO]]]
26
27define amdgpu_kernel void @test_readcyclecounter(i64 addrspace(1)* %out) #0 {
28  %cycle0 = call i64 @llvm.readcyclecounter()
29  store volatile i64 %cycle0, i64 addrspace(1)* %out
30
31  %cycle1 = call i64 @llvm.readcyclecounter()
32  store volatile i64 %cycle1, i64 addrspace(1)* %out
33  ret void
34}
35
36; This test used to crash in ScheduleDAG.
37;
38; GCN-LABEL: {{^}}test_readcyclecounter_smem:
39; MEMTIME-DAG: s_memtime
40; GCN-DAG:     s_load_dword
41; GETREG-DAG:  s_getreg_b32 s1, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
42define amdgpu_cs i32 @test_readcyclecounter_smem(i64 addrspace(4)* inreg %in) #0 {
43  %cycle0 = call i64 @llvm.readcyclecounter()
44  %in.v = load i64, i64 addrspace(4)* %in
45  %r.64 = add i64 %cycle0, %in.v
46  %r.32 = trunc i64 %r.64 to i32
47  ret i32 %r.32
48}
49
50attributes #0 = { nounwind }
51