1; RUN: opt -S -mtriple=amdgcn-- -structurizecfg -si-annotate-control-flow < %s | FileCheck -check-prefix=OPT %s
2; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3
4; OPT-LABEL: {{^}}define amdgpu_vs void @multi_else_break(
5; OPT: main_body:
6; OPT: LOOP.outer:
7; OPT: LOOP:
8; OPT:     [[if:%[0-9]+]] = call { i1, i64 } @llvm.amdgcn.if(
9; OPT:     [[if_exec:%[0-9]+]] = extractvalue { i1, i64 } [[if]], 1
10;
11; OPT: Flow:
12;
13; Ensure two else.break calls, for both the inner and outer loops
14
15; OPT:        call i64 @llvm.amdgcn.else.break(i64 [[if_exec]],
16; OPT-NEXT:   call i64 @llvm.amdgcn.else.break(i64 [[if_exec]],
17; OPT-NEXT:   call void @llvm.amdgcn.end.cf
18;
19; OPT: Flow1:
20
21; GCN-LABEL: {{^}}multi_else_break:
22
23; GCN: [[OUTER_LOOP:BB[0-9]+_[0-9]+]]: ; %LOOP.outer{{$}}
24
25; GCN: [[INNER_LOOP:BB[0-9]+_[0-9]+]]: ; %LOOP{{$}}
26; GCN: s_and_saveexec_b64 [[SAVE_BREAK:s\[[0-9]+:[0-9]+\]]], vcc
27
28; GCN: BB{{[0-9]+}}_{{[0-9]+}}: ; %Flow{{$}}
29; GCN-NEXT: ; in Loop: Header=[[INNER_LOOP]] Depth=2
30
31; Ensure extra or eliminated
32; GCN-NEXT: s_or_b64 exec, exec, [[SAVE_BREAK]]
33; GCN-NEXT: s_mov_b64
34; GCN-NEXT: s_and_b64 [[MASKED_SAVE_BREAK:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE_BREAK]]
35; GCN-NEXT: s_or_b64 [[OR_BREAK:s\[[0-9]+:[0-9]+\]]], [[MASKED_SAVE_BREAK]], s{{\[[0-9]+:[0-9]+\]}}
36; TODO: get rid of redundant loop counter moves
37; GCN-NEXT: v_mov_b32_e32
38; GCN-NEXT: s_andn2_b64 exec, exec, [[OR_BREAK]]
39; GCN-NEXT: s_cbranch_execnz [[INNER_LOOP]]
40
41; GCN: ; %bb.{{[0-9]+}}: ; %Flow2{{$}}
42; GCN-NEXT: ; in Loop: Header=[[OUTER_LOOP]] Depth=1
43
44; Ensure copy is eliminated
45; GCN-NEXT: s_or_b64 exec, exec, [[OR_BREAK]]
46; GCN-NEXT: s_and_b64 [[MASKED2_SAVE_BREAK:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE_BREAK]]
47; GCN-NEXT: s_or_b64 [[OUTER_OR_BREAK:s\[[0-9]+:[0-9]+\]]], [[MASKED2_SAVE_BREAK]], s{{\[[0-9]+:[0-9]+\]}}
48; GCN-NEXT: v_mov_b32_e32
49; GCN-NEXT: s_andn2_b64 exec, exec, [[OUTER_OR_BREAK]]
50; GCN-NEXT: s_cbranch_execnz [[OUTER_LOOP]]
51define amdgpu_vs void @multi_else_break(<4 x float> %vec, i32 %ub, i32 %cont) {
52main_body:
53  br label %LOOP.outer
54
55LOOP.outer:                                       ; preds = %ENDIF, %main_body
56  %tmp43 = phi i32 [ 0, %main_body ], [ %tmp47, %ENDIF ]
57  br label %LOOP
58
59LOOP:                                             ; preds = %ENDIF, %LOOP.outer
60  %tmp45 = phi i32 [ %tmp43, %LOOP.outer ], [ %tmp47, %ENDIF ]
61  %tmp47 = add i32 %tmp45, 1
62  %tmp48 = icmp slt i32 %tmp45, %ub
63  br i1 %tmp48, label %ENDIF, label %IF
64
65IF:                                               ; preds = %LOOP
66  ret void
67
68ENDIF:                                            ; preds = %LOOP
69  %tmp51 = icmp eq i32 %tmp47, %cont
70  br i1 %tmp51, label %LOOP, label %LOOP.outer
71}
72
73; OPT-LABEL: define amdgpu_kernel void @multi_if_break_loop(
74; OPT: llvm.amdgcn.break
75; OPT: llvm.amdgcn.loop
76; OPT: llvm.amdgcn.if.break
77; OPT: llvm.amdgcn.if.break
78; OPT: llvm.amdgcn.end.cf
79
80; GCN-LABEL: {{^}}multi_if_break_loop:
81; GCN: s_mov_b64 [[BREAK_REG:s\[[0-9]+:[0-9]+\]]], 0{{$}}
82
83; GCN: [[LOOP:BB[0-9]+_[0-9]+]]: ; %bb1{{$}}
84
85; Uses a copy intsead of an or
86; GCN: s_mov_b64 [[COPY:s\[[0-9]+:[0-9]+\]]], [[BREAK_REG]]
87; GCN: s_or_b64 [[BREAK_REG]], exec, [[BREAK_REG]]
88define amdgpu_kernel void @multi_if_break_loop(i32 %arg) #0 {
89bb:
90  %id = call i32 @llvm.amdgcn.workitem.id.x()
91  %tmp = sub i32 %id, %arg
92  br label %bb1
93
94bb1:
95  %lsr.iv = phi i32 [ undef, %bb ], [ %lsr.iv.next, %case0 ], [ %lsr.iv.next, %case1 ]
96  %lsr.iv.next = add i32 %lsr.iv, 1
97  %cmp0 = icmp slt i32 %lsr.iv.next, 0
98  %load0 = load volatile i32, i32 addrspace(1)* undef, align 4
99  switch i32 %load0, label %bb9 [
100    i32 0, label %case0
101    i32 1, label %case1
102  ]
103
104case0:
105  %load1 = load volatile i32, i32 addrspace(1)* undef, align 4
106  %cmp1 = icmp slt i32 %tmp, %load1
107  br i1 %cmp1, label %bb1, label %bb9
108
109case1:
110  %load2 = load volatile i32, i32 addrspace(1)* undef, align 4
111  %cmp2 = icmp slt i32 %tmp, %load2
112  br i1 %cmp2, label %bb1, label %bb9
113
114bb9:
115  ret void
116}
117
118declare i32 @llvm.amdgcn.workitem.id.x() #1
119
120attributes #0 = { nounwind }
121attributes #1 = { nounwind readnone }
122