1; RUN: llc -march=amdgcn -mattr=+mad-mac-f32-insts -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s 2; XUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s 3 4 ; FIXME: None of these trigger madmk emission anymore. It is still 5 ; possible, but requires the correct registers to be used which is 6 ; hard to trigger. 7 8declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 9declare float @llvm.fabs.f32(float) nounwind readnone 10 11; GCN-LABEL: {{^}}madmk_f32: 12; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}} 13; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 14; GCN: v_mac_f32_e32 [[VB]], 0x41200000, [[VA]] 15define amdgpu_kernel void @madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 { 16 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 17 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid 18 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 19 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 20 21 %a = load volatile float, float addrspace(1)* %gep.0, align 4 22 %b = load volatile float, float addrspace(1)* %gep.1, align 4 23 24 %mul = fmul float %a, 10.0 25 %madmk = fadd float %mul, %b 26 store float %madmk, float addrspace(1)* %out.gep, align 4 27 ret void 28} 29 30; GCN-LABEL: {{^}}madmk_2_use_f32: 31; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}} 32; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 33; GCN-DAG: buffer_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 34; GCN-DAG: v_mac_f32_e32 [[VB]], 0x41200000, [[VA]] 35; GCN-DAG: v_mac_f32_e32 [[VC]], 0x41200000, [[VA]] 36; GCN: s_endpgm 37define amdgpu_kernel void @madmk_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 { 38 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 39 40 %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid 41 %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 42 %in.gep.2 = getelementptr float, float addrspace(1)* %in.gep.0, i32 2 43 44 %out.gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid 45 %out.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 46 47 %a = load volatile float, float addrspace(1)* %in.gep.0, align 4 48 %b = load volatile float, float addrspace(1)* %in.gep.1, align 4 49 %c = load volatile float, float addrspace(1)* %in.gep.2, align 4 50 51 %mul0 = fmul float %a, 10.0 52 %mul1 = fmul float %a, 10.0 53 %madmk0 = fadd float %mul0, %b 54 %madmk1 = fadd float %mul1, %c 55 56 store float %madmk0, float addrspace(1)* %out.gep.0, align 4 57 store float %madmk1, float addrspace(1)* %out.gep.1, align 4 58 ret void 59} 60 61; We don't get any benefit if the constant is an inline immediate. 62; GCN-LABEL: {{^}}madmk_inline_imm_f32: 63; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}} 64; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 65; GCN: v_mac_f32_e32 [[VB]], 4.0, [[VA]] 66define amdgpu_kernel void @madmk_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 { 67 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 68 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid 69 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 70 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 71 72 %a = load volatile float, float addrspace(1)* %gep.0, align 4 73 %b = load volatile float, float addrspace(1)* %gep.1, align 4 74 75 %mul = fmul float %a, 4.0 76 %madmk = fadd float %mul, %b 77 store float %madmk, float addrspace(1)* %out.gep, align 4 78 ret void 79} 80 81; GCN-LABEL: {{^}}s_s_madmk_f32: 82; GCN-NOT: v_madmk_f32 83; GCN: v_mac_f32_e32 84; GCN: s_endpgm 85define amdgpu_kernel void @s_s_madmk_f32(float addrspace(1)* noalias %out, [8 x i32], float %a, [8 x i32], float %b) #0 { 86 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 87 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 88 89 %mul = fmul float %a, 10.0 90 %madmk = fadd float %mul, %b 91 store float %madmk, float addrspace(1)* %out.gep, align 4 92 ret void 93} 94 95; GCN-LABEL: {{^}}v_s_madmk_f32: 96; GCN-DAG: s_load_dword [[SREG:s[0-9]+]] 97; GCN-DAG: buffer_load_dword [[VREG1:v[0-9]+]] 98; GCN: v_mov_b32_e32 [[VREG2:v[0-9]+]], [[SREG]] 99; GCN: v_mac_f32_e32 [[VREG2]], 0x41200000, [[VREG1]] 100; GCN: s_endpgm 101define amdgpu_kernel void @v_s_madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in, float %b) #0 { 102 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 103 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid 104 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 105 %a = load float, float addrspace(1)* %gep.0, align 4 106 107 %mul = fmul float %a, 10.0 108 %madmk = fadd float %mul, %b 109 store float %madmk, float addrspace(1)* %out.gep, align 4 110 ret void 111} 112 113; GCN-LABEL: {{^}}scalar_vector_madmk_f32: 114; GCN-NOT: v_madmk_f32 115; GCN: v_mac_f32_e32 116; GCN: s_endpgm 117define amdgpu_kernel void @scalar_vector_madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in, float %a) #0 { 118 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 119 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid 120 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 121 %b = load float, float addrspace(1)* %gep.0, align 4 122 123 %mul = fmul float %a, 10.0 124 %madmk = fadd float %mul, %b 125 store float %madmk, float addrspace(1)* %out.gep, align 4 126 ret void 127} 128 129; GCN-LABEL: {{^}}no_madmk_src0_modifier_f32: 130; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}} 131; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 132; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x41200000 133; GCN: v_mad_f32 {{v[0-9]+}}, |[[VA]]|, [[SK]], [[VB]] 134define amdgpu_kernel void @no_madmk_src0_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 { 135 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 136 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid 137 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 138 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 139 140 %a = load volatile float, float addrspace(1)* %gep.0, align 4 141 %b = load volatile float, float addrspace(1)* %gep.1, align 4 142 143 %a.fabs = call float @llvm.fabs.f32(float %a) nounwind readnone 144 145 %mul = fmul float %a.fabs, 10.0 146 %madmk = fadd float %mul, %b 147 store float %madmk, float addrspace(1)* %out.gep, align 4 148 ret void 149} 150 151; GCN-LABEL: {{^}}no_madmk_src2_modifier_f32: 152; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}} 153; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 154; GCN: v_mad_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{[sv][0-9]+}}, |{{v[0-9]+}}| 155define amdgpu_kernel void @no_madmk_src2_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 { 156 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 157 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid 158 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 159 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 160 161 %a = load volatile float, float addrspace(1)* %gep.0, align 4 162 %b = load volatile float, float addrspace(1)* %gep.1, align 4 163 164 %b.fabs = call float @llvm.fabs.f32(float %b) nounwind readnone 165 166 %mul = fmul float %a, 10.0 167 %madmk = fadd float %mul, %b.fabs 168 store float %madmk, float addrspace(1)* %out.gep, align 4 169 ret void 170} 171 172; GCN-LABEL: {{^}}madmk_add_inline_imm_f32: 173; GCN: buffer_load_dword [[A:v[0-9]+]] 174; GCN: s_mov_b32 [[SK:s[0-9]+]], 0x41200000 175; GCN: v_mad_f32 {{v[0-9]+}}, [[A]], [[SK]], 2.0 176define amdgpu_kernel void @madmk_add_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 { 177 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 178 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid 179 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid 180 181 %a = load float, float addrspace(1)* %gep.0, align 4 182 183 %mul = fmul float %a, 10.0 184 %madmk = fadd float %mul, 2.0 185 store float %madmk, float addrspace(1)* %out.gep, align 4 186 ret void 187} 188 189; SI-LABEL: {{^}}kill_madmk_verifier_error: 190; SI: s_or_b64 191; SI: s_xor_b64 192; SI: v_mac_f32_e32 {{v[0-9]+}}, 0x472aee8c, {{v[0-9]+}} 193define amdgpu_kernel void @kill_madmk_verifier_error() #0 { 194bb: 195 br label %bb2 196 197bb1: ; preds = %bb2 198 ret void 199 200bb2: ; preds = %bb6, %bb 201 %tmp = phi float [ undef, %bb ], [ %tmp8, %bb6 ] 202 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #1 203 %f_tid = bitcast i32 %tid to float 204 %tmp3 = fsub float %f_tid, %tmp 205 %tmp5 = fcmp oeq float %tmp3, 1.000000e+04 206 br i1 %tmp5, label %bb1, label %bb6 207 208bb6: ; preds = %bb2 209 %tmp7 = fmul float %tmp, 0x40E55DD180000000 210 %tmp8 = fadd float %tmp7, %tmp 211 br label %bb2 212} 213 214declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 215 216attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" } 217attributes #1 = { nounwind readnone } 218