1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck %s
3; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s
4; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck %s
5
6define amdgpu_gs void @test_fptrunc_round_upward(float %a, i32 %data0, <4 x i32> %data1, half addrspace(1)* %out) {
7; CHECK-LABEL: test_fptrunc_round_upward:
8; CHECK:       ; %bb.0:
9; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1
10; CHECK-NEXT:    v_cvt_f16_f32_e32 v0, v0
11; CHECK-NEXT:    global_store_short v[6:7], v0, off
12; CHECK-NEXT:    s_endpgm
13  %res = call half @llvm.fptrunc.round(float %a, metadata !"round.upward")
14  store half %res, half addrspace(1)* %out, align 4
15  ret void
16}
17
18define amdgpu_gs void @test_fptrunc_round_downward(float %a, i32 %data0, <4 x i32> %data1, half addrspace(1)* %out) {
19; CHECK-LABEL: test_fptrunc_round_downward:
20; CHECK:       ; %bb.0:
21; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1
22; CHECK-NEXT:    v_cvt_f16_f32_e32 v0, v0
23; CHECK-NEXT:    global_store_short v[6:7], v0, off
24; CHECK-NEXT:    s_endpgm
25  %res = call half @llvm.fptrunc.round(float %a, metadata !"round.downward")
26  store half %res, half addrspace(1)* %out, align 4
27  ret void
28}
29
30define amdgpu_gs void @test_fptrunc_round_upward_multiple_calls(float %a, float %b, i32 %data0, <4 x i32> %data1, half addrspace(1)* %out) {
31; CHECK-LABEL: test_fptrunc_round_upward_multiple_calls:
32; CHECK:       ; %bb.0:
33; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1
34; CHECK-NEXT:    v_cvt_f16_f32_e32 v0, v0
35; CHECK-NEXT:    v_cvt_f16_f32_e32 v2, v1
36; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 2
37; CHECK-NEXT:    v_cvt_f16_f32_e32 v1, v1
38; CHECK-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 0
39; CHECK-NEXT:    v_add_f16_e32 v0, v0, v2
40; CHECK-NEXT:    v_add_f16_e32 v0, v1, v0
41; CHECK-NEXT:    global_store_short v[7:8], v0, off
42; CHECK-NEXT:    s_endpgm
43  %res1 = call half @llvm.fptrunc.round(float %a, metadata !"round.upward")
44  %res2 = call half @llvm.fptrunc.round(float %b, metadata !"round.upward")
45  %res3 = call half @llvm.fptrunc.round(float %b, metadata !"round.downward")
46  %res4 = fadd half %res1, %res2
47  %res5 = fadd half %res3, %res4
48  store half %res5, half addrspace(1)* %out, align 4
49  ret void
50}
51
52declare half @llvm.fptrunc.round(float, metadata)
53