1; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
3; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s
4
5; GCN-LABEL: {{^}}gs_const:
6; GCN-NOT: v_cmpx
7; GCN: s_mov_b64 exec, 0
8define amdgpu_gs void @gs_const() {
9  %tmp = icmp ule i32 0, 3
10  %tmp1 = select i1 %tmp, float 1.000000e+00, float -1.000000e+00
11  %c1 = fcmp oge float %tmp1, 0.0
12  call void @llvm.amdgcn.kill(i1 %c1)
13  %tmp2 = icmp ule i32 3, 0
14  %tmp3 = select i1 %tmp2, float 1.000000e+00, float -1.000000e+00
15  %c2 = fcmp oge float %tmp3, 0.0
16  call void @llvm.amdgcn.kill(i1 %c2)
17  call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
18  ret void
19}
20
21; GCN-LABEL: {{^}}vcc_implicit_def:
22; GCN: v_cmp_nle_f32_e32 vcc, 0, v{{[0-9]+}}
23; GCN: v_cmp_gt_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], 0, v{{[0-9]+}}
24; GCN: s_andn2_b64 exec, exec, vcc
25; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1.0, [[CMP]]
26define amdgpu_ps void @vcc_implicit_def(float %arg13, float %arg14) {
27  %tmp0 = fcmp olt float %arg13, 0.000000e+00
28  %c1 = fcmp oge float %arg14, 0.0
29  call void @llvm.amdgcn.kill(i1 %c1)
30  %tmp1 = select i1 %tmp0, float 1.000000e+00, float 0.000000e+00
31  call void @llvm.amdgcn.exp.f32(i32 1, i32 15, float %tmp1, float %tmp1, float %tmp1, float %tmp1, i1 true, i1 true) #0
32  call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
33  ret void
34}
35
36; GCN-LABEL: {{^}}true:
37; GCN-NEXT: %bb.
38; GCN-NEXT: s_endpgm
39define amdgpu_gs void @true() {
40  call void @llvm.amdgcn.kill(i1 true)
41  ret void
42}
43
44; GCN-LABEL: {{^}}false:
45; GCN-NOT: v_cmpx
46; GCN: s_mov_b64 exec, 0
47define amdgpu_gs void @false() {
48  call void @llvm.amdgcn.kill(i1 false)
49  call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
50  ret void
51}
52
53; GCN-LABEL: {{^}}and:
54; GCN: v_cmp_lt_i32
55; GCN: v_cmp_lt_i32
56; GCN: s_or_b64 s[0:1]
57; GCN: s_xor_b64 s[0:1], s[0:1], exec
58; GCN: s_andn2_b64 s[2:3], s[2:3], s[0:1]
59; GCN: s_and_b64 exec, exec, s[2:3]
60define amdgpu_gs void @and(i32 %a, i32 %b, i32 %c, i32 %d) {
61  %c1 = icmp slt i32 %a, %b
62  %c2 = icmp slt i32 %c, %d
63  %x = or i1 %c1, %c2
64  call void @llvm.amdgcn.kill(i1 %x)
65  call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
66  ret void
67}
68
69; GCN-LABEL: {{^}}andn2:
70; GCN: v_cmp_lt_i32
71; GCN: v_cmp_lt_i32
72; GCN: s_xor_b64 s[0:1]
73; GCN: s_andn2_b64 s[2:3], s[2:3], s[0:1]
74; GCN: s_and_b64 exec, exec, s[2:3]
75define amdgpu_gs void @andn2(i32 %a, i32 %b, i32 %c, i32 %d) {
76  %c1 = icmp slt i32 %a, %b
77  %c2 = icmp slt i32 %c, %d
78  %x = xor i1 %c1, %c2
79  %y = xor i1 %x, 1
80  call void @llvm.amdgcn.kill(i1 %y)
81  call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
82  ret void
83}
84
85; GCN-LABEL: {{^}}oeq:
86; GCN: v_cmp_neq_f32
87define amdgpu_gs void @oeq(float %a) {
88  %c1 = fcmp oeq float %a, 0.0
89  call void @llvm.amdgcn.kill(i1 %c1)
90  call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
91  ret void
92}
93
94; GCN-LABEL: {{^}}ogt:
95; GCN: v_cmp_nlt_f32
96define amdgpu_gs void @ogt(float %a) {
97  %c1 = fcmp ogt float %a, 0.0
98  call void @llvm.amdgcn.kill(i1 %c1)
99  call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
100  ret void
101}
102
103; GCN-LABEL: {{^}}oge:
104; GCN: v_cmp_nle_f32
105define amdgpu_gs void @oge(float %a) {
106  %c1 = fcmp oge float %a, 0.0
107  call void @llvm.amdgcn.kill(i1 %c1)
108  call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
109  ret void
110}
111
112; GCN-LABEL: {{^}}olt:
113; GCN: v_cmp_ngt_f32
114define amdgpu_gs void @olt(float %a) {
115  %c1 = fcmp olt float %a, 0.0
116  call void @llvm.amdgcn.kill(i1 %c1)
117  call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
118  ret void
119}
120
121; GCN-LABEL: {{^}}ole:
122; GCN: v_cmp_nge_f32
123define amdgpu_gs void @ole(float %a) {
124  %c1 = fcmp ole float %a, 0.0
125  call void @llvm.amdgcn.kill(i1 %c1)
126  call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
127  ret void
128}
129
130; GCN-LABEL: {{^}}one:
131; GCN: v_cmp_nlg_f32
132define amdgpu_gs void @one(float %a) {
133  %c1 = fcmp one float %a, 0.0
134  call void @llvm.amdgcn.kill(i1 %c1)
135  call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
136  ret void
137}
138
139; GCN-LABEL: {{^}}ord:
140; GCN: v_cmp_o_f32
141define amdgpu_gs void @ord(float %a) {
142  %c1 = fcmp ord float %a, 0.0
143  call void @llvm.amdgcn.kill(i1 %c1)
144  call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
145  ret void
146}
147
148; GCN-LABEL: {{^}}uno:
149; GCN: v_cmp_u_f32
150define amdgpu_gs void @uno(float %a) {
151  %c1 = fcmp uno float %a, 0.0
152  call void @llvm.amdgcn.kill(i1 %c1)
153  call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
154  ret void
155}
156
157; GCN-LABEL: {{^}}ueq:
158; GCN: v_cmp_lg_f32
159define amdgpu_gs void @ueq(float %a) {
160  %c1 = fcmp ueq float %a, 0.0
161  call void @llvm.amdgcn.kill(i1 %c1)
162  call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
163  ret void
164}
165
166; GCN-LABEL: {{^}}ugt:
167; GCN: v_cmp_ge_f32
168define amdgpu_gs void @ugt(float %a) {
169  %c1 = fcmp ugt float %a, 0.0
170  call void @llvm.amdgcn.kill(i1 %c1)
171  call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
172  ret void
173}
174
175; GCN-LABEL: {{^}}uge:
176; GCN: v_cmp_gt_f32_e32 vcc, -1.0
177define amdgpu_gs void @uge(float %a) {
178  %c1 = fcmp uge float %a, -1.0
179  call void @llvm.amdgcn.kill(i1 %c1)
180  call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
181  ret void
182}
183
184; GCN-LABEL: {{^}}ult:
185; GCN: v_cmp_le_f32_e32 vcc, -2.0
186define amdgpu_gs void @ult(float %a) {
187  %c1 = fcmp ult float %a, -2.0
188  call void @llvm.amdgcn.kill(i1 %c1)
189  call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
190  ret void
191}
192
193; GCN-LABEL: {{^}}ule:
194; GCN: v_cmp_lt_f32_e32 vcc, 2.0
195define amdgpu_gs void @ule(float %a) {
196  %c1 = fcmp ule float %a, 2.0
197  call void @llvm.amdgcn.kill(i1 %c1)
198  call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
199  ret void
200}
201
202; GCN-LABEL: {{^}}une:
203; GCN: v_cmp_eq_f32_e32 vcc, 0
204define amdgpu_gs void @une(float %a) {
205  %c1 = fcmp une float %a, 0.0
206  call void @llvm.amdgcn.kill(i1 %c1)
207  call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
208  ret void
209}
210
211; GCN-LABEL: {{^}}neg_olt:
212; GCN: v_cmp_gt_f32_e32 vcc, 1.0
213define amdgpu_gs void @neg_olt(float %a) {
214  %c1 = fcmp olt float %a, 1.0
215  %c2 = xor i1 %c1, 1
216  call void @llvm.amdgcn.kill(i1 %c2)
217  call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0)
218  ret void
219}
220
221; GCN-LABEL: {{^}}fcmp_x2:
222; FIXME: LLVM should be able to combine these fcmp opcodes.
223; SI: v_cmp_lt_f32_e32 vcc, s{{[0-9]+}}, v0
224; GFX10: v_cmp_lt_f32_e32 vcc, 0x3e800000, v0
225; GCN: v_cndmask_b32
226; GCN: v_cmp_nle_f32
227define amdgpu_ps void @fcmp_x2(float %a) #0 {
228  %ogt = fcmp nsz ogt float %a, 2.500000e-01
229  %k = select i1 %ogt, float -1.000000e+00, float 0.000000e+00
230  %c = fcmp nsz oge float %k, 0.000000e+00
231  call void @llvm.amdgcn.kill(i1 %c) #1
232  ret void
233}
234
235; Note: an almost identical test for this exists in llvm.amdgcn.wqm.vote.ll
236; GCN-LABEL: {{^}}wqm:
237; GCN: v_cmp_neq_f32_e32 vcc, 0
238; GCN-DAG: s_wqm_b64 s[2:3], vcc
239; GCN-DAG: s_mov_b64 s[0:1], exec
240; GCN: s_xor_b64 s[2:3], s[2:3], exec
241; GCN: s_andn2_b64 s[0:1], s[0:1], s[2:3]
242; GCN: s_and_b64 exec, exec, s[0:1]
243define amdgpu_ps float @wqm(float %a) {
244  %c1 = fcmp une float %a, 0.0
245  %c2 = call i1 @llvm.amdgcn.wqm.vote(i1 %c1)
246  call void @llvm.amdgcn.kill(i1 %c2)
247  ret float 0.0
248}
249
250; This checks that we use the 64-bit encoding when the operand is a SGPR.
251; GCN-LABEL: {{^}}test_sgpr:
252; GCN: v_cmp_nle_f32_e64
253define amdgpu_ps void @test_sgpr(float inreg %a) #0 {
254  %c = fcmp ole float %a, 1.000000e+00
255  call void @llvm.amdgcn.kill(i1 %c) #1
256  ret void
257}
258
259; GCN-LABEL: {{^}}test_non_inline_imm_sgpr:
260; GCN-NOT: v_cmp_le_f32_e64
261define amdgpu_ps void @test_non_inline_imm_sgpr(float inreg %a) #0 {
262  %c = fcmp ole float %a, 1.500000e+00
263  call void @llvm.amdgcn.kill(i1 %c) #1
264  ret void
265}
266
267; GCN-LABEL: {{^}}test_scc_liveness:
268; GCN: s_cmp
269; GCN: s_and_b64 exec
270; GCN: s_cmp
271; GCN: s_cbranch_scc
272define amdgpu_ps void @test_scc_liveness() #0 {
273main_body:
274  br label %loop3
275
276loop3:                                            ; preds = %loop3, %main_body
277  %tmp = phi i32 [ 0, %main_body ], [ %tmp5, %loop3 ]
278  %tmp1 = icmp sgt i32 %tmp, 0
279  call void @llvm.amdgcn.kill(i1 %tmp1) #1
280  %tmp5 = add i32 %tmp, 1
281  br i1 %tmp1, label %endloop15, label %loop3
282
283endloop15:                                        ; preds = %loop3
284  ret void
285}
286
287; Check this compiles.
288; If kill is marked as defining VCC then this will fail with live interval issues.
289; GCN-LABEL: {{^}}kill_with_loop_exit:
290; GCN: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec
291; GCN: s_andn2_b64 [[LIVE]], [[LIVE]], exec
292; GCN-NEXT: s_cbranch_scc0
293define amdgpu_ps void @kill_with_loop_exit(float inreg %inp0, float inreg %inp1, <4 x i32> inreg %inp2, float inreg %inp3) {
294.entry:
295  %tmp24 = fcmp olt float %inp0, 1.280000e+02
296  %tmp25 = fcmp olt float %inp1, 1.280000e+02
297  %tmp26 = and i1 %tmp24, %tmp25
298  br i1 %tmp26, label %bb35, label %.preheader1.preheader
299
300.preheader1.preheader:                            ; preds = %.entry
301  %tmp31 = fcmp ogt float %inp3, 0.0
302  br label %bb
303
304bb:                                               ; preds = %bb, %.preheader1.preheader
305  %tmp30 = phi float [ %tmp32, %bb ], [ 1.500000e+00, %.preheader1.preheader ]
306  %tmp32 = fadd reassoc nnan nsz arcp contract float %tmp30, 2.500000e-01
307  %tmp34 = fadd reassoc nnan nsz arcp contract float %tmp30, 2.500000e-01
308  br i1 %tmp31, label %bb, label %bb33
309
310bb33:                                             ; preds = %bb
311  call void @llvm.amdgcn.kill(i1 false)
312  br label %bb35
313
314bb35:                                             ; preds = %bb33, %.entry
315  %tmp36 = phi float [ %tmp34, %bb33 ], [ 1.000000e+00, %.entry ]
316  call void @llvm.amdgcn.exp.f32(i32 immarg 0, i32 immarg 15, float %tmp36, float %tmp36, float %tmp36, float %tmp36, i1 immarg true, i1 immarg true) #3
317  ret void
318}
319
320declare void @llvm.amdgcn.kill(i1) #0
321declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
322declare void @llvm.amdgcn.s.sendmsg(i32, i32) #0
323declare i1 @llvm.amdgcn.wqm.vote(i1)
324
325attributes #0 = { nounwind }
326