1; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s 2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s 3; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s 4; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX10 %s 5 6; GCN-LABEL: {{^}}gs_const: 7; GCN-NOT: v_cmpx 8; GCN: s_mov_b64 exec, 0 9define amdgpu_gs void @gs_const() { 10 %tmp = icmp ule i32 0, 3 11 %tmp1 = select i1 %tmp, float 1.000000e+00, float -1.000000e+00 12 %c1 = fcmp oge float %tmp1, 0.0 13 call void @llvm.amdgcn.kill(i1 %c1) 14 %tmp2 = icmp ule i32 3, 0 15 %tmp3 = select i1 %tmp2, float 1.000000e+00, float -1.000000e+00 16 %c2 = fcmp oge float %tmp3, 0.0 17 call void @llvm.amdgcn.kill(i1 %c2) 18 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) 19 ret void 20} 21 22; GCN-LABEL: {{^}}vcc_implicit_def: 23; GCN: v_cmp_nle_f32_e32 vcc, 0, v{{[0-9]+}} 24; GCN: v_cmp_gt_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], 0, v{{[0-9]+}} 25; GCN: s_and{{n2|_not1}}_b64 exec, exec, vcc 26; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1.0, [[CMP]] 27define amdgpu_ps void @vcc_implicit_def(float %arg13, float %arg14) { 28 %tmp0 = fcmp olt float %arg13, 0.000000e+00 29 %c1 = fcmp oge float %arg14, 0.0 30 call void @llvm.amdgcn.kill(i1 %c1) 31 %tmp1 = select i1 %tmp0, float 1.000000e+00, float 0.000000e+00 32 call void @llvm.amdgcn.exp.f32(i32 1, i32 15, float %tmp1, float %tmp1, float %tmp1, float %tmp1, i1 true, i1 true) #0 33 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) 34 ret void 35} 36 37; GCN-LABEL: {{^}}true: 38; GCN-NEXT: %bb. 39; GCN-NEXT: s_endpgm 40define amdgpu_gs void @true() { 41 call void @llvm.amdgcn.kill(i1 true) 42 ret void 43} 44 45; GCN-LABEL: {{^}}false: 46; GCN-NOT: v_cmpx 47; GCN: s_mov_b64 exec, 0 48define amdgpu_gs void @false() { 49 call void @llvm.amdgcn.kill(i1 false) 50 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) 51 ret void 52} 53 54; GCN-LABEL: {{^}}and: 55; GCN: v_cmp_lt_i32 56; GCN: v_cmp_lt_i32 57; GCN: s_or_b64 s[0:1] 58; GCN: s_xor_b64 s[0:1], s[0:1], exec 59; GCN: s_and{{n2|_not1}}_b64 s[2:3], s[2:3], s[0:1] 60; GCN: s_and_b64 exec, exec, s[2:3] 61define amdgpu_gs void @and(i32 %a, i32 %b, i32 %c, i32 %d) { 62 %c1 = icmp slt i32 %a, %b 63 %c2 = icmp slt i32 %c, %d 64 %x = or i1 %c1, %c2 65 call void @llvm.amdgcn.kill(i1 %x) 66 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) 67 ret void 68} 69 70; GCN-LABEL: {{^}}andn2: 71; GCN: v_cmp_lt_i32 72; GCN: v_cmp_lt_i32 73; GCN: s_xor_b64 s[0:1] 74; GCN: s_and{{n2|_not1}}_b64 s[2:3], s[2:3], s[0:1] 75; GCN: s_and_b64 exec, exec, s[2:3] 76define amdgpu_gs void @andn2(i32 %a, i32 %b, i32 %c, i32 %d) { 77 %c1 = icmp slt i32 %a, %b 78 %c2 = icmp slt i32 %c, %d 79 %x = xor i1 %c1, %c2 80 %y = xor i1 %x, 1 81 call void @llvm.amdgcn.kill(i1 %y) 82 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) 83 ret void 84} 85 86; GCN-LABEL: {{^}}oeq: 87; GCN: v_cmp_neq_f32 88define amdgpu_gs void @oeq(float %a) { 89 %c1 = fcmp oeq float %a, 0.0 90 call void @llvm.amdgcn.kill(i1 %c1) 91 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) 92 ret void 93} 94 95; GCN-LABEL: {{^}}ogt: 96; GCN: v_cmp_nlt_f32 97define amdgpu_gs void @ogt(float %a) { 98 %c1 = fcmp ogt float %a, 0.0 99 call void @llvm.amdgcn.kill(i1 %c1) 100 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) 101 ret void 102} 103 104; GCN-LABEL: {{^}}oge: 105; GCN: v_cmp_nle_f32 106define amdgpu_gs void @oge(float %a) { 107 %c1 = fcmp oge float %a, 0.0 108 call void @llvm.amdgcn.kill(i1 %c1) 109 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) 110 ret void 111} 112 113; GCN-LABEL: {{^}}olt: 114; GCN: v_cmp_ngt_f32 115define amdgpu_gs void @olt(float %a) { 116 %c1 = fcmp olt float %a, 0.0 117 call void @llvm.amdgcn.kill(i1 %c1) 118 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) 119 ret void 120} 121 122; GCN-LABEL: {{^}}ole: 123; GCN: v_cmp_nge_f32 124define amdgpu_gs void @ole(float %a) { 125 %c1 = fcmp ole float %a, 0.0 126 call void @llvm.amdgcn.kill(i1 %c1) 127 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) 128 ret void 129} 130 131; GCN-LABEL: {{^}}one: 132; GCN: v_cmp_nlg_f32 133define amdgpu_gs void @one(float %a) { 134 %c1 = fcmp one float %a, 0.0 135 call void @llvm.amdgcn.kill(i1 %c1) 136 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) 137 ret void 138} 139 140; GCN-LABEL: {{^}}ord: 141; GCN: v_cmp_o_f32 142define amdgpu_gs void @ord(float %a) { 143 %c1 = fcmp ord float %a, 0.0 144 call void @llvm.amdgcn.kill(i1 %c1) 145 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) 146 ret void 147} 148 149; GCN-LABEL: {{^}}uno: 150; GCN: v_cmp_u_f32 151define amdgpu_gs void @uno(float %a) { 152 %c1 = fcmp uno float %a, 0.0 153 call void @llvm.amdgcn.kill(i1 %c1) 154 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) 155 ret void 156} 157 158; GCN-LABEL: {{^}}ueq: 159; GCN: v_cmp_lg_f32 160define amdgpu_gs void @ueq(float %a) { 161 %c1 = fcmp ueq float %a, 0.0 162 call void @llvm.amdgcn.kill(i1 %c1) 163 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) 164 ret void 165} 166 167; GCN-LABEL: {{^}}ugt: 168; GCN: v_cmp_ge_f32 169define amdgpu_gs void @ugt(float %a) { 170 %c1 = fcmp ugt float %a, 0.0 171 call void @llvm.amdgcn.kill(i1 %c1) 172 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) 173 ret void 174} 175 176; GCN-LABEL: {{^}}uge: 177; GCN: v_cmp_gt_f32_e32 vcc, -1.0 178define amdgpu_gs void @uge(float %a) { 179 %c1 = fcmp uge float %a, -1.0 180 call void @llvm.amdgcn.kill(i1 %c1) 181 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) 182 ret void 183} 184 185; GCN-LABEL: {{^}}ult: 186; GCN: v_cmp_le_f32_e32 vcc, -2.0 187define amdgpu_gs void @ult(float %a) { 188 %c1 = fcmp ult float %a, -2.0 189 call void @llvm.amdgcn.kill(i1 %c1) 190 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) 191 ret void 192} 193 194; GCN-LABEL: {{^}}ule: 195; GCN: v_cmp_lt_f32_e32 vcc, 2.0 196define amdgpu_gs void @ule(float %a) { 197 %c1 = fcmp ule float %a, 2.0 198 call void @llvm.amdgcn.kill(i1 %c1) 199 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) 200 ret void 201} 202 203; GCN-LABEL: {{^}}une: 204; GCN: v_cmp_eq_f32_e32 vcc, 0 205define amdgpu_gs void @une(float %a) { 206 %c1 = fcmp une float %a, 0.0 207 call void @llvm.amdgcn.kill(i1 %c1) 208 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) 209 ret void 210} 211 212; GCN-LABEL: {{^}}neg_olt: 213; GCN: v_cmp_gt_f32_e32 vcc, 1.0 214define amdgpu_gs void @neg_olt(float %a) { 215 %c1 = fcmp olt float %a, 1.0 216 %c2 = xor i1 %c1, 1 217 call void @llvm.amdgcn.kill(i1 %c2) 218 call void @llvm.amdgcn.s.sendmsg(i32 3, i32 0) 219 ret void 220} 221 222; GCN-LABEL: {{^}}fcmp_x2: 223; FIXME: LLVM should be able to combine these fcmp opcodes. 224; SI: v_cmp_lt_f32_e32 vcc, s{{[0-9]+}}, v0 225; GFX10: v_cmp_lt_f32_e32 vcc, 0x3e800000, v0 226; GCN: v_cndmask_b32 227; GCN: v_cmp_nle_f32 228define amdgpu_ps void @fcmp_x2(float %a) #0 { 229 %ogt = fcmp nsz ogt float %a, 2.500000e-01 230 %k = select i1 %ogt, float -1.000000e+00, float 0.000000e+00 231 %c = fcmp nsz oge float %k, 0.000000e+00 232 call void @llvm.amdgcn.kill(i1 %c) #1 233 ret void 234} 235 236; Note: an almost identical test for this exists in llvm.amdgcn.wqm.vote.ll 237; GCN-LABEL: {{^}}wqm: 238; GCN: v_cmp_neq_f32_e32 vcc, 0 239; GCN-DAG: s_wqm_b64 s[2:3], vcc 240; GCN-DAG: s_mov_b64 s[0:1], exec 241; GCN: s_xor_b64 s[2:3], s[2:3], exec 242; GCN: s_and{{n2|_not1}}_b64 s[0:1], s[0:1], s[2:3] 243; GCN: s_and_b64 exec, exec, s[0:1] 244define amdgpu_ps float @wqm(float %a) { 245 %c1 = fcmp une float %a, 0.0 246 %c2 = call i1 @llvm.amdgcn.wqm.vote(i1 %c1) 247 call void @llvm.amdgcn.kill(i1 %c2) 248 ret float 0.0 249} 250 251; This checks that we use the 64-bit encoding when the operand is a SGPR. 252; GCN-LABEL: {{^}}test_sgpr: 253; GCN: v_cmp_nle_f32_e64 254define amdgpu_ps void @test_sgpr(float inreg %a) #0 { 255 %c = fcmp ole float %a, 1.000000e+00 256 call void @llvm.amdgcn.kill(i1 %c) #1 257 ret void 258} 259 260; GCN-LABEL: {{^}}test_non_inline_imm_sgpr: 261; GCN-NOT: v_cmp_le_f32_e64 262define amdgpu_ps void @test_non_inline_imm_sgpr(float inreg %a) #0 { 263 %c = fcmp ole float %a, 1.500000e+00 264 call void @llvm.amdgcn.kill(i1 %c) #1 265 ret void 266} 267 268; GCN-LABEL: {{^}}test_scc_liveness: 269; GCN: s_cmp 270; GCN: s_and_b64 exec 271; GCN: s_cmp 272; GCN: s_cbranch_scc 273define amdgpu_ps void @test_scc_liveness() #0 { 274main_body: 275 br label %loop3 276 277loop3: ; preds = %loop3, %main_body 278 %tmp = phi i32 [ 0, %main_body ], [ %tmp5, %loop3 ] 279 %tmp1 = icmp sgt i32 %tmp, 0 280 call void @llvm.amdgcn.kill(i1 %tmp1) #1 281 %tmp5 = add i32 %tmp, 1 282 br i1 %tmp1, label %endloop15, label %loop3 283 284endloop15: ; preds = %loop3 285 ret void 286} 287 288; Check this compiles. 289; If kill is marked as defining VCC then this will fail with live interval issues. 290; GCN-LABEL: {{^}}kill_with_loop_exit: 291; GCN: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec 292; GCN: s_and{{n2|_not1}}_b64 [[LIVE]], [[LIVE]], exec 293; GCN-NEXT: s_cbranch_scc0 294define amdgpu_ps void @kill_with_loop_exit(float inreg %inp0, float inreg %inp1, <4 x i32> inreg %inp2, float inreg %inp3) { 295.entry: 296 %tmp24 = fcmp olt float %inp0, 1.280000e+02 297 %tmp25 = fcmp olt float %inp1, 1.280000e+02 298 %tmp26 = and i1 %tmp24, %tmp25 299 br i1 %tmp26, label %bb35, label %.preheader1.preheader 300 301.preheader1.preheader: ; preds = %.entry 302 %tmp31 = fcmp ogt float %inp3, 0.0 303 br label %bb 304 305bb: ; preds = %bb, %.preheader1.preheader 306 %tmp30 = phi float [ %tmp32, %bb ], [ 1.500000e+00, %.preheader1.preheader ] 307 %tmp32 = fadd reassoc nnan nsz arcp contract float %tmp30, 2.500000e-01 308 %tmp34 = fadd reassoc nnan nsz arcp contract float %tmp30, 2.500000e-01 309 br i1 %tmp31, label %bb, label %bb33 310 311bb33: ; preds = %bb 312 call void @llvm.amdgcn.kill(i1 false) 313 br label %bb35 314 315bb35: ; preds = %bb33, %.entry 316 %tmp36 = phi float [ %tmp34, %bb33 ], [ 1.000000e+00, %.entry ] 317 call void @llvm.amdgcn.exp.f32(i32 immarg 0, i32 immarg 15, float %tmp36, float %tmp36, float %tmp36, float %tmp36, i1 immarg true, i1 immarg true) #3 318 ret void 319} 320 321declare void @llvm.amdgcn.kill(i1) #0 322declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0 323declare void @llvm.amdgcn.s.sendmsg(i32, i32) #0 324declare i1 @llvm.amdgcn.wqm.vote(i1) 325 326attributes #0 = { nounwind } 327