1; RUN: not llc < %s -march=amdgcn -mcpu=bonaire -verify-machineinstrs | FileCheck --check-prefix=GCN %s 2; RUN: not llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=VI %s 3 4; RUN: not llc < %s -march=amdgcn -mcpu=bonaire -verify-machineinstrs 2>&1 | FileCheck --check-prefix=NOGCN --check-prefix=NOSI %s 5; RUN: not llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs 2>&1 | FileCheck --check-prefix=NOGCN %s 6 7; GCN-LABEL: {{^}}inline_reg_constraints: 8; GCN: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}] 9; GCN: flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] 10; GCN: flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] 11; GCN: flat_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] 12; GCN: flat_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] 13; GCN: s_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}] 14; GCN: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] 15; GCN: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] 16; GCN: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] 17; GCN: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] 18; GCN: s_load_dwordx8 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] 19 20define amdgpu_kernel void @inline_reg_constraints(i32 addrspace(1)* %ptr) { 21entry: 22 %v32 = tail call i32 asm sideeffect "flat_load_dword $0, $1", "=v,v"(i32 addrspace(1)* %ptr) 23 %v2_32 = tail call <2 x i32> asm sideeffect "flat_load_dwordx2 $0, $1", "=v,v"(i32 addrspace(1)* %ptr) 24 %v64 = tail call i64 asm sideeffect "flat_load_dwordx2 $0, $1", "=v,v"(i32 addrspace(1)* %ptr) 25 %v4_32 = tail call <4 x i32> asm sideeffect "flat_load_dwordx4 $0, $1", "=v,v"(i32 addrspace(1)* %ptr) 26 %v128 = tail call i128 asm sideeffect "flat_load_dwordx4 $0, $1", "=v,v"(i32 addrspace(1)* %ptr) 27 %s32 = tail call i32 asm sideeffect "s_load_dword $0, $1", "=s,s"(i32 addrspace(1)* %ptr) 28 %s32_2 = tail call <2 x i32> asm sideeffect "s_load_dwordx2 $0, $1", "=s,s"(i32 addrspace(1)* %ptr) 29 %s64 = tail call i64 asm sideeffect "s_load_dwordx2 $0, $1", "=s,s"(i32 addrspace(1)* %ptr) 30 %s4_32 = tail call <4 x i32> asm sideeffect "s_load_dwordx4 $0, $1", "=s,s"(i32 addrspace(1)* %ptr) 31 %s128 = tail call i128 asm sideeffect "s_load_dwordx4 $0, $1", "=s,s"(i32 addrspace(1)* %ptr) 32 %s256 = tail call <8 x i32> asm sideeffect "s_load_dwordx8 $0, $1", "=s,s"(i32 addrspace(1)* %ptr) 33 ret void 34} 35 36; GCN-LABEL: {{^}}inline_sreg_constraint_m0: 37; GCN: s_mov_b32 m0, -1 38; GCN-NOT: m0 39; GCN: ; use m0 40define amdgpu_kernel void @inline_sreg_constraint_m0() { 41 %m0 = tail call i32 asm sideeffect "s_mov_b32 m0, -1", "={m0}"() 42 tail call void asm sideeffect "; use $0", "s"(i32 %m0) 43 ret void 44} 45 46; GCN-LABEL: {{^}}inline_sreg_constraint_imm_i32: 47; GCN: s_mov_b32 [[REG:s[0-9]+]], 32 48; GCN: ; use [[REG]] 49define amdgpu_kernel void @inline_sreg_constraint_imm_i32() { 50 tail call void asm sideeffect "; use $0", "s"(i32 32) 51 ret void 52} 53 54; GCN-LABEL: {{^}}inline_sreg_constraint_imm_f32: 55; GCN: s_mov_b32 [[REG:s[0-9]+]], 1.0 56; GCN: ; use [[REG]] 57define amdgpu_kernel void @inline_sreg_constraint_imm_f32() { 58 tail call void asm sideeffect "; use $0", "s"(float 1.0) 59 ret void 60} 61 62; FIXME: Should be able to use s_mov_b64 63; GCN-LABEL: {{^}}inline_sreg_constraint_imm_i64: 64; GCN-DAG: s_mov_b32 s[[REG_LO:[0-9]+]], -4{{$}} 65; GCN-DAG: s_mov_b32 s[[REG_HI:[0-9]+]], -1{{$}} 66; GCN: ; use s{{\[}}[[REG_LO]]:[[REG_HI]]{{\]}} 67define amdgpu_kernel void @inline_sreg_constraint_imm_i64() { 68 tail call void asm sideeffect "; use $0", "s"(i64 -4) 69 ret void 70} 71 72; GCN-LABEL: {{^}}inline_sreg_constraint_imm_f64: 73; GCN-DAG: s_mov_b32 s[[REG_LO:[0-9]+]], 0{{$}} 74; GCN-DAG: s_mov_b32 s[[REG_HI:[0-9]+]], 0x3ff00000{{$}} 75; GCN: ; use s{{\[}}[[REG_LO]]:[[REG_HI]]{{\]}} 76define amdgpu_kernel void @inline_sreg_constraint_imm_f64() { 77 tail call void asm sideeffect "; use $0", "s"(double 1.0) 78 ret void 79} 80 81;============================================================================== 82; 'A' constraint, 16-bit operand 83;============================================================================== 84 85; NOSI: error: invalid operand for inline asm constraint 'A' 86; VI-LABEL: {{^}}inline_A_constraint_H0: 87; VI: v_mov_b32 {{v[0-9]+}}, 64 88define i32 @inline_A_constraint_H0() { 89 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i16 64) 90 ret i32 %v0 91} 92 93; NOSI: error: invalid operand for inline asm constraint 'A' 94; VI-LABEL: {{^}}inline_A_constraint_H1: 95; VI: v_mov_b32 {{v[0-9]+}}, -16 96define i32 @inline_A_constraint_H1() { 97 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i16 -16) 98 ret i32 %v0 99} 100 101; NOSI: error: invalid operand for inline asm constraint 'A' 102; VI-LABEL: {{^}}inline_A_constraint_H2: 103; VI: v_mov_b32 {{v[0-9]+}}, 0x3c00 104define i32 @inline_A_constraint_H2() { 105 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i16 bitcast (half 1.0 to i16)) 106 ret i32 %v0 107} 108 109; NOSI: error: invalid operand for inline asm constraint 'A' 110; VI-LABEL: {{^}}inline_A_constraint_H3: 111; VI: v_mov_b32 {{v[0-9]+}}, 0xbc00 112define i32 @inline_A_constraint_H3() { 113 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i16 bitcast (half -1.0 to i16)) 114 ret i32 %v0 115} 116 117; NOSI: error: invalid operand for inline asm constraint 'A' 118; VI-LABEL: {{^}}inline_A_constraint_H4: 119; VI: v_mov_b32 {{v[0-9]+}}, 0x3118 120define i32 @inline_A_constraint_H4() { 121 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(half 0xH3118) 122 ret i32 %v0 123} 124 125; NOSI: error: invalid operand for inline asm constraint 'A' 126; VI-LABEL: {{^}}inline_A_constraint_H5: 127; VI: v_mov_b32 {{v[0-9]+}}, 0x3118 128define i32 @inline_A_constraint_H5() { 129 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i16 bitcast (half 0xH3118 to i16)) 130 ret i32 %v0 131} 132 133; NOSI: error: invalid operand for inline asm constraint 'A' 134; VI-LABEL: {{^}}inline_A_constraint_H6: 135; VI: v_mov_b32 {{v[0-9]+}}, 0xb800 136define i32 @inline_A_constraint_H6() { 137 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(half -0.5) 138 ret i32 %v0 139} 140 141; NOGCN: error: invalid operand for inline asm constraint 'A' 142define i32 @inline_A_constraint_H7() { 143 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i16 bitcast (half 0xH3119 to i16)) 144 ret i32 %v0 145} 146 147; NOGCN: error: invalid operand for inline asm constraint 'A' 148define i32 @inline_A_constraint_H8() { 149 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i16 bitcast (half 0xH3117 to i16)) 150 ret i32 %v0 151} 152 153; NOGCN: error: invalid operand for inline asm constraint 'A' 154define i32 @inline_A_constraint_H9() { 155 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i16 65) 156 ret i32 %v0 157} 158 159;============================================================================== 160; 'A' constraint, 32-bit operand 161;============================================================================== 162 163; GCN-LABEL: {{^}}inline_A_constraint_F0: 164; GCN: v_mov_b32 {{v[0-9]+}}, -16 165define i32 @inline_A_constraint_F0() { 166 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i32 -16) 167 ret i32 %v0 168} 169 170; GCN-LABEL: {{^}}inline_A_constraint_F1: 171; GCN: v_mov_b32 {{v[0-9]+}}, 1 172define i32 @inline_A_constraint_F1() { 173 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i32 1) 174 ret i32 %v0 175} 176 177; GCN-LABEL: {{^}}inline_A_constraint_F2: 178; GCN: v_mov_b32 {{v[0-9]+}}, 0xbf000000 179define i32 @inline_A_constraint_F2() { 180 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i32 bitcast (float -0.5 to i32)) 181 ret i32 %v0 182} 183 184; GCN-LABEL: {{^}}inline_A_constraint_F3: 185; GCN: v_mov_b32 {{v[0-9]+}}, 0x40000000 186define i32 @inline_A_constraint_F3() { 187 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i32 bitcast (float 2.0 to i32)) 188 ret i32 %v0 189} 190 191; GCN-LABEL: {{^}}inline_A_constraint_F4: 192; GCN: v_mov_b32 {{v[0-9]+}}, 0xc0800000 193define i32 @inline_A_constraint_F4() { 194 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(float -4.0) 195 ret i32 %v0 196} 197 198; NOSI: error: invalid operand for inline asm constraint 'A' 199; VI-LABEL: {{^}}inline_A_constraint_F5: 200; VI: v_mov_b32 {{v[0-9]+}}, 0x3e22f983 201define i32 @inline_A_constraint_F5() { 202 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i32 1042479491) 203 ret i32 %v0 204} 205 206; GCN-LABEL: {{^}}inline_A_constraint_F6: 207; GCN: v_mov_b32 {{v[0-9]+}}, 0x3f000000 208define i32 @inline_A_constraint_F6() { 209 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(float 0.5) 210 ret i32 %v0 211} 212 213; NOGCN: error: invalid operand for inline asm constraint 'A' 214define i32 @inline_A_constraint_F7() { 215 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i32 1042479490) 216 ret i32 %v0 217} 218 219; NOGCN: error: invalid operand for inline asm constraint 'A' 220define i32 @inline_A_constraint_F8() { 221 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i32 -17) 222 ret i32 %v0 223} 224 225;============================================================================== 226; 'A' constraint, 64-bit operand 227;============================================================================== 228 229; GCN-LABEL: {{^}}inline_A_constraint_D0: 230; GCN: v_mov_b32 {{v[0-9]+}}, -16 231define i32 @inline_A_constraint_D0() { 232 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i64 -16) 233 ret i32 %v0 234} 235 236; GCN-LABEL: {{^}}inline_A_constraint_D1: 237; GCN: v_cvt_f32_f64 {{v[0-9]+}}, 0xc000000000000000 238define i32 @inline_A_constraint_D1() { 239 %v0 = tail call i32 asm "v_cvt_f32_f64 $0, $1", "=v,A"(i64 bitcast (double -2.0 to i64)) 240 ret i32 %v0 241} 242 243; GCN-LABEL: {{^}}inline_A_constraint_D2: 244; GCN: v_cvt_f32_f64 {{v[0-9]+}}, 0x3fe0000000000000 245define i32 @inline_A_constraint_D2() { 246 %v0 = tail call i32 asm "v_cvt_f32_f64 $0, $1", "=v,A"(double 0.5) 247 ret i32 %v0 248} 249 250; NOSI: error: invalid operand for inline asm constraint 'A' 251; VI-LABEL: {{^}}inline_A_constraint_D3: 252; VI: v_cvt_f32_f64 {{v[0-9]+}}, 0x3fc45f306dc9c882 253define i32 @inline_A_constraint_D3() { 254 %v0 = tail call i32 asm "v_cvt_f32_f64 $0, $1", "=v,A"(double 0.15915494309189532) 255 ret i32 %v0 256} 257 258; NOSI: error: invalid operand for inline asm constraint 'A' 259; VI-LABEL: {{^}}inline_A_constraint_D4: 260; VI: v_cvt_f32_f64 {{v[0-9]+}}, 0x3fc45f306dc9c882 261define i32 @inline_A_constraint_D4() { 262 %v0 = tail call i32 asm "v_cvt_f32_f64 $0, $1", "=v,A"(i64 bitcast (double 0.15915494309189532 to i64)) 263 ret i32 %v0 264} 265 266; GCN-LABEL: {{^}}inline_A_constraint_D5: 267; GCN: v_cvt_f32_f64 {{v[0-9]+}}, 0xc000000000000000 268define i32 @inline_A_constraint_D5() { 269 %v0 = tail call i32 asm "v_cvt_f32_f64 $0, $1", "=v,A"(double -2.0) 270 ret i32 %v0 271} 272 273; NOGCN: error: invalid operand for inline asm constraint 'A' 274define i32 @inline_A_constraint_D8() { 275 %v0 = tail call i32 asm "v_cvt_f32_f64 $0, $1", "=v,A"(double 1.1) 276 ret i32 %v0 277} 278 279; NOGCN: error: invalid operand for inline asm constraint 'A' 280define i32 @inline_A_constraint_D9() { 281 %v0 = tail call i32 asm "v_cvt_f32_f64 $0, $1", "=v,A"(i64 bitcast (double 0.1 to i64)) 282 ret i32 %v0 283} 284 285;============================================================================== 286; 'A' constraint, v2x16 operand 287;============================================================================== 288 289; NOSI: error: invalid operand for inline asm constraint 'A' 290; VI-LABEL: {{^}}inline_A_constraint_V0: 291; VI: v_mov_b32 {{v[0-9]+}}, -4 292define i32 @inline_A_constraint_V0() { 293 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(<2 x i16> <i16 -4, i16 -4>) 294 ret i32 %v0 295} 296 297; NOSI: error: invalid operand for inline asm constraint 'A' 298; VI-LABEL: {{^}}inline_A_constraint_V1: 299; VI: v_mov_b32 {{v[0-9]+}}, 0xb800 300define i32 @inline_A_constraint_V1() { 301 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(<2 x half> <half -0.5, half -0.5>) 302 ret i32 %v0 303} 304 305; NOGCN: error: invalid operand for inline asm constraint 'A' 306define i32 @inline_A_constraint_V2() { 307 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(<2 x i16> <i16 -4, i16 undef>) 308 ret i32 %v0 309} 310 311; NOGCN: error: invalid operand for inline asm constraint 'A' 312define i32 @inline_A_constraint_V3() { 313 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(<2 x half> <half undef, half -0.5>) 314 ret i32 %v0 315} 316 317; NOGCN: error: invalid operand for inline asm constraint 'A' 318define i32 @inline_A_constraint_V4() { 319 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(<2 x i16> <i16 1, i16 2>) 320 ret i32 %v0 321} 322 323; NOGCN: error: invalid operand for inline asm constraint 'A' 324define i32 @inline_A_constraint_V5() { 325 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(<4 x i16> <i16 0, i16 0, i16 0, i16 0>) 326 ret i32 %v0 327} 328 329; NOGCN: error: invalid operand for inline asm constraint 'A' 330define i32 @inline_A_constraint_V6() { 331 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(<2 x i32> <i32 0, i32 0>) 332 ret i32 %v0 333} 334 335;============================================================================== 336; 'A' constraint, type errors 337;============================================================================== 338 339; NOGCN: error: invalid operand for inline asm constraint 'A' 340define i32 @inline_A_constraint_E1(i32 %x) { 341 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i32 %x) 342 ret i32 %v0 343} 344 345; NOGCN: error: invalid operand for inline asm constraint 'A' 346define i32 @inline_A_constraint_E2() { 347 %v0 = tail call i32 asm "v_mov_b32 $0, $1", "=v,A"(i128 100000000000000000000) 348 ret i32 %v0 349} 350