1; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3 | FileCheck --check-prefix=HSA %s
2; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3,-flat-for-global | FileCheck --check-prefix=HSA-CI %s
3; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=-code-object-v3 | FileCheck --check-prefix=HSA %s
4; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=-code-object-v3,-flat-for-global | FileCheck --check-prefix=HSA-VI %s
5; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj -mattr=-code-object-v3 | llvm-readobj -symbols -s -sd | FileCheck --check-prefix=ELF %s
6; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3 | llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3 | llvm-readobj -symbols -s -sd | FileCheck %s --check-prefix=ELF
7; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+WavefrontSize32,-WavefrontSize64,-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=GFX10 --check-prefix=GFX10-W32 %s
8; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=-WavefrontSize32,+WavefrontSize64,-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=GFX10 --check-prefix=GFX10-W64 %s
9
10; The SHT_NOTE section contains the output from the .hsa_code_object_*
11; directives.
12
13; ELF: Section {
14; ELF: Name: .text
15; ELF: Type: SHT_PROGBITS (0x1)
16; ELF: Flags [ (0x6)
17; ELF: SHF_ALLOC (0x2)
18; ELF: SHF_EXECINSTR (0x4)
19; ELF: }
20
21; ELF: SHT_NOTE
22; ELF: Flags [ (0x0)
23; ELF: ]
24; ELF: SectionData (
25; ELF: 0000: 04000000 08000000 01000000 414D4400
26; ELF: 0010: 02000000 01000000 04000000 1B000000
27; ELF: 0020: 03000000 414D4400 04000700 07000000
28; ELF: 0030: 00000000 00000000 414D4400 414D4447
29; ELF: 0040: 50550000
30; ELF: )
31
32; ELF: Symbol {
33; ELF: Name: simple
34; ELF: Size: 288
35; ELF: Type: AMDGPU_HSA_KERNEL (0xA)
36; ELF: }
37
38; HSA-NOT: .AMDGPU.config
39; HSA: .text
40; HSA: .hsa_code_object_version 2,1
41; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
42; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU"
43
44; HSA-LABEL: .amdgpu_hsa_kernel simple
45; HSA: {{^}}simple:
46; HSA: .amd_kernel_code_t
47; HSA: enable_sgpr_private_segment_buffer = 1
48; HSA: enable_sgpr_kernarg_segment_ptr = 1
49
50; PRE-GFX10: enable_wavefront_size32 = 0
51; GFX10-W32: enable_wavefront_size32 = 1
52; GFX10-W64: enable_wavefront_size32 = 0
53
54; PRE-GFX10: wavefront_size = 6
55; GFX10-W32: wavefront_size = 5
56; GFX10-W64: wavefront_size = 6
57
58; HSA: call_convention = -1
59; HSA: .end_amd_kernel_code_t
60; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0
61
62; Make sure we are setting the ATC bit:
63; HSA-CI: s_mov_b32 s[[HI:[0-9]]], 0x100f000
64; On VI+ we also need to set MTYPE = 2
65; HSA-VI: s_mov_b32 s[[HI:[0-9]]], 0x1100f000
66; Make sure we generate flat store for HSA
67; PRE-GFX10: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}
68; GFX10: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}
69
70; HSA: .Lfunc_end0:
71; HSA: .size   simple, .Lfunc_end0-simple
72
73define amdgpu_kernel void @simple(i32 addrspace(1)* %out) {
74entry:
75  store i32 0, i32 addrspace(1)* %out
76  ret void
77}
78
79; HSA-LABEL: .amdgpu_hsa_kernel simple_no_kernargs
80; HSA: enable_sgpr_kernarg_segment_ptr = 0
81define amdgpu_kernel void @simple_no_kernargs() {
82entry:
83  store volatile i32 0, i32 addrspace(1)* undef
84  ret void
85}
86