1; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA %s
2; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -mattr=-flat-for-global | FileCheck --check-prefix=HSA-CI %s
3; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA %s
4; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 -mattr=-flat-for-global | FileCheck --check-prefix=HSA-VI %s
5; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj --amdhsa-code-object-version=2 | llvm-readobj -S --sd --syms - | FileCheck --check-prefix=ELF %s
6; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | llvm-readobj -S --sd --syms - | FileCheck %s --check-prefix=ELF
7; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W32 %s
8; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W64 %s
9; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W32 %s
10; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W64 %s
11
12; The SHT_NOTE section contains the output from the .hsa_code_object_*
13; directives.
14
15; ELF: Section {
16; ELF: Name: .text
17; ELF: Type: SHT_PROGBITS (0x1)
18; ELF: Flags [ (0x6)
19; ELF: SHF_ALLOC (0x2)
20; ELF: SHF_EXECINSTR (0x4)
21; ELF: }
22
23; ELF: SHT_NOTE
24; ELF: Flags [ (0x2)
25; ELF: SHF_ALLOC (0x2)
26; ELF: ]
27; ELF: SectionData (
28; ELF: 0000: 04000000 08000000 01000000 414D4400
29; ELF: 0010: 02000000 01000000 04000000 1B000000
30; ELF: 0020: 03000000 414D4400 04000700 07000000
31; ELF: 0030: 00000000 00000000 414D4400 414D4447
32; ELF: 0040: 50550000
33; ELF: )
34
35; ELF: Symbol {
36; ELF: Name: simple
37; ELF: Size: 288
38; ELF: Type: AMDGPU_HSA_KERNEL (0xA)
39; ELF: }
40
41; HSA-NOT: .AMDGPU.config
42; HSA: .text
43; HSA: .hsa_code_object_version 2,1
44; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
45; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU"
46
47; HSA-LABEL: .amdgpu_hsa_kernel simple
48; HSA: {{^}}simple:
49; HSA: .amd_kernel_code_t
50; HSA: enable_sgpr_private_segment_buffer = 1
51; HSA: enable_sgpr_kernarg_segment_ptr = 1
52
53; PRE-GFX10: enable_wavefront_size32 = 0
54; GFX10-W32: .amdhsa_wavefront_size32 1
55; GFX10-W64: .amdhsa_wavefront_size32 0
56
57; PRE-GFX10: wavefront_size = 6
58
59; HSA: call_convention = -1
60; HSA: .end_amd_kernel_code_t
61; HSA: s_load_{{dwordx2|b64}} s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0
62
63; Make sure we are setting the ATC bit:
64; HSA-CI: s_mov_b32 s[[HI:[0-9]]], 0x100f000
65; On VI+ we also need to set MTYPE = 2
66; HSA-VI: s_mov_b32 s[[HI:[0-9]]], 0x1100f000
67; Make sure we generate flat store for HSA
68; PRE-GFX10: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}
69; GFX10: global_store_{{dword|b32}} v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, off
70
71; HSA: .Lfunc_end0:
72; HSA: .size   simple, .Lfunc_end0-simple
73
74define amdgpu_kernel void @simple(i32 addrspace(1)* %out) {
75entry:
76  store i32 0, i32 addrspace(1)* %out
77  ret void
78}
79
80; HSA-LABEL: .amdgpu_hsa_kernel simple_no_kernargs
81; HSA: enable_sgpr_kernarg_segment_ptr = 0
82define amdgpu_kernel void @simple_no_kernargs() {
83entry:
84  store volatile i32 0, i32 addrspace(1)* undef
85  ret void
86}
87