1; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA %s 2; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -mattr=-flat-for-global | FileCheck --check-prefix=HSA-CI %s 3; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA %s 4; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 -mattr=-flat-for-global | FileCheck --check-prefix=HSA-VI %s 5; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj --amdhsa-code-object-version=2 | llvm-readobj -S --sd --syms - | FileCheck --check-prefix=ELF %s 6; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | llvm-readobj -S --sd --syms - | FileCheck %s --check-prefix=ELF 7; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W32 %s 8; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W64 %s 9 10; The SHT_NOTE section contains the output from the .hsa_code_object_* 11; directives. 12 13; ELF: Section { 14; ELF: Name: .text 15; ELF: Type: SHT_PROGBITS (0x1) 16; ELF: Flags [ (0x6) 17; ELF: SHF_ALLOC (0x2) 18; ELF: SHF_EXECINSTR (0x4) 19; ELF: } 20 21; ELF: SHT_NOTE 22; ELF: Flags [ (0x2) 23; ELF: SHF_ALLOC (0x2) 24; ELF: ] 25; ELF: SectionData ( 26; ELF: 0000: 04000000 08000000 01000000 414D4400 27; ELF: 0010: 02000000 01000000 04000000 1B000000 28; ELF: 0020: 03000000 414D4400 04000700 07000000 29; ELF: 0030: 00000000 00000000 414D4400 414D4447 30; ELF: 0040: 50550000 31; ELF: ) 32 33; ELF: Symbol { 34; ELF: Name: simple 35; ELF: Size: 288 36; ELF: Type: AMDGPU_HSA_KERNEL (0xA) 37; ELF: } 38 39; HSA-NOT: .AMDGPU.config 40; HSA: .text 41; HSA: .hsa_code_object_version 2,1 42; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU" 43; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU" 44 45; HSA-LABEL: .amdgpu_hsa_kernel simple 46; HSA: {{^}}simple: 47; HSA: .amd_kernel_code_t 48; HSA: enable_sgpr_private_segment_buffer = 1 49; HSA: enable_sgpr_kernarg_segment_ptr = 1 50 51; PRE-GFX10: enable_wavefront_size32 = 0 52; GFX10-W32: .amdhsa_wavefront_size32 1 53; GFX10-W64: .amdhsa_wavefront_size32 0 54 55; PRE-GFX10: wavefront_size = 6 56 57; HSA: call_convention = -1 58; HSA: .end_amd_kernel_code_t 59; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0 60 61; Make sure we are setting the ATC bit: 62; HSA-CI: s_mov_b32 s[[HI:[0-9]]], 0x100f000 63; On VI+ we also need to set MTYPE = 2 64; HSA-VI: s_mov_b32 s[[HI:[0-9]]], 0x1100f000 65; Make sure we generate flat store for HSA 66; PRE-GFX10: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} 67; GFX10: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, off 68 69; HSA: .Lfunc_end0: 70; HSA: .size simple, .Lfunc_end0-simple 71 72define amdgpu_kernel void @simple(i32 addrspace(1)* %out) { 73entry: 74 store i32 0, i32 addrspace(1)* %out 75 ret void 76} 77 78; HSA-LABEL: .amdgpu_hsa_kernel simple_no_kernargs 79; HSA: enable_sgpr_kernarg_segment_ptr = 0 80define amdgpu_kernel void @simple_no_kernargs() { 81entry: 82 store volatile i32 0, i32 addrspace(1)* undef 83 ret void 84} 85