1; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
3; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -enable-var-scope -check-prefix=R600 -check-prefix=FUNC %s
4
5; FUNC-LABEL: {{^}}s_fneg_f32:
6; R600: -PV
7
8; GCN: s_load_dword [[VAL:s[0-9]+]]
9; GCN: s_xor_b32 [[NEG_VAL:s[0-9]+]], [[VAL]], 0x80000000
10; GCN: v_mov_b32_e32 v{{[0-9]+}}, [[NEG_VAL]]
11define amdgpu_kernel void @s_fneg_f32(float addrspace(1)* %out, float %in) {
12  %fneg = fsub float -0.000000e+00, %in
13  store float %fneg, float addrspace(1)* %out
14  ret void
15}
16
17; FUNC-LABEL: {{^}}s_fneg_v2f32:
18; R600: -PV
19; R600: -PV
20
21; GCN: s_xor_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x80000000
22; GCN: s_xor_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x80000000
23define amdgpu_kernel void @s_fneg_v2f32(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) {
24  %fneg = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in
25  store <2 x float> %fneg, <2 x float> addrspace(1)* %out
26  ret void
27}
28
29; FUNC-LABEL: {{^}}s_fneg_v4f32:
30; R600: -PV
31; R600: -T
32; R600: -PV
33; R600: -PV
34
35; GCN: s_xor_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x80000000
36; GCN: s_xor_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x80000000
37; GCN: s_xor_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x80000000
38; GCN: s_xor_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x80000000
39define amdgpu_kernel void @s_fneg_v4f32(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) {
40  %fneg = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in
41  store <4 x float> %fneg, <4 x float> addrspace(1)* %out
42  ret void
43}
44
45; DAGCombiner will transform:
46; (fneg (f32 bitcast (i32 a))) => (f32 bitcast (xor (i32 a), 0x80000000))
47; unless the target returns true for isNegFree()
48
49; FUNC-LABEL: {{^}}fsub0_f32:
50
51; GCN: v_sub_f32_e64 v{{[0-9]}}, 0, s{{[0-9]+$}}
52
53; R600-NOT: XOR
54; R600: -KC0[2].Z
55define amdgpu_kernel void @fsub0_f32(float addrspace(1)* %out, i32 %in) {
56  %bc = bitcast i32 %in to float
57  %fsub = fsub float 0.0, %bc
58  store float %fsub, float addrspace(1)* %out
59  ret void
60}
61; FUNC-LABEL: {{^}}fneg_free_f32:
62; SI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
63; VI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
64
65; GCN: s_xor_b32 [[RES:s[0-9]+]], [[NEG_VALUE]], 0x80000000
66; GCN: v_mov_b32_e32 [[V_RES:v[0-9]+]], [[RES]]
67; GCN: buffer_store_dword [[V_RES]]
68
69; R600-NOT: XOR
70; R600: -PV.W
71define amdgpu_kernel void @fneg_free_f32(float addrspace(1)* %out, i32 %in) {
72  %bc = bitcast i32 %in to float
73  %fsub = fsub float -0.0, %bc
74  store float %fsub, float addrspace(1)* %out
75  ret void
76}
77
78; FUNC-LABEL: {{^}}fneg_fold_f32:
79; SI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
80; VI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
81; GCN-NOT: xor
82; GCN: v_mul_f32_e64 v{{[0-9]+}}, -[[NEG_VALUE]], [[NEG_VALUE]]
83define amdgpu_kernel void @fneg_fold_f32(float addrspace(1)* %out, float %in) {
84  %fsub = fsub float -0.0, %in
85  %fmul = fmul float %fsub, %in
86  store float %fmul, float addrspace(1)* %out
87  ret void
88}
89
90; Make sure we turn some integer operations back into fabs
91; FUNC-LABEL: {{^}}bitpreserve_fneg_f32:
92; GCN: v_mul_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, -4.0
93define amdgpu_kernel void @bitpreserve_fneg_f32(float addrspace(1)* %out, float %in) {
94  %in.bc = bitcast float %in to i32
95  %int.abs = xor i32 %in.bc, 2147483648
96  %bc = bitcast i32 %int.abs to float
97  %fadd = fmul float %bc, 4.0
98  store float %fadd, float addrspace(1)* %out
99  ret void
100}
101