1; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s
2; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
3
4; CHECK-LABEL: {{^}}else_no_execfix:
5; CHECK: ; %Flow
6; CHECK-NEXT: s_or_saveexec_b64 [[DST:s\[[0-9]+:[0-9]+\]]],
7; CHECK-NEXT: s_xor_b64 exec, exec, [[DST]]
8; CHECK-NEXT: ; mask branch
9define amdgpu_ps float @else_no_execfix(i32 %z, float %v) {
10main_body:
11  %cc = icmp sgt i32 %z, 5
12  br i1 %cc, label %if, label %else
13
14if:
15  %v.if = fmul float %v, 2.0
16  br label %end
17
18else:
19  %v.else = fmul float %v, 3.0
20  br label %end
21
22end:
23  %r = phi float [ %v.if, %if ], [ %v.else, %else ]
24  ret float %r
25}
26
27; CHECK-LABEL: {{^}}else_execfix_leave_wqm:
28; CHECK: ; BB#0:
29; CHECK-NEXT: s_mov_b64 [[INIT_EXEC:s\[[0-9]+:[0-9]+\]]], exec
30; CHECK: ; %Flow
31; CHECK-NEXT: s_or_saveexec_b64 [[DST:s\[[0-9]+:[0-9]+\]]],
32; CHECK-NEXT: s_and_b64 exec, exec, [[INIT_EXEC]]
33; CHECK-NEXT: s_and_b64 [[AND_INIT:s\[[0-9]+:[0-9]+\]]], exec, [[DST]]
34; CHECK-NEXT: s_xor_b64 exec, exec, [[AND_INIT]]
35; CHECK-NEXT: ; mask branch
36define amdgpu_ps void @else_execfix_leave_wqm(i32 %z, float %v) {
37main_body:
38  %cc = icmp sgt i32 %z, 5
39  br i1 %cc, label %if, label %else
40
41if:
42  %v.if = fmul float %v, 2.0
43  br label %end
44
45else:
46  %c = fmul float %v, 3.0
47  %c.i = bitcast float %c to i32
48  %tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %c.i, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
49  %v.else = extractelement <4 x float> %tex, i32 0
50  br label %end
51
52end:
53  %r = phi float [ %v.if, %if ], [ %v.else, %else ]
54  call void @llvm.amdgcn.buffer.store.f32(float %r, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0)
55  ret void
56}
57
58declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) nounwind
59
60declare <4 x float> @llvm.SI.image.sample.i32(i32, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) nounwind readnone
61