1; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN
2; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN
3; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN
4
5; GCN-LABEL: {{^}}dpp_add:
6; GCN: global_load_{{dword|b32}} [[V:v[0-9]+]],
7; GCN: v_add_{{(nc_)?}}u32_dpp [[V]], [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
8define amdgpu_kernel void @dpp_add(i32 addrspace(1)* %arg) {
9  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
10  %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id
11  %load = load i32, i32 addrspace(1)* %gep
12  %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %load, i32 %load, i32 1, i32 15, i32 15, i1 1) #0
13  %add = add i32 %tmp0, %load
14  store i32 %add, i32 addrspace(1)* %gep
15  ret void
16}
17
18; GCN-LABEL: {{^}}dpp_ceil:
19; GCN: global_load_{{dword|b32}} [[V:v[0-9]+]],
20; GCN: v_ceil_f32_dpp [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
21define amdgpu_kernel void @dpp_ceil(i32 addrspace(1)* %arg) {
22  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
23  %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id
24  %load = load i32, i32 addrspace(1)* %gep
25  %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %load, i32 %load, i32 1, i32 15, i32 15, i1 1) #0
26  %tmp1 = bitcast i32 %tmp0 to float
27  %round = tail call float @llvm.ceil.f32(float %tmp1)
28  %tmp2 = bitcast float %round to i32
29  store i32 %tmp2, i32 addrspace(1)* %gep
30  ret void
31}
32
33; GCN-LABEL: {{^}}dpp_fadd:
34; GCN: global_load_{{dword|b32}} [[V:v[0-9]+]],
35; GCN: v_add_f32_dpp [[V]], [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
36define amdgpu_kernel void @dpp_fadd(i32 addrspace(1)* %arg) {
37  %id = tail call i32 @llvm.amdgcn.workitem.id.x()
38  %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id
39  %load = load i32, i32 addrspace(1)* %gep
40  %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %load, i32 %load, i32 1, i32 15, i32 15, i1 1) #0
41  %tmp1 = bitcast i32 %tmp0 to float
42  %t = bitcast i32 %load to float
43  %add = fadd float %tmp1, %t
44  %tmp2 = bitcast float %add to i32
45  store i32 %tmp2, i32 addrspace(1)* %gep
46  ret void
47}
48
49
50declare i32 @llvm.amdgcn.workitem.id.x()
51declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1) #0
52declare float @llvm.ceil.f32(float)
53
54attributes #0 = { nounwind readnone convergent }
55