1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=machine-scheduler -verify-machineinstrs %s -o - | FileCheck %s
3--- |
4
5  declare void @llvm.dbg.value(metadata, metadata, metadata) #0
6
7  define amdgpu_kernel void @could_not_use_debug_inst_to_query_mi2mimap() #1 {
8    ret void
9  }
10
11  declare hidden float @foo(float, float, float) local_unnamed_addr #1
12
13  attributes #0 = { nounwind readnone speculatable }
14  attributes #1 = {nounwind }
15
16...
17---
18name:            could_not_use_debug_inst_to_query_mi2mimap
19tracksRegLiveness: true
20frameInfo:
21  hasCalls:        true
22body:             |
23  ; CHECK-LABEL: name: could_not_use_debug_inst_to_query_mi2mimap
24  ; CHECK: bb.0:
25  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
26  ; CHECK-NEXT: {{  $}}
27  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
28  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
29  ; CHECK-NEXT:   [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
30  ; CHECK-NEXT:   [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
31  ; CHECK-NEXT:   [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
32  ; CHECK-NEXT:   [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
33  ; CHECK-NEXT:   [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
34  ; CHECK-NEXT:   [[DEF7:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
35  ; CHECK-NEXT:   %9:vgpr_32 = nofpexcept V_MUL_F32_e32 1082130432, [[DEF]], implicit $mode, implicit $exec
36  ; CHECK-NEXT:   [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
37  ; CHECK-NEXT:   [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
38  ; CHECK-NEXT: {{  $}}
39  ; CHECK-NEXT: bb.1:
40  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
41  ; CHECK-NEXT: {{  $}}
42  ; CHECK-NEXT:   DBG_VALUE
43  ; CHECK-NEXT:   DBG_VALUE
44  ; CHECK-NEXT:   DBG_VALUE
45  ; CHECK-NEXT: {{  $}}
46  ; CHECK-NEXT: bb.2:
47  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
48  ; CHECK-NEXT: {{  $}}
49  ; CHECK-NEXT:   S_BRANCH %bb.3
50  ; CHECK-NEXT: {{  $}}
51  ; CHECK-NEXT: bb.3:
52  ; CHECK-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
53  ; CHECK-NEXT:   [[DEF10:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
54  ; CHECK-NEXT:   [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
55  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_MOV_B32_e32_]]
56  ; CHECK-NEXT:   %16:vgpr_32 = nofpexcept V_MUL_F32_e32 [[DEF6]], [[DEF6]], implicit $mode, implicit $exec
57  ; CHECK-NEXT:   %17:vgpr_32 = nofpexcept V_MUL_F32_e32 [[DEF6]], [[DEF6]], implicit $mode, implicit $exec
58  ; CHECK-NEXT:   %18:vgpr_32 = nofpexcept V_MUL_F32_e32 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_]], implicit $mode, implicit $exec
59  ; CHECK-NEXT:   [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
60  ; CHECK-NEXT:   [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
61  ; CHECK-NEXT:   %21:vgpr_32 = nofpexcept V_ADD_F32_e32 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_]], implicit $mode, implicit $exec
62  ; CHECK-NEXT:   %22:vgpr_32 = nofpexcept V_MUL_F32_e32 [[DEF6]], [[DEF6]], implicit $mode, implicit $exec
63  ; CHECK-NEXT:   dead %23:vgpr_32 = nofpexcept V_MUL_F32_e32 %22, [[DEF12]], implicit $mode, implicit $exec
64  ; CHECK-NEXT:   dead [[V_MOV_B32_e32_1]]:vgpr_32 = nofpexcept V_MAC_F32_e32 %21, [[COPY]], [[V_MOV_B32_e32_1]], implicit $mode, implicit $exec
65  ; CHECK-NEXT:   [[DEF13:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
66  ; CHECK-NEXT:   $sgpr4 = IMPLICIT_DEF
67  ; CHECK-NEXT:   $vgpr0 = COPY [[DEF10]]
68  ; CHECK-NEXT:   $vgpr0 = COPY [[V_MOV_B32_e32_]]
69  ; CHECK-NEXT:   $vgpr1 = COPY [[DEF6]]
70  ; CHECK-NEXT:   $vgpr0 = COPY %16
71  ; CHECK-NEXT:   $vgpr1 = COPY %17
72  ; CHECK-NEXT:   $vgpr2 = COPY %18
73  ; CHECK-NEXT:   dead $sgpr30_sgpr31 = SI_CALL [[DEF13]], @foo, csr_amdgpu, implicit undef $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $sgpr4, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit-def $vgpr0
74  ; CHECK-NEXT:   %25:vgpr_32 = nofpexcept V_ADD_F32_e32 %9, [[DEF7]], implicit $mode, implicit $exec
75  ; CHECK-NEXT:   %25:vgpr_32 = nofpexcept V_MAC_F32_e32 [[DEF11]], [[DEF8]], %25, implicit $mode, implicit $exec
76  ; CHECK-NEXT:   dead %26:vgpr_32 = nofpexcept V_MAD_F32_e64 0, %25, 0, [[DEF3]], 0, [[DEF]], 0, 0, implicit $mode, implicit $exec
77  ; CHECK-NEXT:   dead %27:vgpr_32 = nofpexcept V_MAD_F32_e64 0, %25, 0, [[DEF4]], 0, [[DEF1]], 0, 0, implicit $mode, implicit $exec
78  ; CHECK-NEXT:   dead %28:vgpr_32 = nofpexcept V_MAD_F32_e64 0, %25, 0, [[DEF5]], 0, [[DEF2]], 0, 0, implicit $mode, implicit $exec
79  ; CHECK-NEXT:   [[DEF14:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
80  ; CHECK-NEXT:   GLOBAL_STORE_DWORD [[DEF14]], [[DEF9]], 0, 0, implicit $exec
81  ; CHECK-NEXT:   S_ENDPGM 0
82  bb.0:
83    successors: %bb.1
84
85    %0:vreg_64 = IMPLICIT_DEF
86    %1:vgpr_32 = IMPLICIT_DEF
87    %2:vgpr_32 = IMPLICIT_DEF
88    %3:vgpr_32 = IMPLICIT_DEF
89    %4:vgpr_32 = IMPLICIT_DEF
90    %5:vgpr_32 = IMPLICIT_DEF
91    %6:vgpr_32 = IMPLICIT_DEF
92    %7:vgpr_32 = IMPLICIT_DEF
93    %8:vgpr_32 = IMPLICIT_DEF
94    %9:vgpr_32 = nofpexcept V_MUL_F32_e32 1082130432, %1, implicit $mode, implicit $exec
95    %10:vgpr_32 = IMPLICIT_DEF
96    %11:vgpr_32 = IMPLICIT_DEF
97
98  bb.1:
99    successors: %bb.2
100
101    DBG_VALUE
102    DBG_VALUE
103    DBG_VALUE
104
105  bb.2:
106    successors: %bb.3
107
108    S_BRANCH %bb.3
109
110  bb.3:
111    %12:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
112    %13:vgpr_32 = COPY %12
113    %14:vgpr_32 = IMPLICIT_DEF
114    %15:vgpr_32 = IMPLICIT_DEF
115    %16:vgpr_32 = nofpexcept V_MUL_F32_e32 %7, %7, implicit $mode, implicit $exec
116    %17:vgpr_32 = nofpexcept V_MUL_F32_e32 %7, %7, implicit $mode, implicit $exec
117    %18:vgpr_32 = nofpexcept V_MUL_F32_e32 %12, %12, implicit $mode, implicit $exec
118    %19:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
119    %20:vgpr_32 = IMPLICIT_DEF
120    %21:vgpr_32 = nofpexcept V_ADD_F32_e32 %12, %12, implicit $mode, implicit $exec
121    %22:vgpr_32 = nofpexcept V_MUL_F32_e32 %7, %7, implicit $mode, implicit $exec
122    %23:vgpr_32 = nofpexcept V_MUL_F32_e32 %22, %20, implicit $mode, implicit $exec
123    %19:vgpr_32 = nofpexcept V_MAC_F32_e32 %21, %13, %19, implicit $mode, implicit $exec
124    %24:sreg_64 = IMPLICIT_DEF
125    $vgpr0 = COPY %14
126    $vgpr0 = COPY %12
127    $vgpr1 = COPY %7
128    $vgpr0 = COPY %16
129    $vgpr1 = COPY %17
130    $vgpr2 = COPY %18
131    $sgpr4 = IMPLICIT_DEF
132    dead $sgpr30_sgpr31 = SI_CALL %24, @foo, csr_amdgpu, implicit undef $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $sgpr4, implicit killed $vgpr0, implicit killed $vgpr1, implicit killed $vgpr2, implicit-def $vgpr0
133    %25:vgpr_32 = nofpexcept V_ADD_F32_e32 %9, %8, implicit $mode, implicit $exec
134    %25:vgpr_32 = nofpexcept V_MAC_F32_e32 %15, %10, %25, implicit $mode, implicit $exec
135    %26:vgpr_32 = nofpexcept V_MAD_F32_e64 0, %25, 0, %4, 0, %1, 0, 0, implicit $mode, implicit $exec
136    %27:vgpr_32 = nofpexcept V_MAD_F32_e64 0, %25, 0, %5, 0, %2, 0, 0, implicit $mode, implicit $exec
137    %28:vgpr_32 = nofpexcept V_MAD_F32_e64 0, %25, 0, %6, 0, %3, 0, 0, implicit $mode, implicit $exec
138    GLOBAL_STORE_DWORD %0, %11, 0, 0, implicit $exec
139    S_ENDPGM 0
140
141...
142