1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -march=amdgcn -mcpu=gfx1010 -amdgpu-atomic-optimizations < %s | FileCheck %s -check-prefixes=GFX10
3
4declare void @llvm.amdgcn.exp.f32(i32 immarg, i32 immarg, float, float, float, float, i1 immarg, i1 immarg)
5declare i32 @llvm.amdgcn.raw.buffer.atomic.and.i32(i32, <4 x i32>, i32, i32, i32 immarg)
6declare float @llvm.amdgcn.strict.wqm.f32(float)
7
8define amdgpu_ps void @main(i32 %arg) {
9; GFX10-LABEL: main:
10; GFX10:       ; %bb.0: ; %bb
11; GFX10-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 1, v0
12; GFX10-NEXT:    v_mov_b32_e32 v0, 0
13; GFX10-NEXT:    s_mov_b32 s1, exec_lo
14; GFX10-NEXT:    s_mov_b32 s4, 0
15; GFX10-NEXT:    s_mov_b32 s2, 0
16; GFX10-NEXT:    s_branch .LBB0_2
17; GFX10-NEXT:  .LBB0_1: ; %Flow
18; GFX10-NEXT:    ; in Loop: Header=BB0_2 Depth=1
19; GFX10-NEXT:    s_waitcnt_depctr 0xffe3
20; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s3
21; GFX10-NEXT:    s_andn2_b32 exec_lo, exec_lo, s2
22; GFX10-NEXT:    s_cbranch_execz .LBB0_5
23; GFX10-NEXT:  .LBB0_2: ; %bb4
24; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
25; GFX10-NEXT:    s_and_b32 s0, exec_lo, vcc_lo
26; GFX10-NEXT:    s_or_b32 s2, s0, s2
27; GFX10-NEXT:    s_and_saveexec_b32 s3, s1
28; GFX10-NEXT:    s_cbranch_execz .LBB0_1
29; GFX10-NEXT:  ; %bb.3: ; in Loop: Header=BB0_2 Depth=1
30; GFX10-NEXT:    v_mbcnt_lo_u32_b32 v1, exec_lo, 0
31; GFX10-NEXT:    v_cmp_eq_u32_e64 s0, 0, v1
32; GFX10-NEXT:    s_and_b32 exec_lo, exec_lo, s0
33; GFX10-NEXT:    s_cbranch_execz .LBB0_1
34; GFX10-NEXT:  ; %bb.4: ; in Loop: Header=BB0_2 Depth=1
35; GFX10-NEXT:    s_mov_b32 s5, s4
36; GFX10-NEXT:    s_mov_b32 s6, s4
37; GFX10-NEXT:    s_mov_b32 s7, s4
38; GFX10-NEXT:    buffer_atomic_and v0, off, s[4:7], 0
39; GFX10-NEXT:    s_branch .LBB0_1
40; GFX10-NEXT:  .LBB0_5: ; %bb8
41; GFX10-NEXT:    s_or_b32 exec_lo, exec_lo, s2
42; GFX10-NEXT:    s_mov_b32 s0, 0
43; GFX10-NEXT:    v_mov_b32_e32 v1, 0
44; GFX10-NEXT:    v_mov_b32_e32 v0, s0
45; GFX10-NEXT:    exp mrt0 off, off, off, off
46; GFX10-NEXT:    s_endpgm
47bb:
48  br label %bb4
49
50bb4:
51  %i5 = call i32 @llvm.amdgcn.raw.buffer.atomic.and.i32(i32 0, <4 x i32> zeroinitializer, i32 0, i32 0, i32 0)
52  %i7 = icmp eq i32 %arg, 1
53  br i1 %i7, label %bb8, label %bb4
54
55bb8:
56  %i9 = call float @llvm.amdgcn.strict.wqm.f32(float 0.0)
57  call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float %i9, float 0.0, float 0.0, float 0.0, i1 false, i1 false)
58  ret void
59}
60