1; RUN: opt -mtriple=amdgcn--amdhsa -data-layout=A5 -O3 -S -inline-threshold=1 < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-INL1 %s
2; RUN: opt -mtriple=amdgcn--amdhsa -data-layout=A5 -O3 -S < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-INLDEF %s
3
4define coldcc float @foo(float %x, float %y) {
5entry:
6  %cmp = fcmp ogt float %x, 0.000000e+00
7  %div = fdiv float %y, %x
8  %mul = fmul float %x, %y
9  %cond = select i1 %cmp, float %div, float %mul
10  ret float %cond
11}
12
13define coldcc void @foo_private_ptr(float addrspace(5)* nocapture %p) {
14entry:
15  %tmp1 = load float, float addrspace(5)* %p, align 4
16  %cmp = fcmp ogt float %tmp1, 1.000000e+00
17  br i1 %cmp, label %if.then, label %if.end
18
19if.then:                                          ; preds = %entry
20  %div = fdiv float 1.000000e+00, %tmp1
21  store float %div, float addrspace(5)* %p, align 4
22  br label %if.end
23
24if.end:                                           ; preds = %if.then, %entry
25  ret void
26}
27
28define coldcc void @foo_private_ptr2(float addrspace(5)* nocapture %p1, float addrspace(5)* nocapture %p2) {
29entry:
30  %tmp1 = load float, float addrspace(5)* %p1, align 4
31  %div = fdiv float 2.000000e+00, %tmp1
32  store float %div, float addrspace(5)* %p2, align 4
33  ret void
34}
35
36define coldcc float @sin_wrapper(float %x) {
37bb:
38  %call = tail call float @_Z3sinf(float %x)
39  ret float %call
40}
41
42define void @foo_noinline(float addrspace(5)* nocapture %p) #0 {
43entry:
44  %tmp1 = load float, float addrspace(5)* %p, align 4
45  %mul = fmul float %tmp1, 2.000000e+00
46  store float %mul, float addrspace(5)* %p, align 4
47  ret void
48}
49
50; GCN: define amdgpu_kernel void @test_inliner(
51; GCN-INL1:   %c1 = tail call coldcc float @foo(
52; GCN-INLDEF: %cmp.i = fcmp ogt float %tmp2, 0.000000e+00
53; GCN:        %div.i{{[0-9]*}} = fdiv float 1.000000e+00, %c
54; GCN:        %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i
55; GCN:        call void @foo_noinline(
56; GCN:        tail call float @_Z3sinf(
57define amdgpu_kernel void @test_inliner(float addrspace(1)* nocapture %a, i32 %n) {
58entry:
59  %pvt_arr = alloca [64 x float], align 4, addrspace(5)
60  %tid = tail call i32 @llvm.amdgcn.workitem.id.x()
61  %arrayidx = getelementptr inbounds float, float addrspace(1)* %a, i32 %tid
62  %tmp2 = load float, float addrspace(1)* %arrayidx, align 4
63  %add = add i32 %tid, 1
64  %arrayidx2 = getelementptr inbounds float, float addrspace(1)* %a, i32 %add
65  %tmp5 = load float, float addrspace(1)* %arrayidx2, align 4
66  %c1 = tail call coldcc float @foo(float %tmp2, float %tmp5)
67  %or = or i32 %tid, %n
68  %arrayidx5 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 %or
69  store float %c1, float addrspace(5)* %arrayidx5, align 4
70  %arrayidx7 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 %or
71  call coldcc void @foo_private_ptr(float addrspace(5)* %arrayidx7)
72  %arrayidx8 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 1
73  %arrayidx9 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 2
74  call coldcc void @foo_private_ptr2(float addrspace(5)* %arrayidx8, float addrspace(5)* %arrayidx9)
75  call void @foo_noinline(float addrspace(5)* %arrayidx7)
76  %and = and i32 %tid, %n
77  %arrayidx11 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 %and
78  %tmp12 = load float, float addrspace(5)* %arrayidx11, align 4
79  %c2 = call coldcc float @sin_wrapper(float %tmp12)
80  store float %c2, float addrspace(5)* %arrayidx7, align 4
81  %xor = xor i32 %tid, %n
82  %arrayidx16 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 %xor
83  %tmp16 = load float, float addrspace(5)* %arrayidx16, align 4
84  store float %tmp16, float addrspace(1)* %arrayidx, align 4
85  ret void
86}
87
88; GCN: define amdgpu_kernel void @test_inliner_multi_pvt_ptr(
89; GCN: %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i
90define amdgpu_kernel void @test_inliner_multi_pvt_ptr(float addrspace(1)* nocapture %a, i32 %n, float %v) {
91entry:
92  %pvt_arr1 = alloca [32 x float], align 4, addrspace(5)
93  %pvt_arr2 = alloca [32 x float], align 4, addrspace(5)
94  %tid = tail call i32 @llvm.amdgcn.workitem.id.x()
95  %arrayidx = getelementptr inbounds float, float addrspace(1)* %a, i32 %tid
96  %or = or i32 %tid, %n
97  %arrayidx4 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 %or
98  %arrayidx5 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr2, i32 0, i32 %or
99  store float %v, float addrspace(5)* %arrayidx4, align 4
100  store float %v, float addrspace(5)* %arrayidx5, align 4
101  %arrayidx8 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 1
102  %arrayidx9 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr2, i32 0, i32 2
103  call coldcc void @foo_private_ptr2(float addrspace(5)* %arrayidx8, float addrspace(5)* %arrayidx9)
104  %xor = xor i32 %tid, %n
105  %arrayidx15 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 %xor
106  %arrayidx16 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr2, i32 0, i32 %xor
107  %tmp15 = load float, float addrspace(5)* %arrayidx15, align 4
108  %tmp16 = load float, float addrspace(5)* %arrayidx16, align 4
109  %tmp17 = fadd float %tmp15, %tmp16
110  store float %tmp17, float addrspace(1)* %arrayidx, align 4
111  ret void
112}
113
114; GCN: define amdgpu_kernel void @test_inliner_multi_pvt_ptr_cutoff(
115; GCN-INL1:   call coldcc void @foo_private_ptr2
116; GCN-INLDEF: %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i
117define amdgpu_kernel void @test_inliner_multi_pvt_ptr_cutoff(float addrspace(1)* nocapture %a, i32 %n, float %v) {
118entry:
119  %pvt_arr1 = alloca [32 x float], align 4, addrspace(5)
120  %pvt_arr2 = alloca [33 x float], align 4, addrspace(5)
121  %tid = tail call i32 @llvm.amdgcn.workitem.id.x()
122  %arrayidx = getelementptr inbounds float, float addrspace(1)* %a, i32 %tid
123  %or = or i32 %tid, %n
124  %arrayidx4 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 %or
125  %arrayidx5 = getelementptr inbounds [33 x float], [33 x float] addrspace(5)* %pvt_arr2, i32 0, i32 %or
126  store float %v, float addrspace(5)* %arrayidx4, align 4
127  store float %v, float addrspace(5)* %arrayidx5, align 4
128  %arrayidx8 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 1
129  %arrayidx9 = getelementptr inbounds [33 x float], [33 x float] addrspace(5)* %pvt_arr2, i32 0, i32 2
130  call coldcc void @foo_private_ptr2(float addrspace(5)* %arrayidx8, float addrspace(5)* %arrayidx9)
131  %xor = xor i32 %tid, %n
132  %arrayidx15 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 %xor
133  %arrayidx16 = getelementptr inbounds [33 x float], [33 x float] addrspace(5)* %pvt_arr2, i32 0, i32 %xor
134  %tmp15 = load float, float addrspace(5)* %arrayidx15, align 4
135  %tmp16 = load float, float addrspace(5)* %arrayidx16, align 4
136  %tmp17 = fadd float %tmp15, %tmp16
137  store float %tmp17, float addrspace(1)* %arrayidx, align 4
138  ret void
139}
140
141declare i32 @llvm.amdgcn.workitem.id.x() #1
142declare float @_Z3sinf(float) #1
143
144attributes #0 = { noinline }
145attributes #1 = { nounwind readnone }
146