1; RUN: opt -mtriple=amdgcn--amdhsa -data-layout=A5 -O3 -S -inline-threshold=1 < %s | FileCheck -check-prefixes=GCN,GCN-INL1,GCN-MAXBBDEF %s
2; RUN: opt -mtriple=amdgcn--amdhsa -data-layout=A5 -O3 -S < %s | FileCheck -check-prefixes=GCN,GCN-INLDEF,GCN-MAXBBDEF %s
3; RUN: opt -mtriple=amdgcn--amdhsa -data-layout=A5 -passes='default<O3>' -S -inline-threshold=1 < %s | FileCheck -check-prefixes=GCN,GCN-INL1,GCN-MAXBBDEF %s
4; RUN: opt -mtriple=amdgcn--amdhsa -data-layout=A5 -passes='default<O3>' -S < %s | FileCheck -check-prefixes=GCN,GCN-INLDEF,GCN-MAXBBDEF %s
5; RUN: opt -mtriple=amdgcn--amdhsa -data-layout=A5 -passes='default<O3>' -S -amdgpu-inline-max-bb=1 < %s | FileCheck -check-prefixes=GCN,GCN-MAXBB1 %s
6
7define coldcc float @foo(float %x, float %y) {
8entry:
9  %cmp = fcmp ogt float %x, 0.000000e+00
10  %div = fdiv float %y, %x
11  %mul = fmul float %x, %y
12  %cond = select i1 %cmp, float %div, float %mul
13  ret float %cond
14}
15
16define coldcc void @foo_private_ptr(float addrspace(5)* nocapture %p) {
17entry:
18  %tmp1 = load float, float addrspace(5)* %p, align 4
19  %cmp = fcmp ogt float %tmp1, 1.000000e+00
20  br i1 %cmp, label %if.then, label %if.end
21
22if.then:                                          ; preds = %entry
23  %div = fdiv float 1.000000e+00, %tmp1
24  store float %div, float addrspace(5)* %p, align 4
25  br label %if.end
26
27if.end:                                           ; preds = %if.then, %entry
28  ret void
29}
30
31define coldcc void @foo_private_ptr2(float addrspace(5)* nocapture %p1, float addrspace(5)* nocapture %p2) {
32entry:
33  %tmp1 = load float, float addrspace(5)* %p1, align 4
34  %cmp = fcmp ogt float %tmp1, 1.000000e+00
35  br i1 %cmp, label %if.then, label %if.end
36
37if.then:
38  %div = fdiv float 2.000000e+00, %tmp1
39  store float %div, float addrspace(5)* %p2, align 4
40  br label %if.end
41
42if.end:
43  ret void
44}
45
46define float @sin_wrapper(float %x) {
47bb:
48  %call = tail call float @_Z3sinf(float %x)
49  ret float %call
50}
51
52define void @foo_noinline(float addrspace(5)* nocapture %p) #0 {
53entry:
54  %tmp1 = load float, float addrspace(5)* %p, align 4
55  %mul = fmul float %tmp1, 2.000000e+00
56  store float %mul, float addrspace(5)* %p, align 4
57  ret void
58}
59
60; GCN: define amdgpu_kernel void @test_inliner(
61; GCN-INL1:     %c1 = tail call coldcc float @foo(
62; GCN-INLDEF:   %cmp.i = fcmp ogt float %tmp2, 0.000000e+00
63; GCN-MAXBBDEF: %div.i{{[0-9]*}} = fdiv float 1.000000e+00, %c
64; GCN-MAXBBDEF: %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i
65; GCN-MAXBB1:   call coldcc void @foo_private_ptr
66; GCN-MAXBB1:   call coldcc void @foo_private_ptr2
67; GCN:          call void @foo_noinline(
68; GCN:          tail call float @_Z3sinf(
69define amdgpu_kernel void @test_inliner(float addrspace(1)* nocapture %a, i32 %n) {
70entry:
71  %pvt_arr = alloca [64 x float], align 4, addrspace(5)
72  %tid = tail call i32 @llvm.amdgcn.workitem.id.x()
73  %arrayidx = getelementptr inbounds float, float addrspace(1)* %a, i32 %tid
74  %tmp2 = load float, float addrspace(1)* %arrayidx, align 4
75  %add = add i32 %tid, 1
76  %arrayidx2 = getelementptr inbounds float, float addrspace(1)* %a, i32 %add
77  %tmp5 = load float, float addrspace(1)* %arrayidx2, align 4
78  %c1 = tail call coldcc float @foo(float %tmp2, float %tmp5)
79  %or = or i32 %tid, %n
80  %arrayidx5 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 %or
81  store float %c1, float addrspace(5)* %arrayidx5, align 4
82  %arrayidx7 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 %or
83  call coldcc void @foo_private_ptr(float addrspace(5)* %arrayidx7)
84  %arrayidx8 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 1
85  %arrayidx9 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 2
86  call coldcc void @foo_private_ptr2(float addrspace(5)* %arrayidx8, float addrspace(5)* %arrayidx9)
87  call void @foo_noinline(float addrspace(5)* %arrayidx7)
88  %and = and i32 %tid, %n
89  %arrayidx11 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 %and
90  %tmp12 = load float, float addrspace(5)* %arrayidx11, align 4
91  %c2 = call float @sin_wrapper(float %tmp12)
92  store float %c2, float addrspace(5)* %arrayidx7, align 4
93  %xor = xor i32 %tid, %n
94  %arrayidx16 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 %xor
95  %tmp16 = load float, float addrspace(5)* %arrayidx16, align 4
96  store float %tmp16, float addrspace(1)* %arrayidx, align 4
97  ret void
98}
99
100; GCN: define amdgpu_kernel void @test_inliner_multi_pvt_ptr(
101; GCN-MAXBBDEF: %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i
102; GCN-MAXBB1:   call coldcc void @foo_private_ptr2
103define amdgpu_kernel void @test_inliner_multi_pvt_ptr(float addrspace(1)* nocapture %a, i32 %n, float %v) {
104entry:
105  %pvt_arr1 = alloca [32 x float], align 4, addrspace(5)
106  %pvt_arr2 = alloca [32 x float], align 4, addrspace(5)
107  %tid = tail call i32 @llvm.amdgcn.workitem.id.x()
108  %arrayidx = getelementptr inbounds float, float addrspace(1)* %a, i32 %tid
109  %or = or i32 %tid, %n
110  %arrayidx4 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 %or
111  %arrayidx5 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr2, i32 0, i32 %or
112  store float %v, float addrspace(5)* %arrayidx4, align 4
113  store float %v, float addrspace(5)* %arrayidx5, align 4
114  %arrayidx8 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 1
115  %arrayidx9 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr2, i32 0, i32 2
116  call coldcc void @foo_private_ptr2(float addrspace(5)* %arrayidx8, float addrspace(5)* %arrayidx9)
117  %xor = xor i32 %tid, %n
118  %arrayidx15 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 %xor
119  %arrayidx16 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr2, i32 0, i32 %xor
120  %tmp15 = load float, float addrspace(5)* %arrayidx15, align 4
121  %tmp16 = load float, float addrspace(5)* %arrayidx16, align 4
122  %tmp17 = fadd float %tmp15, %tmp16
123  store float %tmp17, float addrspace(1)* %arrayidx, align 4
124  ret void
125}
126
127; GCN: define amdgpu_kernel void @test_inliner_multi_pvt_ptr_cutoff(
128; GCN-INL1:   call coldcc void @foo_private_ptr2
129; GCN-INLDEF: %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i
130define amdgpu_kernel void @test_inliner_multi_pvt_ptr_cutoff(float addrspace(1)* nocapture %a, i32 %n, float %v) {
131entry:
132  %pvt_arr1 = alloca [32 x float], align 4, addrspace(5)
133  %pvt_arr2 = alloca [33 x float], align 4, addrspace(5)
134  %tid = tail call i32 @llvm.amdgcn.workitem.id.x()
135  %arrayidx = getelementptr inbounds float, float addrspace(1)* %a, i32 %tid
136  %or = or i32 %tid, %n
137  %arrayidx4 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 %or
138  %arrayidx5 = getelementptr inbounds [33 x float], [33 x float] addrspace(5)* %pvt_arr2, i32 0, i32 %or
139  store float %v, float addrspace(5)* %arrayidx4, align 4
140  store float %v, float addrspace(5)* %arrayidx5, align 4
141  %arrayidx8 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 1
142  %arrayidx9 = getelementptr inbounds [33 x float], [33 x float] addrspace(5)* %pvt_arr2, i32 0, i32 2
143  call coldcc void @foo_private_ptr2(float addrspace(5)* %arrayidx8, float addrspace(5)* %arrayidx9)
144  %xor = xor i32 %tid, %n
145  %arrayidx15 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 %xor
146  %arrayidx16 = getelementptr inbounds [33 x float], [33 x float] addrspace(5)* %pvt_arr2, i32 0, i32 %xor
147  %tmp15 = load float, float addrspace(5)* %arrayidx15, align 4
148  %tmp16 = load float, float addrspace(5)* %arrayidx16, align 4
149  %tmp17 = fadd float %tmp15, %tmp16
150  store float %tmp17, float addrspace(1)* %arrayidx, align 4
151  ret void
152}
153
154; GCN: define amdgpu_kernel void @test_inliner_maxbb_singlebb(
155; GCN: tail call float @_Z3sinf
156define amdgpu_kernel void @test_inliner_maxbb_singlebb(float addrspace(1)* nocapture %a, i32 %n) {
157entry:
158  %cmp = icmp eq i32 %n, 1
159  br i1 %cmp, label %bb.1, label %bb.2
160  br label %bb.1
161
162bb.1:
163  store float 1.0, float* undef
164  br label %bb.2
165
166bb.2:
167  %c = call float @sin_wrapper(float 1.0)
168  store float %c, float addrspace(1)* %a
169  ret void
170}
171
172declare i32 @llvm.amdgcn.workitem.id.x() #1
173declare float @_Z3sinf(float) #1
174
175attributes #0 = { noinline }
176attributes #1 = { nounwind readnone }
177