1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -verify-machineinstrs -o - < %s | FileCheck %s --check-prefixes=GFX,GFX6
3; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -verify-machineinstrs -o - < %s | FileCheck %s --check-prefixes=GFX,GFX8
4
5declare i16 @llvm.abs.i16(i16, i1)
6declare i32 @llvm.abs.i32(i32, i1)
7declare i64 @llvm.abs.i64(i64, i1)
8declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)
9
10define amdgpu_cs i16 @abs_sgpr_i16(i16 inreg %arg) {
11; GFX-LABEL: abs_sgpr_i16:
12; GFX:       ; %bb.0:
13; GFX-NEXT:    s_sext_i32_i16 s0, s0
14; GFX-NEXT:    s_abs_i32 s0, s0
15; GFX-NEXT:    ; return to shader part epilog
16  %res = call i16 @llvm.abs.i16(i16 %arg, i1 false)
17  ret i16 %res
18}
19
20define amdgpu_cs i32 @abs_sgpr_i32(i32 inreg %arg) {
21; GFX-LABEL: abs_sgpr_i32:
22; GFX:       ; %bb.0:
23; GFX-NEXT:    s_abs_i32 s0, s0
24; GFX-NEXT:    ; return to shader part epilog
25  %res = call i32 @llvm.abs.i32(i32 %arg, i1 false)
26  ret i32 %res
27}
28
29define amdgpu_cs i64 @abs_sgpr_i64(i64 inreg %arg) {
30; GFX-LABEL: abs_sgpr_i64:
31; GFX:       ; %bb.0:
32; GFX-NEXT:    s_ashr_i32 s2, s1, 31
33; GFX-NEXT:    s_add_u32 s0, s0, s2
34; GFX-NEXT:    s_cselect_b32 s4, 1, 0
35; GFX-NEXT:    s_and_b32 s4, s4, 1
36; GFX-NEXT:    s_cmp_lg_u32 s4, 0
37; GFX-NEXT:    s_mov_b32 s3, s2
38; GFX-NEXT:    s_addc_u32 s1, s1, s2
39; GFX-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
40; GFX-NEXT:    ; return to shader part epilog
41  %res = call i64 @llvm.abs.i64(i64 %arg, i1 false)
42  ret i64 %res
43}
44
45define amdgpu_cs <4 x i32> @abs_sgpr_v4i32(<4 x i32> inreg %arg) {
46; GFX-LABEL: abs_sgpr_v4i32:
47; GFX:       ; %bb.0:
48; GFX-NEXT:    s_abs_i32 s0, s0
49; GFX-NEXT:    s_abs_i32 s1, s1
50; GFX-NEXT:    s_abs_i32 s2, s2
51; GFX-NEXT:    s_abs_i32 s3, s3
52; GFX-NEXT:    ; return to shader part epilog
53  %res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %arg, i1 false)
54  ret <4 x i32> %res
55}
56
57define amdgpu_cs i16 @abs_vgpr_i16(i16 %arg) {
58; GFX6-LABEL: abs_vgpr_i16:
59; GFX6:       ; %bb.0:
60; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 16
61; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, 0, v0
62; GFX6-NEXT:    v_max_i32_e32 v0, v0, v1
63; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
64; GFX6-NEXT:    ; return to shader part epilog
65;
66; GFX8-LABEL: abs_vgpr_i16:
67; GFX8:       ; %bb.0:
68; GFX8-NEXT:    v_sub_u16_e32 v1, 0, v0
69; GFX8-NEXT:    v_max_i16_e32 v0, v0, v1
70; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
71; GFX8-NEXT:    ; return to shader part epilog
72  %res = call i16 @llvm.abs.i16(i16 %arg, i1 false)
73  ret i16 %res
74}
75
76define amdgpu_cs i32 @abs_vgpr_i32(i32 %arg) {
77; GFX6-LABEL: abs_vgpr_i32:
78; GFX6:       ; %bb.0:
79; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, 0, v0
80; GFX6-NEXT:    v_max_i32_e32 v0, v0, v1
81; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
82; GFX6-NEXT:    ; return to shader part epilog
83;
84; GFX8-LABEL: abs_vgpr_i32:
85; GFX8:       ; %bb.0:
86; GFX8-NEXT:    v_sub_u32_e32 v1, vcc, 0, v0
87; GFX8-NEXT:    v_max_i32_e32 v0, v0, v1
88; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
89; GFX8-NEXT:    ; return to shader part epilog
90  %res = call i32 @llvm.abs.i32(i32 %arg, i1 false)
91  ret i32 %res
92}
93
94define amdgpu_cs i64 @abs_vgpr_i64(i64 %arg) {
95; GFX6-LABEL: abs_vgpr_i64:
96; GFX6:       ; %bb.0:
97; GFX6-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
98; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
99; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
100; GFX6-NEXT:    v_xor_b32_e32 v0, v0, v2
101; GFX6-NEXT:    v_xor_b32_e32 v1, v1, v2
102; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
103; GFX6-NEXT:    v_readfirstlane_b32 s1, v1
104; GFX6-NEXT:    ; return to shader part epilog
105;
106; GFX8-LABEL: abs_vgpr_i64:
107; GFX8:       ; %bb.0:
108; GFX8-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
109; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
110; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
111; GFX8-NEXT:    v_xor_b32_e32 v0, v0, v2
112; GFX8-NEXT:    v_xor_b32_e32 v1, v1, v2
113; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
114; GFX8-NEXT:    v_readfirstlane_b32 s1, v1
115; GFX8-NEXT:    ; return to shader part epilog
116  %res = call i64 @llvm.abs.i64(i64 %arg, i1 false)
117  ret i64 %res
118}
119
120define amdgpu_cs <4 x i32> @abs_vgpr_v4i32(<4 x i32> %arg) {
121; GFX6-LABEL: abs_vgpr_v4i32:
122; GFX6:       ; %bb.0:
123; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
124; GFX6-NEXT:    v_max_i32_e32 v0, v0, v4
125; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 0, v1
126; GFX6-NEXT:    v_max_i32_e32 v1, v1, v4
127; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 0, v2
128; GFX6-NEXT:    v_max_i32_e32 v2, v2, v4
129; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
130; GFX6-NEXT:    v_max_i32_e32 v3, v3, v4
131; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
132; GFX6-NEXT:    v_readfirstlane_b32 s1, v1
133; GFX6-NEXT:    v_readfirstlane_b32 s2, v2
134; GFX6-NEXT:    v_readfirstlane_b32 s3, v3
135; GFX6-NEXT:    ; return to shader part epilog
136;
137; GFX8-LABEL: abs_vgpr_v4i32:
138; GFX8:       ; %bb.0:
139; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 0, v0
140; GFX8-NEXT:    v_max_i32_e32 v0, v0, v4
141; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 0, v1
142; GFX8-NEXT:    v_max_i32_e32 v1, v1, v4
143; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 0, v2
144; GFX8-NEXT:    v_max_i32_e32 v2, v2, v4
145; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 0, v3
146; GFX8-NEXT:    v_max_i32_e32 v3, v3, v4
147; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
148; GFX8-NEXT:    v_readfirstlane_b32 s1, v1
149; GFX8-NEXT:    v_readfirstlane_b32 s2, v2
150; GFX8-NEXT:    v_readfirstlane_b32 s3, v3
151; GFX8-NEXT:    ; return to shader part epilog
152  %res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %arg, i1 false)
153  ret <4 x i32> %res
154}
155