1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -verify-machineinstrs -o - < %s | FileCheck %s --check-prefixes=GFX,GFX6
3; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -verify-machineinstrs -o - < %s | FileCheck %s --check-prefixes=GFX,GFX8
4
5declare i16 @llvm.abs.i16(i16, i1)
6declare i32 @llvm.abs.i32(i32, i1)
7declare i64 @llvm.abs.i64(i64, i1)
8declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)
9
10define amdgpu_cs i16 @abs_sgpr_i16(i16 inreg %arg) {
11; GFX-LABEL: abs_sgpr_i16:
12; GFX:       ; %bb.0:
13; GFX-NEXT:    s_sext_i32_i16 s0, s0
14; GFX-NEXT:    s_abs_i32 s0, s0
15; GFX-NEXT:    ; return to shader part epilog
16  %res = call i16 @llvm.abs.i16(i16 %arg, i1 false)
17  ret i16 %res
18}
19
20define amdgpu_cs i32 @abs_sgpr_i32(i32 inreg %arg) {
21; GFX-LABEL: abs_sgpr_i32:
22; GFX:       ; %bb.0:
23; GFX-NEXT:    s_abs_i32 s0, s0
24; GFX-NEXT:    ; return to shader part epilog
25  %res = call i32 @llvm.abs.i32(i32 %arg, i1 false)
26  ret i32 %res
27}
28
29define amdgpu_cs i64 @abs_sgpr_i64(i64 inreg %arg) {
30; GFX-LABEL: abs_sgpr_i64:
31; GFX:       ; %bb.0:
32; GFX-NEXT:    s_ashr_i32 s2, s1, 31
33; GFX-NEXT:    s_add_u32 s0, s0, s2
34; GFX-NEXT:    s_mov_b32 s3, s2
35; GFX-NEXT:    s_addc_u32 s1, s1, s2
36; GFX-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
37; GFX-NEXT:    ; return to shader part epilog
38  %res = call i64 @llvm.abs.i64(i64 %arg, i1 false)
39  ret i64 %res
40}
41
42define amdgpu_cs <4 x i32> @abs_sgpr_v4i32(<4 x i32> inreg %arg) {
43; GFX-LABEL: abs_sgpr_v4i32:
44; GFX:       ; %bb.0:
45; GFX-NEXT:    s_abs_i32 s0, s0
46; GFX-NEXT:    s_abs_i32 s1, s1
47; GFX-NEXT:    s_abs_i32 s2, s2
48; GFX-NEXT:    s_abs_i32 s3, s3
49; GFX-NEXT:    ; return to shader part epilog
50  %res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %arg, i1 false)
51  ret <4 x i32> %res
52}
53
54define amdgpu_cs i16 @abs_vgpr_i16(i16 %arg) {
55; GFX6-LABEL: abs_vgpr_i16:
56; GFX6:       ; %bb.0:
57; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 16
58; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, 0, v0
59; GFX6-NEXT:    v_max_i32_e32 v0, v0, v1
60; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
61; GFX6-NEXT:    ; return to shader part epilog
62;
63; GFX8-LABEL: abs_vgpr_i16:
64; GFX8:       ; %bb.0:
65; GFX8-NEXT:    v_sub_u16_e32 v1, 0, v0
66; GFX8-NEXT:    v_max_i16_e32 v0, v0, v1
67; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
68; GFX8-NEXT:    ; return to shader part epilog
69  %res = call i16 @llvm.abs.i16(i16 %arg, i1 false)
70  ret i16 %res
71}
72
73define amdgpu_cs i32 @abs_vgpr_i32(i32 %arg) {
74; GFX6-LABEL: abs_vgpr_i32:
75; GFX6:       ; %bb.0:
76; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, 0, v0
77; GFX6-NEXT:    v_max_i32_e32 v0, v0, v1
78; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
79; GFX6-NEXT:    ; return to shader part epilog
80;
81; GFX8-LABEL: abs_vgpr_i32:
82; GFX8:       ; %bb.0:
83; GFX8-NEXT:    v_sub_u32_e32 v1, vcc, 0, v0
84; GFX8-NEXT:    v_max_i32_e32 v0, v0, v1
85; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
86; GFX8-NEXT:    ; return to shader part epilog
87  %res = call i32 @llvm.abs.i32(i32 %arg, i1 false)
88  ret i32 %res
89}
90
91define amdgpu_cs i64 @abs_vgpr_i64(i64 %arg) {
92; GFX6-LABEL: abs_vgpr_i64:
93; GFX6:       ; %bb.0:
94; GFX6-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
95; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
96; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
97; GFX6-NEXT:    v_xor_b32_e32 v0, v0, v2
98; GFX6-NEXT:    v_xor_b32_e32 v1, v1, v2
99; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
100; GFX6-NEXT:    v_readfirstlane_b32 s1, v1
101; GFX6-NEXT:    ; return to shader part epilog
102;
103; GFX8-LABEL: abs_vgpr_i64:
104; GFX8:       ; %bb.0:
105; GFX8-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
106; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
107; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
108; GFX8-NEXT:    v_xor_b32_e32 v0, v0, v2
109; GFX8-NEXT:    v_xor_b32_e32 v1, v1, v2
110; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
111; GFX8-NEXT:    v_readfirstlane_b32 s1, v1
112; GFX8-NEXT:    ; return to shader part epilog
113  %res = call i64 @llvm.abs.i64(i64 %arg, i1 false)
114  ret i64 %res
115}
116
117define amdgpu_cs <4 x i32> @abs_vgpr_v4i32(<4 x i32> %arg) {
118; GFX6-LABEL: abs_vgpr_v4i32:
119; GFX6:       ; %bb.0:
120; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
121; GFX6-NEXT:    v_max_i32_e32 v0, v0, v4
122; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 0, v1
123; GFX6-NEXT:    v_max_i32_e32 v1, v1, v4
124; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 0, v2
125; GFX6-NEXT:    v_max_i32_e32 v2, v2, v4
126; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
127; GFX6-NEXT:    v_max_i32_e32 v3, v3, v4
128; GFX6-NEXT:    v_readfirstlane_b32 s0, v0
129; GFX6-NEXT:    v_readfirstlane_b32 s1, v1
130; GFX6-NEXT:    v_readfirstlane_b32 s2, v2
131; GFX6-NEXT:    v_readfirstlane_b32 s3, v3
132; GFX6-NEXT:    ; return to shader part epilog
133;
134; GFX8-LABEL: abs_vgpr_v4i32:
135; GFX8:       ; %bb.0:
136; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 0, v0
137; GFX8-NEXT:    v_max_i32_e32 v0, v0, v4
138; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 0, v1
139; GFX8-NEXT:    v_max_i32_e32 v1, v1, v4
140; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 0, v2
141; GFX8-NEXT:    v_max_i32_e32 v2, v2, v4
142; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 0, v3
143; GFX8-NEXT:    v_max_i32_e32 v3, v3, v4
144; GFX8-NEXT:    v_readfirstlane_b32 s0, v0
145; GFX8-NEXT:    v_readfirstlane_b32 s1, v1
146; GFX8-NEXT:    v_readfirstlane_b32 s2, v2
147; GFX8-NEXT:    v_readfirstlane_b32 s3, v3
148; GFX8-NEXT:    ; return to shader part epilog
149  %res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %arg, i1 false)
150  ret <4 x i32> %res
151}
152